diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
51 files changed, 44614 insertions, 42199 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 213dc1867..fc255dc72 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,135 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.902739 # Number of seconds simulated -sim_ticks 1902738973500 # Number of ticks simulated -final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904665 # Number of seconds simulated +sim_ticks 1904665099500 # Number of ticks simulated +final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132013 # Simulator instruction rate (inst/s) -host_op_rate 132013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4427958303 # Simulator tick rate (ticks/s) -host_mem_usage 313120 # Number of bytes of host memory used -host_seconds 429.71 # Real time elapsed on the host -sim_insts 56727331 # Number of instructions simulated -sim_ops 56727331 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24806400 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 74944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 436992 # Number of bytes read from this memory -system.physmem.bytes_read::total 28869696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 900544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 74944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 975488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7821440 # Number of bytes written to this memory -system.physmem.bytes_written::total 7821440 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387600 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122210 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122210 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 473288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13037206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1393158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 39387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 229665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15172704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 473288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 39387 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4110622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4110622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4110622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 473288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13037206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1393158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 39387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 229665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19283326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451089 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 122210 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 451089 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 122210 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28869696 # Total number of bytes read from memory -system.physmem.bytesWritten 7821440 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28869696 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7821440 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4926 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28357 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7885 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7637 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6924 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 6873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7305 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7954 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8091 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7908 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1902738952500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451089 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 122210 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +host_inst_rate 126318 # Simulator instruction rate (inst/s) +host_op_rate 126318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4285588150 # Simulator tick rate (ticks/s) +host_mem_usage 339596 # Number of bytes of host memory used +host_seconds 444.44 # Real time elapsed on the host +sim_insts 56140339 # Number of instructions simulated +sim_ops 56140339 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory +system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory +system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450624 # Number of read requests accepted +system.physmem.writeReqs 122060 # Number of write requests accepted +system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue +system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28171 # Per bank write bursts +system.physmem.perBankRdBursts::1 27944 # Per bank write bursts +system.physmem.perBankRdBursts::2 28133 # Per bank write bursts +system.physmem.perBankRdBursts::3 27978 # Per bank write bursts +system.physmem.perBankRdBursts::4 27881 # Per bank write bursts +system.physmem.perBankRdBursts::5 28082 # Per bank write bursts +system.physmem.perBankRdBursts::6 28123 # Per bank write bursts +system.physmem.perBankRdBursts::7 28118 # Per bank write bursts +system.physmem.perBankRdBursts::8 28377 # Per bank write bursts +system.physmem.perBankRdBursts::9 28284 # Per bank write bursts +system.physmem.perBankRdBursts::10 27947 # Per bank write bursts +system.physmem.perBankRdBursts::11 28190 # Per bank write bursts +system.physmem.perBankRdBursts::12 28259 # Per bank write bursts +system.physmem.perBankRdBursts::13 28280 # Per bank write bursts +system.physmem.perBankRdBursts::14 28300 # Per bank write bursts +system.physmem.perBankRdBursts::15 28502 # Per bank write bursts +system.physmem.perBankWrBursts::0 7913 # Per bank write bursts +system.physmem.perBankWrBursts::1 7477 # Per bank write bursts +system.physmem.perBankWrBursts::2 7607 # Per bank write bursts +system.physmem.perBankWrBursts::3 7420 # Per bank write bursts +system.physmem.perBankWrBursts::4 7384 # Per bank write bursts +system.physmem.perBankWrBursts::5 7571 # Per bank write bursts +system.physmem.perBankWrBursts::6 7682 # Per bank write bursts +system.physmem.perBankWrBursts::7 7471 # Per bank write bursts +system.physmem.perBankWrBursts::8 7660 # Per bank write bursts +system.physmem.perBankWrBursts::9 7641 # Per bank write bursts +system.physmem.perBankWrBursts::10 7379 # Per bank write bursts +system.physmem.perBankWrBursts::11 7517 # Per bank write bursts +system.physmem.perBankWrBursts::12 7673 # Per bank write bursts +system.physmem.perBankWrBursts::13 7762 # Per bank write bursts +system.physmem.perBankWrBursts::14 7923 # Per bank write bursts +system.physmem.perBankWrBursts::15 7975 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1904663535000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 450624 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 122060 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 322714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -139,396 +141,458 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 906.491388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 223.789110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2353.116019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14451 35.71% 35.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6072 15.00% 50.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3826 9.45% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2468 6.10% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1670 4.13% 70.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1520 3.76% 74.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1058 2.61% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 819 2.02% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 687 1.70% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 564 1.39% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 556 1.37% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 509 1.26% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 268 0.66% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 232 0.57% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 203 0.50% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 288 0.71% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 119 0.29% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 109 0.27% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 110 0.27% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 196 0.48% 88.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 119 0.29% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 500 1.24% 90.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 628 1.55% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 91 0.22% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 33 0.08% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 99 0.24% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 30 0.07% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 12 0.03% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 48 0.12% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 23 0.06% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 33 0.08% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 7 0.02% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 3 0.01% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.00% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2429 6.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 243 0.60% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40469 # Bytes accessed per row activation -system.physmem.totQLat 6403559750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13868349750 # Sum of mem lat for all requests -system.physmem.totBusLat 2255080000 # Total cycles spent in databus access -system.physmem.totBankLat 5209710000 # Total cycles spent in bank access -system.physmem.avgQLat 14198.08 # Average queueing delay per request -system.physmem.avgBankLat 11551.05 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30749.13 # Average memory access latency -system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 55 0.12% 94.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 21 0.05% 94.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 49 0.11% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 50 0.11% 94.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 11 0.02% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 26 0.06% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 38 0.08% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 26 0.06% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 54 0.12% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 52 0.11% 95.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 22 0.05% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 49 0.11% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 39 0.08% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 31 0.07% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 44 0.09% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 9 0.02% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 51 0.11% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 50 0.11% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 23 0.05% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 20 0.04% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 23 0.05% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 51 0.11% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 49 0.11% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 7 0.02% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 28 0.06% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 86 0.19% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 45 0.10% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 319 0.69% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 8 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 15 0.03% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 7 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 319 0.69% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation +system.physmem.totQLat 8608105750 # Total ticks spent queuing +system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks +system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.36 # Average write queue length over time -system.physmem.readRowHits 435126 # Number of row buffer hits during reads -system.physmem.writeRowHits 97620 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.88 # Row buffer hit rate for writes -system.physmem.avgGap 3318929.48 # Average gap between requests -system.membus.throughput 19341454 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296468 # Transaction distribution -system.membus.trans_dist::ReadResp 296394 # Transaction distribution -system.membus.trans_dist::WriteReq 13061 # Transaction distribution -system.membus.trans_dist::WriteResp 13061 # Transaction distribution -system.membus.trans_dist::Writeback 122210 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9880 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5735 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4929 # Transaction distribution -system.membus.trans_dist::ReadExReq 162867 # Transaction distribution -system.membus.trans_dist::ReadExResp 162463 # Transaction distribution -system.membus.trans_dist::BadAddressError 74 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921241 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 961899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1086565 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73866 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31383040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31456906 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36765002 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36765002 # Total data (bytes) -system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37911498 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing +system.physmem.readRowHits 429097 # Number of row buffer hits during reads +system.physmem.writeRowHits 97193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes +system.physmem.avgGap 3325854.28 # Average gap between requests +system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19299112 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296504 # Transaction distribution +system.membus.trans_dist::ReadResp 296255 # Transaction distribution +system.membus.trans_dist::WriteReq 12358 # Transaction distribution +system.membus.trans_dist::WriteResp 12358 # Transaction distribution +system.membus.trans_dist::Writeback 122060 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution +system.membus.trans_dist::ReadExReq 162296 # Transaction distribution +system.membus.trans_dist::ReadExResp 162161 # Transaction distribution +system.membus.trans_dist::BadAddressError 249 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36720010 # Total data (bytes) +system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1609327499 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 93500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3831145563 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376230495 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 344151 # number of replacements -system.l2c.tags.tagsinuse 65253.870311 # Cycle average of tags in use -system.l2c.tags.total_refs 2581362 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409161 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.308915 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53541.051154 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5362.839741 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6144.208257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 141.383324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 64.387836 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816972 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081830 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093753 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002157 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000982 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995695 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 862836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 735075 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 214357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 69353 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1881621 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822225 # number of Writeback hits -system.l2c.Writeback_hits::total 822225 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 270 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 439 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 153625 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26073 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179698 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 862836 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 888700 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 214357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 95426 # number of demand (read+write) hits -system.l2c.demand_hits::total 2061319 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 862836 # number of overall hits -system.l2c.overall_hits::cpu0.data 888700 # number of overall hits -system.l2c.overall_hits::cpu1.inst 214357 # number of overall hits -system.l2c.overall_hits::cpu1.data 95426 # number of overall hits -system.l2c.overall_hits::total 2061319 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14080 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273430 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1180 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 427 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2676 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1075 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3751 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 425 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 454 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 879 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114757 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6453 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121210 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14080 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 388187 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1180 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6880 # number of demand (read+write) misses -system.l2c.demand_misses::total 410327 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14080 # number of overall misses -system.l2c.overall_misses::cpu0.data 388187 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1180 # number of overall misses -system.l2c.overall_misses::cpu1.data 6880 # number of overall misses -system.l2c.overall_misses::total 410327 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1210878995 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17193583984 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 109764250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 37725999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18551953228 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1076463 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4839759 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 5916222 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 977458 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 93496 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1070954 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9311235979 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 722690467 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10033926446 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1210878995 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26504819963 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 109764250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 760416466 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 28585879674 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1210878995 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26504819963 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 109764250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 760416466 # number of overall miss cycles -system.l2c.overall_miss_latency::total 28585879674 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 876916 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1008505 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 215537 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 69780 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2170738 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 822225 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 822225 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2845 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1345 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4190 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 468 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 479 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 947 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 268382 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 32526 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300908 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 876916 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1276887 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 215537 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 102306 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2471646 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 876916 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1276887 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 215537 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 102306 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2471646 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016056 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.271124 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005475 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006119 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133188 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940598 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.799257 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.895227 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.908120 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947808 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.928194 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.427588 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.198395 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.402814 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016056 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.304010 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005475 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.067249 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.166014 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016056 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.304010 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005475 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.067249 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.166014 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85999.928622 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 62881.117595 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 93020.550847 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88351.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 64167.631886 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 402.265695 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4502.101395 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1577.238603 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2299.901176 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 205.938326 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1218.377702 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81138.719024 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 111992.943902 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 82781.341853 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 85999.928622 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 68278.484243 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 93020.550847 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 110525.649128 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69666.094783 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 85999.928622 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 68278.484243 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 93020.550847 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 110525.649128 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69666.094783 # average overall miss latency +system.l2c.tags.replacements 343738 # number of replacements +system.l2c.tags.tagsinuse 65291.635140 # Cycle average of tags in use +system.l2c.tags.total_refs 2609074 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408707 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.383727 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53622.087129 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4120.650208 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5604.001242 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1368.077401 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 576.819161 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.818208 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.085510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.020875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008802 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 744945 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 568804 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 325372 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 253262 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1892383 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 840158 # number of Writeback hits +system.l2c.Writeback_hits::total 840158 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 143496 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 47101 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 190597 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 744945 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 712300 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 325372 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 300363 # number of demand (read+write) hits +system.l2c.demand_hits::total 2082980 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 744945 # number of overall hits +system.l2c.overall_hits::cpu0.data 712300 # number of overall hits +system.l2c.overall_hits::cpu1.inst 325372 # number of overall hits +system.l2c.overall_hits::cpu1.data 300363 # number of overall hits +system.l2c.overall_hits::total 2082980 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11483 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272043 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3807 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1819 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2542 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 549 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3091 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 55 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 155 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 106452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120772 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11483 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 378495 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3807 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16139 # number of demand (read+write) misses +system.l2c.demand_misses::total 409924 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11483 # number of overall misses +system.l2c.overall_misses::cpu0.data 378495 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3807 # number of overall misses +system.l2c.overall_misses::cpu1.data 16139 # number of overall misses +system.l2c.overall_misses::total 409924 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 923162249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17695673499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 318789981 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 142364996 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19079990725 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 555479 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1281945 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1837424 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 201494 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 69497 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 270991 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8670131391 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1451250197 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10121381588 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 923162249 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 26365804890 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 318789981 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1593615193 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 29201372313 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 923162249 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 26365804890 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 318789981 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1593615193 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29201372313 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 756428 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 840847 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 329179 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 255081 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2181535 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 840158 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 840158 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2683 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 636 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3319 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 90 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 131 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 221 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 249948 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 61421 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 311369 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 756428 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1090795 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 329179 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 316502 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2492904 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 756428 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1090795 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 329179 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 316502 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2492904 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.323534 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011565 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007131 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132545 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947447 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.863208 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.931305 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.611111 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.763359 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.701357 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.425897 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.233145 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.387874 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015181 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.346990 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011565 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.050992 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.164436 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015181 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.346990 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011565 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.050992 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.164436 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.821214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 65047.339939 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83737.846336 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78265.528312 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 65986.023700 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 218.520456 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2335.054645 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 594.443222 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3663.527273 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 694.970000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1748.329032 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81446.392656 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101344.287500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 83805.696585 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71236.064034 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71236.064034 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,125 +601,125 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80690 # number of writebacks -system.l2c.writebacks::total 80690 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 80540 # number of writebacks +system.l2c.writebacks::total 80540 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 14072 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273429 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1171 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 427 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289099 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2676 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1075 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3751 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 425 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 454 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 879 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114757 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6453 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121210 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 14072 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 388186 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1171 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6880 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 410309 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 14072 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 388186 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1171 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6880 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 410309 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1031878505 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13784019266 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 94337500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 32390501 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 14942625772 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26984633 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10773037 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 37757670 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4256416 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4544453 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 8800869 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7896551021 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 642755533 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8539306554 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1031878505 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21680570287 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 94337500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 675146034 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 23481932326 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1031878505 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21680570287 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 94337500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 675146034 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 23481932326 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367321000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22027000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389348000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2025100000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 585946999 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2611046999 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3392421000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 607973999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4000394999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271123 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006119 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.133180 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940598 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.799257 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.895227 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.908120 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947808 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.928194 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.427588 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198395 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.402814 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.304010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.067249 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.166006 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.304010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.067249 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.166006 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50411.694685 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75855.974239 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 51686.881560 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10083.943572 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.429767 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.027726 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.096471 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.808370 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.365188 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68811.061818 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99605.692391 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70450.511954 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 11476 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272042 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3797 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1819 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2542 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 549 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3091 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 55 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 155 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 106452 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14320 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 120772 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 11476 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 378494 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3797 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 16139 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 409906 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 11476 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 378494 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3797 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 16139 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 409906 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 777853501 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14301350001 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270265519 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 144194502 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15493663523 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25563003 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5558045 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 31121048 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 600552 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1003598 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1604150 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7364952609 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1275013301 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8639965910 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 777853501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 21666302610 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 270265519 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1419207803 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24133629433 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 777853501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 21666302610 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 270265519 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1419207803 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24133629433 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929130500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460152500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389283000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1572515500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890654999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2463170499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2501646000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350807499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3852453499 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.323533 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007131 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132537 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.947447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.863208 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.931305 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.611111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.763359 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.701357 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425897 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.233145 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.387874 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164429 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164429 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52570.375166 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79271.304013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53586.446156 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.256098 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10123.943534 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.278227 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10919.127273 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.980000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10349.354839 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69185.666864 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89037.241690 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71539.478604 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -666,39 +730,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.476417 # Cycle average of tags in use +system.iocache.tags.replacements 41697 # number of replacements +system.iocache.tags.tagsinuse 0.224170 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.476417 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029776 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029776 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.warmup_cycle 1712302770000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.224170 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.014011 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.014011 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21570383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21570383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10493964012 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10493964012 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10515534395 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10515534395 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10515534395 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10515534395 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -707,40 +771,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123259.331429 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123259.331429 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252550.154313 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 252550.154313 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 252007.918015 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 252007.918015 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 275771 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27285 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.107055 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12468883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8331886522 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8331886522 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8344355405 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8344355405 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8344355405 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8344355405 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -749,14 +813,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71250.760000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71250.760000 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200517.099586 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 200517.099586 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -770,35 +834,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12458299 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10491650 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 332886 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8054816 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5283733 # Number of BTB hits +system.cpu0.branchPred.lookups 10889682 # Number of BP lookups +system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.597191 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 799392 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28656 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8872852 # DTB read hits -system.cpu0.dtb.read_misses 32010 # DTB read misses -system.cpu0.dtb.read_acv 540 # DTB read access violations -system.cpu0.dtb.read_accesses 628428 # DTB read accesses -system.cpu0.dtb.write_hits 5797852 # DTB write hits -system.cpu0.dtb.write_misses 8130 # DTB write misses -system.cpu0.dtb.write_acv 348 # DTB write access violations -system.cpu0.dtb.write_accesses 210128 # DTB write accesses -system.cpu0.dtb.data_hits 14670704 # DTB hits -system.cpu0.dtb.data_misses 40140 # DTB misses -system.cpu0.dtb.data_acv 888 # DTB access violations -system.cpu0.dtb.data_accesses 838556 # DTB accesses -system.cpu0.itb.fetch_hits 994919 # ITB hits -system.cpu0.itb.fetch_misses 28800 # ITB misses -system.cpu0.itb.fetch_acv 922 # ITB acv -system.cpu0.itb.fetch_accesses 1023719 # ITB accesses +system.cpu0.dtb.read_hits 7794998 # DTB read hits +system.cpu0.dtb.read_misses 29740 # DTB read misses +system.cpu0.dtb.read_acv 552 # DTB read access violations +system.cpu0.dtb.read_accesses 624038 # DTB read accesses +system.cpu0.dtb.write_hits 5176736 # DTB write hits +system.cpu0.dtb.write_misses 7776 # DTB write misses +system.cpu0.dtb.write_acv 327 # DTB write access violations +system.cpu0.dtb.write_accesses 207382 # DTB write accesses +system.cpu0.dtb.data_hits 12971734 # DTB hits +system.cpu0.dtb.data_misses 37516 # DTB misses +system.cpu0.dtb.data_acv 879 # DTB access violations +system.cpu0.dtb.data_accesses 831420 # DTB accesses +system.cpu0.itb.fetch_hits 929400 # ITB hits +system.cpu0.itb.fetch_misses 28175 # ITB misses +system.cpu0.itb.fetch_acv 908 # ITB acv +system.cpu0.itb.fetch_accesses 957575 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -811,269 +875,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 114636003 # number of cpu cycles simulated +system.cpu0.numCycles 103787820 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25048083 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63888139 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12458299 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6083125 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12009946 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1716539 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37364333 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31995 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 196940 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 358937 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 467 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7724257 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 222992 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76114982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177033 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64105036 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 766655 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1565630 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 705022 0.93% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2586372 3.40% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 523946 0.69% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578047 0.76% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 832534 1.09% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4451740 5.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76114982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.108677 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.557313 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26317520 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36878715 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10917325 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 932522 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1068899 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 511897 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35733 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62704701 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 106993 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1068899 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27334042 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 15040257 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18326535 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10227103 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4118144 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59323627 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7153 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 638131 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72093935 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 128190 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 211881 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11242711 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9290886 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6078694 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1146384 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 744084 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52609114 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1811011 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51412755 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 100173 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5939256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3114263 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1226583 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76114982 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.675462 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.326460 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53279780 70.00% 70.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10372988 13.63% 83.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4693410 6.17% 89.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3092664 4.06% 93.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2443569 3.21% 97.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1213853 1.59% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 652140 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 314050 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52528 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76114982 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82827 12.15% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 318873 46.78% 58.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 279966 41.07% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35420825 68.90% 68.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56384 0.11% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15702 0.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9231506 17.96% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5866326 11.41% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 816348 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51412755 # Type of FU issued -system.cpu0.iq.rate 0.448487 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 681666 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013259 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 179170597 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60104783 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50356616 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 551733 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267128 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260409 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51801972 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288664 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 541765 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued +system.cpu0.iq.rate 0.434084 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1139912 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4116 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12815 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 456622 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18431 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 154294 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1068899 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10746647 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 795792 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57645786 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 623000 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9290886 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6078694 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1595130 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 581617 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5318 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12815 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164656 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351489 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516145 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51022070 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8928198 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 390684 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3225661 # number of nop insts executed -system.cpu0.iew.exec_refs 14747797 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8123465 # Number of branches executed -system.cpu0.iew.exec_stores 5819599 # Number of stores executed -system.cpu0.iew.exec_rate 0.445079 # Inst execution rate -system.cpu0.iew.wb_sent 50710143 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50617025 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25247170 # num instructions producing a value -system.cpu0.iew.wb_consumers 34011376 # num instructions consuming a value +system.cpu0.iew.exec_nop 2780674 # number of nop insts executed +system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7066025 # Number of branches executed +system.cpu0.iew.exec_stores 5196118 # Number of stores executed +system.cpu0.iew.exec_rate 0.430889 # Inst execution rate +system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22095606 # num instructions producing a value +system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.441546 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742315 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6411331 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 584428 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 481702 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75046083 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.681415 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.595696 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55785925 74.34% 74.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8029512 10.70% 85.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4410175 5.88% 90.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2388789 3.18% 94.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1317256 1.76% 95.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 560978 0.75% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 472301 0.63% 97.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 435634 0.58% 97.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1645513 2.19% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75046083 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51137491 # Number of instructions committed -system.cpu0.commit.committedOps 51137491 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 44873722 # Number of instructions committed +system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13773046 # Number of memory references committed -system.cpu0.commit.loads 8150974 # Number of loads committed -system.cpu0.commit.membars 198820 # Number of memory barriers committed -system.cpu0.commit.branches 7724848 # Number of branches committed -system.cpu0.commit.fp_insts 258424 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47356368 # Number of committed integer instructions. -system.cpu0.commit.function_calls 655486 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1645513 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12194166 # Number of memory references committed +system.cpu0.commit.loads 7163069 # Number of loads committed +system.cpu0.commit.membars 173899 # Number of memory barriers committed +system.cpu0.commit.branches 6736138 # Number of branches committed +system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions. +system.cpu0.commit.function_calls 557213 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 130752703 # The number of ROB reads -system.cpu0.rob.rob_writes 116166541 # The number of ROB writes -system.cpu0.timesIdled 1097555 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38521021 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3690835342 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48197169 # Number of Instructions Simulated -system.cpu0.committedOps 48197169 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 48197169 # Number of Instructions Simulated -system.cpu0.cpi 2.378480 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.378480 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.420437 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.420437 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67125195 # number of integer regfile reads -system.cpu0.int_regfile_writes 36645952 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127833 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129422 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1709874 # number of misc regfile reads -system.cpu0.misc_regfile_writes 817230 # number of misc regfile writes +system.cpu0.rob.rob_reads 113567039 # The number of ROB reads +system.cpu0.rob.rob_writes 101661188 # The number of ROB writes +system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 42330060 # Number of Instructions Simulated +system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated +system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads +system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes +system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads +system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads +system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1105,49 +1169,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111571177 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2198759 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2198668 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13061 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13061 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10020 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5803 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15823 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343740 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302191 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1753935 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3363647 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 431103 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 300395 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5849080 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56122624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 129969996 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13794368 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 11000190 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 210887178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210876874 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1413952 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4971684979 # Layer occupancy (ticks) +system.toL2Bus.throughput 112875870 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 213368266 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3951712593 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5887546567 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 970657716 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 517795038 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1437659 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54613 # Transaction distribution -system.iobus.trans_dist::WriteResp 54613 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1433257 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 53910 # Transaction distribution +system.iobus.trans_dist::WriteResp 53910 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1158,12 +1222,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40510 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123964 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1174,14 +1238,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73866 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735490 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735490 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11269000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68234 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729874 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729874 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9865000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1201,253 +1265,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378285900 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377768695 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26744000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43112505 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42672507 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 876399 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.760309 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6802362 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 876908 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.757213 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.760309 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995626 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995626 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6802362 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6802362 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6802362 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6802362 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6802362 # number of overall hits -system.cpu0.icache.overall_hits::total 6802362 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 921891 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 921891 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 921891 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 921891 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 921891 # number of overall misses -system.cpu0.icache.overall_misses::total 921891 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13290047828 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13290047828 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13290047828 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13290047828 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13290047828 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13290047828 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7724253 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7724253 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7724253 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7724253 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7724253 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7724253 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119350 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119350 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119350 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119350 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119350 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119350 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14416.072863 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14416.072863 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14416.072863 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14416.072863 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1109 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 232 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.685345 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 554.500000 # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 755849 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.693536 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6013634 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 756358 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.950777 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693536 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6013634 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6013634 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6013634 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6013634 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6013634 # number of overall hits +system.cpu0.icache.overall_hits::total 6013634 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 794785 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 794785 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 794785 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 794785 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 794785 # number of overall misses +system.cpu0.icache.overall_misses::total 794785 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11289773018 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11289773018 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11289773018 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11289773018 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11289773018 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11289773018 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6808419 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6808419 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6808419 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6808419 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6808419 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6808419 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116736 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116736 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116736 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116736 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116736 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116736 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14204.813903 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14204.813903 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14204.813903 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14204.813903 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5327 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 41.944882 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44872 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 44872 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 44872 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 44872 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 44872 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 44872 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 877019 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 877019 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 877019 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 877019 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 877019 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 877019 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10904529395 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10904529395 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10904529395 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10904529395 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10904529395 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10904529395 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113541 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113541 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113541 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12433.629596 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38259 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 38259 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 38259 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 38259 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 38259 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 38259 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 756526 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 756526 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 756526 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 756526 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 756526 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 756526 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9285394312 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9285394312 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9285394312 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9285394312 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9285394312 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9285394312 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111116 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111116 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111116 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12273.727951 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1278910 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.619274 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10469394 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1279422 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.182909 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.619274 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987538 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987538 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6440836 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6440836 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3667453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3667453 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162740 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 162740 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187465 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 187465 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10108289 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10108289 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10108289 # number of overall hits -system.cpu0.dcache.overall_hits::total 10108289 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1585845 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1585845 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1749611 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1749611 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20563 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20563 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2808 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2808 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3335456 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3335456 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3335456 # number of overall misses -system.cpu0.dcache.overall_misses::total 3335456 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40055257591 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40055257591 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78246234000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 78246234000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 299434996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 299434996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20885924 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20885924 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 118301491591 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 118301491591 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 118301491591 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 118301491591 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8026681 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8026681 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5417064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183303 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183303 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190273 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190273 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13443745 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13443745 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13443745 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13443745 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197572 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197572 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322981 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.322981 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014758 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014758 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248105 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248105 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248105 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25257.990277 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25257.990277 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44722.074793 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44722.074793 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14561.834168 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14561.834168 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7438.007123 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7438.007123 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35467.861543 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35467.861543 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2886351 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 51822 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 55.697407 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 1092682 # number of replacements +system.cpu0.dcache.tags.tagsinuse 465.850340 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9201265 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1093194 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.416864 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 465.850340 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.909864 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.909864 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5673895 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5673895 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3199282 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3199282 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148885 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 148885 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172652 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 172652 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8873177 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8873177 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8873177 # number of overall hits +system.cpu0.dcache.overall_hits::total 8873177 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1348613 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1348613 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1646140 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1646140 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16729 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16729 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 773 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 773 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2994753 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2994753 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2994753 # number of overall misses +system.cpu0.dcache.overall_misses::total 2994753 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36556454998 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36556454998 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 72896722210 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 72896722210 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251362748 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 251362748 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4670052 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4670052 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 109453177208 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 109453177208 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 109453177208 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 109453177208 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7022508 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7022508 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4845422 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4845422 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 165614 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 165614 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 173425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 173425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11867930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11867930 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11867930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11867930 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192042 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.192042 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339731 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.339731 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101012 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101012 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004457 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004457 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252340 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.252340 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252340 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.252340 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27106.705184 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27106.705184 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44283.428026 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44283.428026 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15025.569251 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15025.569251 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6041.464424 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6041.464424 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36548.315406 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36548.315406 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2779952 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1302 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 46345 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.983860 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 162.750000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 752999 # number of writebacks -system.cpu0.dcache.writebacks::total 752999 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 583027 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 583027 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1475561 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1475561 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4528 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4528 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2058588 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2058588 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2058588 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2058588 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002818 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1002818 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274050 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 274050 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16035 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16035 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2807 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2807 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1276868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1276868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1276868 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1276868 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26563866972 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26563866972 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11468217837 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11468217837 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177500254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177500254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15271076 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15271076 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38032084809 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38032084809 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38032084809 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38032084809 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459298500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459298500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2147907499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2147907499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607205999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607205999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124936 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124936 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050590 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050590 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087478 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087478 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014752 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014752 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094979 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094979 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26489.220349 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26489.220349 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41847.173279 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41847.173279 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11069.551232 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11069.551232 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5440.354827 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5440.354827 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 588957 # number of writebacks +system.cpu0.dcache.writebacks::total 588957 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 514989 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 514989 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392541 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1392541 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3960 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3960 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1907530 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1907530 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1907530 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1907530 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 833624 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 833624 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253599 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 253599 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12769 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1087223 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1087223 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1087223 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1087223 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24857542918 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24857542918 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10684541815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10684541815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 151212250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 151212250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3123948 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3123948 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35542084733 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35542084733 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35542084733 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35542084733 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 990981000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 990981000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668402499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668402499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2659383499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2659383499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118707 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118707 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052338 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052338 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.077101 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.077101 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004457 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004457 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091610 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091610 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29818.650756 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29818.650756 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42131.640168 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42131.640168 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11842.137207 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11842.137207 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4041.329884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4041.329884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1455,35 +1519,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2517085 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2083961 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 72869 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1481224 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 844711 # Number of BTB hits +system.cpu1.branchPred.lookups 4005476 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.027904 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 172550 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7415 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1869470 # DTB read hits -system.cpu1.dtb.read_misses 10476 # DTB read misses -system.cpu1.dtb.read_acv 22 # DTB read access violations -system.cpu1.dtb.read_accesses 321268 # DTB read accesses -system.cpu1.dtb.write_hits 1203365 # DTB write hits -system.cpu1.dtb.write_misses 2061 # DTB write misses -system.cpu1.dtb.write_acv 64 # DTB write access violations -system.cpu1.dtb.write_accesses 130567 # DTB write accesses -system.cpu1.dtb.data_hits 3072835 # DTB hits -system.cpu1.dtb.data_misses 12537 # DTB misses -system.cpu1.dtb.data_acv 86 # DTB access violations -system.cpu1.dtb.data_accesses 451835 # DTB accesses -system.cpu1.itb.fetch_hits 424254 # ITB hits -system.cpu1.itb.fetch_misses 6539 # ITB misses -system.cpu1.itb.fetch_acv 190 # ITB acv -system.cpu1.itb.fetch_accesses 430793 # ITB accesses +system.cpu1.dtb.read_hits 2861061 # DTB read hits +system.cpu1.dtb.read_misses 13171 # DTB read misses +system.cpu1.dtb.read_acv 26 # DTB read access violations +system.cpu1.dtb.read_accesses 327320 # DTB read accesses +system.cpu1.dtb.write_hits 1771736 # DTB write hits +system.cpu1.dtb.write_misses 2413 # DTB write misses +system.cpu1.dtb.write_acv 61 # DTB write access violations +system.cpu1.dtb.write_accesses 133954 # DTB write accesses +system.cpu1.dtb.data_hits 4632797 # DTB hits +system.cpu1.dtb.data_misses 15584 # DTB misses +system.cpu1.dtb.data_acv 87 # DTB access violations +system.cpu1.dtb.data_accesses 461274 # DTB accesses +system.cpu1.itb.fetch_hits 484886 # ITB hits +system.cpu1.itb.fetch_misses 6783 # ITB misses +system.cpu1.itb.fetch_acv 213 # ITB acv +system.cpu1.itb.fetch_accesses 491669 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1496,508 +1560,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 15249987 # number of cpu cycles simulated +system.cpu1.numCycles 26365345 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5781097 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11894429 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2517085 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1017261 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2131045 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 385761 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6016414 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62392 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 56888 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1433413 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48410 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14320297 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.830599 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.206016 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12189252 85.12% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 136413 0.95% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 229060 1.60% 87.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 170637 1.19% 88.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 294592 2.06% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 114916 0.80% 91.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 126454 0.88% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 195471 1.36% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 863502 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14320297 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.165055 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.779963 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5724387 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6255039 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1992849 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 108261 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 239760 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 108451 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6971 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11669639 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20547 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 239760 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5925475 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 420572 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5212839 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1896462 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 625187 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10812976 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55937 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12872049 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52940 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 40484 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1926881 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1976180 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1276143 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 178422 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 98267 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9491737 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 473513 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9233560 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29148 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1376057 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 698810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 340347 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14320297 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.319506 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10263877 71.67% 71.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1860247 12.99% 84.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 792265 5.53% 90.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 533948 3.73% 93.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 454852 3.18% 97.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 207190 1.45% 98.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 132078 0.92% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 67607 0.47% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8233 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14320297 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3147 1.66% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 101977 53.82% 55.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84363 44.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5756733 62.35% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16005 0.17% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10795 0.12% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1955574 21.18% 83.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1226577 13.28% 97.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 262587 2.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9233560 # Type of FU issued -system.cpu1.iq.rate 0.605480 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 189487 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020522 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32803401 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11243674 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8968182 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 202651 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 99238 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 96146 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9314130 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 105391 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 90243 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued +system.cpu1.iq.rate 0.569740 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 277299 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1341 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1688 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 122180 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 318 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 14956 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 239760 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 255964 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 40163 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10453412 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 142319 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1976180 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1276143 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 429143 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33341 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1750 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1688 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 32963 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 95419 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 128382 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9148055 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1886987 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 85505 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 488162 # number of nop insts executed -system.cpu1.iew.exec_refs 3098273 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1362461 # Number of branches executed -system.cpu1.iew.exec_stores 1211286 # Number of stores executed -system.cpu1.iew.exec_rate 0.599873 # Inst execution rate -system.cpu1.iew.wb_sent 9092483 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9064328 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4254481 # num instructions producing a value -system.cpu1.iew.wb_consumers 5984515 # num instructions consuming a value +system.cpu1.iew.exec_nop 898529 # number of nop insts executed +system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2338044 # Number of branches executed +system.cpu1.iew.exec_stores 1780212 # Number of stores executed +system.cpu1.iew.exec_rate 0.564317 # Inst execution rate +system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7139948 # num instructions producing a value +system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.594383 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710915 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1421128 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 133166 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 121427 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14080537 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.636506 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577564 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10719102 76.13% 76.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1572221 11.17% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 583613 4.14% 91.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 356342 2.53% 93.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 255998 1.82% 95.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 100117 0.71% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 105425 0.75% 97.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 105001 0.75% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 282718 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14080537 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8962351 # Number of instructions committed -system.cpu1.commit.committedOps 8962351 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 23251022 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 14604164 # Number of instructions committed +system.cpu1.commit.committedOps 14604164 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2852844 # Number of memory references committed -system.cpu1.commit.loads 1698881 # Number of loads committed -system.cpu1.commit.membars 42409 # Number of memory barriers committed -system.cpu1.commit.branches 1280511 # Number of branches committed -system.cpu1.commit.fp_insts 94891 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8306060 # Number of committed integer instructions. -system.cpu1.commit.function_calls 141484 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 282718 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4287363 # Number of memory references committed +system.cpu1.commit.loads 2592870 # Number of loads committed +system.cpu1.commit.membars 62980 # Number of memory barriers committed +system.cpu1.commit.branches 2183593 # Number of branches committed +system.cpu1.commit.fp_insts 107360 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions. +system.cpu1.commit.function_calls 233831 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 466797 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 24092433 # The number of ROB reads -system.cpu1.rob.rob_writes 21005155 # The number of ROB writes -system.cpu1.timesIdled 128904 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 929690 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3789568266 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8530162 # Number of Instructions Simulated -system.cpu1.committedOps 8530162 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8530162 # Number of Instructions Simulated -system.cpu1.cpi 1.787772 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.787772 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.559355 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.559355 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11798212 # number of integer regfile reads -system.cpu1.int_regfile_writes 6449971 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52607 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52314 # number of floating regfile writes -system.cpu1.misc_regfile_reads 504098 # number of misc regfile reads -system.cpu1.misc_regfile_writes 209723 # number of misc regfile writes -system.cpu1.icache.tags.replacements 214995 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.564735 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1210101 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 215507 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.615135 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878702632250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.564735 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919072 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919072 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1210101 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1210101 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1210101 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1210101 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1210101 # number of overall hits -system.cpu1.icache.overall_hits::total 1210101 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 223312 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 223312 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 223312 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 223312 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 223312 # number of overall misses -system.cpu1.icache.overall_misses::total 223312 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3028009139 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3028009139 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3028009139 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3028009139 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3028009139 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3028009139 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1433413 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1433413 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1433413 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1433413 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1433413 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1433413 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155790 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.155790 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155790 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.155790 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155790 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.155790 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13559.545116 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13559.545116 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13559.545116 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13559.545116 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked +system.cpu1.rob.rob_reads 39695803 # The number of ROB reads +system.cpu1.rob.rob_writes 34392702 # The number of ROB writes +system.cpu1.timesIdled 272923 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2721078 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13810279 # Number of Instructions Simulated +system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated +system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 19249115 # number of integer regfile reads +system.cpu1.int_regfile_writes 10558811 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58616 # number of floating regfile reads +system.cpu1.fp_regfile_writes 58623 # number of floating regfile writes +system.cpu1.misc_regfile_reads 636847 # number of misc regfile reads +system.cpu1.misc_regfile_writes 274262 # number of misc regfile writes +system.cpu1.icache.tags.replacements 328629 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.249918 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1927863 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 329141 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.857256 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 49124844500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.249918 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984863 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1927863 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1927863 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1927863 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1927863 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1927863 # number of overall hits +system.cpu1.icache.overall_hits::total 1927863 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses +system.cpu1.icache.overall_misses::total 344335 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4815194513 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4815194513 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4815194513 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4815194513 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4815194513 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4815194513 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2272198 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2272198 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2272198 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2272198 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2272198 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2272198 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.151543 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.151543 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.151543 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13984.040289 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13984.040289 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1435 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 51 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.531250 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 28.137255 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7746 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7746 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7746 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 215566 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 215566 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 215566 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 215566 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 215566 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 215566 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2508977533 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2508977533 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2508977533 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2508977533 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2508977533 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2508977533 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150387 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.150387 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.150387 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11639.022541 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15125 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 15125 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 15125 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 15125 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 15125 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 15125 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329210 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3979739752 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3979739752 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.144886 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.144886 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.144886 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12088.757182 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 104218 # number of replacements -system.cpu1.dcache.tags.tagsinuse 490.671059 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2506866 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 104618 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.962091 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.671059 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958342 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.958342 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1537129 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1537129 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 905397 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 905397 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30937 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 30937 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29831 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 29831 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2442526 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2442526 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2442526 # number of overall hits -system.cpu1.dcache.overall_hits::total 2442526 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 200186 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 200186 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 209846 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 209846 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5149 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5149 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2998 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2998 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 410032 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 410032 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 410032 # number of overall misses -system.cpu1.dcache.overall_misses::total 410032 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2816563957 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2816563957 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7378261443 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7378261443 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51136995 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 51136995 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22092953 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 22092953 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10194825400 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10194825400 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10194825400 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10194825400 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1737315 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1737315 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1115243 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1115243 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36086 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 36086 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32829 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32829 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2852558 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2852558 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2852558 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2852558 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.115227 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.115227 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188162 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.188162 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142687 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142687 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091322 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091322 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143742 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.143742 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143742 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.143742 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14069.734932 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14069.734932 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35160.362566 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 35160.362566 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9931.442028 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9931.442028 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7369.230487 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7369.230487 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24863.487240 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24863.487240 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 240672 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 330658 # number of replacements +system.cpu1.dcache.tags.tagsinuse 495.877996 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3531981 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 331060 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 10.668704 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 42038170500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.877996 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968512 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.968512 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2174883 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2174883 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1270139 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1270139 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 43234 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 43234 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 46255 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 46255 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3445022 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3445022 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3445022 # number of overall hits +system.cpu1.dcache.overall_hits::total 3445022 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 478937 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 478937 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 369959 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 369959 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7995 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7995 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 815 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 815 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 848896 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 848896 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 848896 # number of overall misses +system.cpu1.dcache.overall_misses::total 848896 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7393539723 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 7393539723 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13842081157 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13842081157 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 114418247 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 114418247 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5712098 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5712098 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 21235620880 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 21235620880 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 21235620880 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 21235620880 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2653820 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2653820 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1640098 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1640098 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 51229 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 51229 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 47070 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 47070 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4293918 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4293918 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4293918 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4293918 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.180471 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.180471 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225571 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.225571 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156064 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156064 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017315 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017315 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197697 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.197697 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197697 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.197697 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15437.395154 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15437.395154 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37415.176160 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37415.176160 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.225391 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14311.225391 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7008.709202 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7008.709202 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25015.574205 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25015.574205 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 432228 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3904 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7570 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.647541 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57.097490 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 69226 # number of writebacks -system.cpu1.dcache.writebacks::total 69226 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 124077 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 124077 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 172447 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 172447 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 558 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 558 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296524 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296524 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296524 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296524 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 76109 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 76109 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37399 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 37399 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4591 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4591 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2996 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2996 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 113508 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 113508 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 113508 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 113508 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 856275217 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 856275217 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1088322932 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1088322932 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34640753 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34640753 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16100047 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16100047 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1944598149 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1944598149 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1944598149 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1944598149 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23613000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23613000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 620064002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 620064002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643677002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643677002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043808 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043808 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033534 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033534 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.127224 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.127224 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091261 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091261 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039792 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039792 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11250.643380 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11250.643380 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29100.321720 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29100.321720 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7545.361141 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7545.361141 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5373.847463 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5373.847463 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 251201 # number of writebacks +system.cpu1.dcache.writebacks::total 251201 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211025 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 211025 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306586 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306586 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1580 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1580 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 517611 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 517611 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 517611 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 517611 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267912 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 267912 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 63373 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 63373 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6415 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6415 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 815 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 815 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 331285 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 331285 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 331285 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 331285 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3418270202 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3418270202 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2068179649 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2068179649 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71253503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71253503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4081902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4081902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5486449851 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5486449851 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5486449851 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5486449851 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491833500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491833500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943255503 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 943255503 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1435089003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1435089003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100953 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.100953 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.125222 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.125222 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017315 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017315 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.077152 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.077152 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12758.929059 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12758.929059 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32635.028309 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32635.028309 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11107.327046 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11107.327046 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5008.468712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5008.468712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2006,170 +2070,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6603 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184198 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65080 40.52% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.20% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 193 0.12% 41.92% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93271 58.08% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 160599 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64086 49.21% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.48% 50.79% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 193 0.15% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63894 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130228 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1861779564000 97.85% 97.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63861000 0.00% 97.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 571607000 0.03% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 92660000 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40230450500 2.11% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1902738142500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984726 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 39.83% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866804619500 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904664253500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983248 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685036 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810889 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.664268 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed +system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed +system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed +system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed +system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3514 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 153834 90.90% 93.18% # number of callpals executed -system.cpu0.kern.callpal::rdps 6534 3.86% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rti 4517 2.67% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169239 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7061 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches +system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed +system.cpu0.kern.callpal::rdps 6127 4.09% 96.83% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.83% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.83% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.83% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.84% # number of callpals executed +system.cpu0.kern.callpal::rti 4274 2.85% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149930 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1285 -system.cpu0.kern.mode_good::user 1286 +system.cpu0.kern.mode_good::kernel 1257 +system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181986 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.308015 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1900726417500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2011717000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3515 # number of times the context was actually changed +system.cpu0.kern.swap_context 2970 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2440 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 55424 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17233 36.50% 36.50% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 4.07% 40.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 284 0.60% 41.17% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27775 58.83% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 47214 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16850 47.30% 47.30% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 5.40% 52.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.80% 53.50% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16566 46.50% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35622 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871948155000 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531300500 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 128640500 0.01% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29802235500 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1902410331500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.977775 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.596436 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.754480 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed +system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed +system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed +system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed +system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed +system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed +system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 193 0.40% 0.40% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.40% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1095 2.25% 2.65% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.66% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41959 86.06% 88.73% # number of callpals executed -system.cpu1.kern.callpal::rdps 2221 4.56% 93.29% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.29% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.30% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.30% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.31% # number of callpals executed -system.cpu1.kern.callpal::rti 3048 6.25% 99.56% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.35% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed +system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed +system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed +system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48756 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1363 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2408 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 668 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 209 -system.cpu1.kern.mode_switch_good::kernel 0.490095 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 66403 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 557 +system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_good::idle 69 +system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086794 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.315839 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4405402000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 814709500 0.04% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1897179577000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1096 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1278 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 56fb70faf..cb131fc03 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,125 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860201 # Number of seconds simulated -sim_ticks 1860200687500 # Number of ticks simulated -final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860198 # Number of seconds simulated +sim_ticks 1860197608000 # Number of ticks simulated +final_tick 1860197608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133673 # Simulator instruction rate (inst/s) -host_op_rate 133673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4693486883 # Simulator tick rate (ticks/s) -host_mem_usage 310052 # Number of bytes of host memory used -host_seconds 396.34 # Real time elapsed on the host -sim_insts 52979577 # Number of instructions simulated -sim_ops 52979577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879296 # Number of bytes read from this memory +host_inst_rate 128608 # Simulator instruction rate (inst/s) +host_op_rate 128608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4515644283 # Simulator tick rate (ticks/s) +host_mem_usage 336512 # Number of bytes of host memory used +host_seconds 411.95 # Real time elapsed on the host +sim_insts 52979573 # Number of instructions simulated +sim_ops 52979573 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879808 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28495552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515968 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388739 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15071 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388747 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445243 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117437 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117437 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15318536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040407 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040407 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28495552 # Total number of bytes read from memory -system.physmem.bytesWritten 7515968 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27330 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28321 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7923 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7495 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7495 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6715 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6683 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7403 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7888 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7823 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1860195209000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445243 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117437 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 330882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.num_reads::total 445260 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117448 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117448 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15319147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445260 # Number of read requests accepted +system.physmem.writeReqs 117448 # Number of write requests accepted +system.physmem.readBursts 445260 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117448 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28493888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue +system.physmem.bytesWritten 7515904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28496640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7516672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 177 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28229 # Per bank write bursts +system.physmem.perBankRdBursts::1 27970 # Per bank write bursts +system.physmem.perBankRdBursts::2 28438 # Per bank write bursts +system.physmem.perBankRdBursts::3 28034 # Per bank write bursts +system.physmem.perBankRdBursts::4 27800 # Per bank write bursts +system.physmem.perBankRdBursts::5 27233 # Per bank write bursts +system.physmem.perBankRdBursts::6 27248 # Per bank write bursts +system.physmem.perBankRdBursts::7 27300 # Per bank write bursts +system.physmem.perBankRdBursts::8 27656 # Per bank write bursts +system.physmem.perBankRdBursts::9 27404 # Per bank write bursts +system.physmem.perBankRdBursts::10 27929 # Per bank write bursts +system.physmem.perBankRdBursts::11 27540 # Per bank write bursts +system.physmem.perBankRdBursts::12 27555 # Per bank write bursts +system.physmem.perBankRdBursts::13 28228 # Per bank write bursts +system.physmem.perBankRdBursts::14 28334 # Per bank write bursts +system.physmem.perBankRdBursts::15 28319 # Per bank write bursts +system.physmem.perBankWrBursts::0 7929 # Per bank write bursts +system.physmem.perBankWrBursts::1 7498 # Per bank write bursts +system.physmem.perBankWrBursts::2 7947 # Per bank write bursts +system.physmem.perBankWrBursts::3 7517 # Per bank write bursts +system.physmem.perBankWrBursts::4 7338 # Per bank write bursts +system.physmem.perBankWrBursts::5 6689 # Per bank write bursts +system.physmem.perBankWrBursts::6 6763 # Per bank write bursts +system.physmem.perBankWrBursts::7 6689 # Per bank write bursts +system.physmem.perBankWrBursts::8 7098 # Per bank write bursts +system.physmem.perBankWrBursts::9 6803 # Per bank write bursts +system.physmem.perBankWrBursts::10 7320 # Per bank write bursts +system.physmem.perBankWrBursts::11 6984 # Per bank write bursts +system.physmem.perBankWrBursts::12 7119 # Per bank write bursts +system.physmem.perBankWrBursts::13 7873 # Per bank write bursts +system.physmem.perBankWrBursts::14 8054 # Per bank write bursts +system.physmem.perBankWrBursts::15 7815 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1860192151000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 445260 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 117448 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 332300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -129,242 +131,288 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 955.810131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 232.523406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2430.690638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13031 34.59% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5648 14.99% 49.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3558 9.45% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2240 5.95% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1644 4.36% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1436 3.81% 73.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 989 2.63% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 804 2.13% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 676 1.79% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 516 1.37% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 573 1.52% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 541 1.44% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 276 0.73% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 231 0.61% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 160 0.42% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 263 0.70% 86.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 87 0.23% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 129 0.34% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 153 0.41% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 242 0.64% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 113 0.30% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 462 1.23% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 590 1.57% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 81 0.22% 91.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 28 0.07% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 16 0.04% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 89 0.24% 91.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 26 0.07% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 8 0.02% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 14 0.04% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 43 0.11% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 28 0.07% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 18 0.05% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 7 0.02% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 5 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 6 0.02% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.01% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 3 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.01% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.01% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 5 0.01% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2432 6.46% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 13 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 5 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37668 # Bytes accessed per row activation -system.physmem.totQLat 6113897250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13475242250 # Sum of mem lat for all requests -system.physmem.totBusLat 2225940000 # Total cycles spent in databus access -system.physmem.totBankLat 5135405000 # Total cycles spent in bank access -system.physmem.avgQLat 13733.29 # Average queueing delay per request -system.physmem.avgBankLat 11535.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30268.66 # Average memory access latency -system.physmem.avgRdBW 15.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.32 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 43193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 833.653601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 238.014185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1939.409877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14703 34.04% 34.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6277 14.53% 48.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4438 10.27% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2692 6.23% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1642 3.80% 68.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1371 3.17% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 939 2.17% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 792 1.83% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 658 1.52% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 515 1.19% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 623 1.44% 80.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 600 1.39% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 275 0.64% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 275 0.64% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 263 0.61% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 360 0.83% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 192 0.44% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 168 0.39% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 100 0.23% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 208 0.48% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 111 0.26% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 353 0.82% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 185 0.43% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 668 1.55% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 85 0.20% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 47 0.11% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 186 0.43% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 74 0.17% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 80 0.19% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 97 0.22% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 19 0.04% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 108 0.25% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 28 0.06% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 15 0.03% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.00% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 16 0.04% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 24 0.06% 91.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 101 0.23% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 13 0.03% 91.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 66 0.15% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 39 0.09% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 82 0.19% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 66 0.15% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 13 0.03% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 95 0.22% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 10 0.02% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 3 0.01% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 24 0.06% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 91 0.21% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 11 0.03% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 39 0.09% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 79 0.18% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 94 0.22% 94.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 22 0.05% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 12 0.03% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 4 0.01% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 12 0.03% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 13 0.03% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 67 0.16% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 68 0.16% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 99 0.23% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 11 0.03% 95.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 14 0.03% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 83 0.19% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 39 0.09% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 81 0.19% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 67 0.16% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 13 0.03% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 21 0.05% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 3 0.01% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 24 0.06% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 13 0.03% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 81 0.19% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 309 0.72% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 16 0.04% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.01% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.01% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 18 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 331 0.77% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 5 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 3 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 37 0.09% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 176 0.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43193 # Bytes accessed per row activation +system.physmem.totQLat 8380902250 # Total ticks spent queuing +system.physmem.totMemAccLat 15783312250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2226085000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5176325000 # Total ticks spent accessing banks +system.physmem.avgQLat 18824.31 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11626.52 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 35450.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.67 # Average write queue length over time -system.physmem.readRowHits 430049 # Number of row buffer hits during reads -system.physmem.writeRowHits 94886 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3305955.80 # Average gap between requests -system.membus.throughput 19401806 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295958 # Transaction distribution -system.membus.trans_dist::ReadResp 295878 # Transaction distribution +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.37 # Average write queue length when enqueuing +system.physmem.readRowHits 424661 # Number of row buffer hits during reads +system.physmem.writeRowHits 94799 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.avgGap 3305785.86 # Average gap between requests +system.physmem.pageHitRate 92.32 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19402801 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295960 # Transaction distribution +system.membus.trans_dist::ReadResp 295877 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117437 # Transaction distribution -system.membus.trans_dist::UpgradeReq 178 # Transaction distribution -system.membus.trans_dist::UpgradeResp 178 # Transaction distribution -system.membus.trans_dist::ReadExReq 156851 # Transaction distribution -system.membus.trans_dist::ReadExResp 156851 # Transaction distribution -system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.trans_dist::Writeback 117448 # Transaction distribution +system.membus.trans_dist::UpgradeReq 180 # Transaction distribution +system.membus.trans_dist::UpgradeResp 180 # Transaction distribution +system.membus.trans_dist::ReadExReq 156869 # Transaction distribution +system.membus.trans_dist::ReadExResp 156869 # Transaction distribution +system.membus.trans_dist::BadAddressError 83 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884153 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917424 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042103 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748404 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36055668 # Total data (bytes) +system.membus.tot_pkt_size::total 36057460 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36057460 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29849000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1552225748 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1551414500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3765192546 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3763341794 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376305243 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261102 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710341438000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261102 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078819 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078819 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -373,14 +421,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21345883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21345883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10482445518 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10482445518 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10503791401 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10503791401 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10503791401 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10503791401 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12983817806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12983817806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13004951689 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13004951689 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13004951689 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13004951689 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -397,19 +445,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123386.606936 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123386.606936 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252272.947584 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 252272.947584 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 251738.559641 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 251738.559641 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 274094 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312471.549047 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312471.549047 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311682.485057 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311682.485057 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 402476 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27191 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29170 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.080321 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.797600 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -423,14 +471,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12348383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12348383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8320362536 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8320362536 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8332710919 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8332710919 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8332710919 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8332710919 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10821554320 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10821554320 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10833691203 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10833691203 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10833691203 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10833691203 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -439,14 +487,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71377.936416 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71377.936416 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200239.760685 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 200239.760685 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260434.018098 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260434.018098 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -460,35 +508,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13856452 # Number of BP lookups -system.cpu.branchPred.condPredicted 11625252 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 398822 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9666189 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5826807 # Number of BTB hits +system.cpu.branchPred.lookups 13864479 # Number of BP lookups +system.cpu.branchPred.condPredicted 11634507 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 398117 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9551974 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5822395 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.280292 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 904750 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39047 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 60.954887 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906213 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38605 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9922890 # DTB read hits -system.cpu.dtb.read_misses 41426 # DTB read misses -system.cpu.dtb.read_acv 537 # DTB read access violations -system.cpu.dtb.read_accesses 941977 # DTB read accesses -system.cpu.dtb.write_hits 6601888 # DTB write hits -system.cpu.dtb.write_misses 10414 # DTB write misses -system.cpu.dtb.write_acv 409 # DTB write access violations -system.cpu.dtb.write_accesses 338180 # DTB write accesses -system.cpu.dtb.data_hits 16524778 # DTB hits -system.cpu.dtb.data_misses 51840 # DTB misses -system.cpu.dtb.data_acv 946 # DTB access violations -system.cpu.dtb.data_accesses 1280157 # DTB accesses -system.cpu.itb.fetch_hits 1306702 # ITB hits -system.cpu.itb.fetch_misses 37996 # ITB misses -system.cpu.itb.fetch_acv 1078 # ITB acv -system.cpu.itb.fetch_accesses 1344698 # ITB accesses +system.cpu.dtb.read_hits 9930859 # DTB read hits +system.cpu.dtb.read_misses 42001 # DTB read misses +system.cpu.dtb.read_acv 541 # DTB read access violations +system.cpu.dtb.read_accesses 942214 # DTB read accesses +system.cpu.dtb.write_hits 6592411 # DTB write hits +system.cpu.dtb.write_misses 10345 # DTB write misses +system.cpu.dtb.write_acv 410 # DTB write access violations +system.cpu.dtb.write_accesses 337923 # DTB write accesses +system.cpu.dtb.data_hits 16523270 # DTB hits +system.cpu.dtb.data_misses 52346 # DTB misses +system.cpu.dtb.data_acv 951 # DTB access violations +system.cpu.dtb.data_accesses 1280137 # DTB accesses +system.cpu.itb.fetch_hits 1308071 # ITB hits +system.cpu.itb.fetch_misses 36703 # ITB misses +system.cpu.itb.fetch_acv 1058 # ITB acv +system.cpu.itb.fetch_accesses 1344774 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -501,134 +549,134 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 120724090 # number of cpu cycles simulated +system.cpu.numCycles 121927488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28054756 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70765698 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13856452 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6731557 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13261846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1996538 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38180961 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33921 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253688 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 362223 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8553305 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264520 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81438491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.868947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.211995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28039089 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70847333 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13864479 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6728608 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13268188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1998523 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38187764 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33374 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253703 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 358378 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 313 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8556240 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264321 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81433386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.870004 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.213508 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68176645 83.72% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854498 1.05% 84.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1700203 2.09% 86.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 823613 1.01% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2757448 3.39% 91.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 566024 0.70% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 644448 0.79% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011541 1.24% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4904071 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68165198 83.71% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 850053 1.04% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1699284 2.09% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 821371 1.01% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2763942 3.39% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 562061 0.69% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645266 0.79% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1012758 1.24% 93.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4913453 6.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81438491 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.114778 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.586177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29237679 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37865551 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12126902 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 959687 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1248671 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585551 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42601 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69445978 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129475 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1248671 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30384491 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14146796 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20012830 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11334710 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4310991 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65667162 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7173 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505660 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79531258 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240064 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12233478 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10440283 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6900737 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318689 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 855517 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58206235 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050936 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56823082 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 100209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6920159 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3549975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389936 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81438491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697742 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359996 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81433386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113711 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.581061 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29221081 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37872240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12130703 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 959021 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1250340 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 583021 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69509272 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129850 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1250340 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30372674 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14147971 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20014852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11335195 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4312352 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65701425 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7084 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 503729 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1544223 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43873094 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79768312 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79589398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166462 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180112 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5692974 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682864 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240315 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12255388 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10448429 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6906827 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1318660 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 851527 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58223534 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050984 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56812947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113805 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6931173 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3605221 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390018 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81433386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56732960 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10881055 13.36% 83.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5157432 6.33% 89.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3394617 4.17% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2629816 3.23% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1458992 1.79% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753848 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332168 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 97603 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56726750 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10882649 13.36% 83.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5163201 6.34% 89.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3388782 4.16% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2628492 3.23% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1462722 1.80% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 751690 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332968 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96132 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81438491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81433386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91824 11.60% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372747 47.08% 58.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 327090 41.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91250 11.56% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372174 47.14% 58.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326051 41.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38740473 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61726 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38733166 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61715 0.11% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued @@ -656,114 +704,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10354642 18.22% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6680643 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949069 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10362094 18.24% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6670366 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56823082 # Type of FU issued -system.cpu.iq.rate 0.470686 # Inst issue rate -system.cpu.iq.fu_busy_cnt 791661 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013932 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195283781 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66854445 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55585028 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692743 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327940 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57245966 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361491 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598566 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56812947 # Type of FU issued +system.cpu.iq.rate 0.465957 # Inst issue rate +system.cpu.iq.fu_busy_cnt 789475 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013896 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195270080 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66882864 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55570085 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692479 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327821 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57233809 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 596971 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1347977 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 522824 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1356016 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3236 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 528856 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17906 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 181081 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17919 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 183461 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1248671 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10233873 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 701956 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63782733 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684936 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10440283 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6900737 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1806230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512408 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17686 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202063 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410564 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612627 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56356224 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9992501 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466857 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1250340 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10233655 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 702274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63801966 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 688802 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10448429 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6906827 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805093 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17454 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 201109 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411560 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 612669 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56346471 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10001011 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466475 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3525562 # number of nop insts executed -system.cpu.iew.exec_refs 16620030 # number of memory reference insts executed -system.cpu.iew.exec_branches 8925380 # Number of branches executed -system.cpu.iew.exec_stores 6627529 # Number of stores executed -system.cpu.iew.exec_rate 0.466818 # Inst execution rate -system.cpu.iew.wb_sent 56027730 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55912968 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27713014 # num instructions producing a value -system.cpu.iew.wb_consumers 37524402 # num instructions consuming a value +system.cpu.iew.exec_nop 3527448 # number of nop insts executed +system.cpu.iew.exec_refs 16619020 # number of memory reference insts executed +system.cpu.iew.exec_branches 8923746 # Number of branches executed +system.cpu.iew.exec_stores 6618009 # Number of stores executed +system.cpu.iew.exec_rate 0.462131 # Inst execution rate +system.cpu.iew.wb_sent 56013491 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55897906 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27708487 # num instructions producing a value +system.cpu.iew.wb_consumers 37528450 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.463147 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738533 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458452 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738333 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7495675 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661000 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 567647 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80189820 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700468 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629642 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7515002 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660966 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566897 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80183046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700527 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629598 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59377156 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8657171 10.80% 84.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4615541 5.76% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2519398 3.14% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1507686 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611065 0.76% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 523948 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 528681 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1849174 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59370328 74.04% 74.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8654728 10.79% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4617014 5.76% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2519187 3.14% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1509953 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 613300 0.76% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 523538 0.65% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 523484 0.65% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1851514 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80189820 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170363 # Number of instructions committed -system.cpu.commit.committedOps 56170363 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80183046 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170357 # Number of instructions committed +system.cpu.commit.committedOps 56170357 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470219 # Number of memory references committed -system.cpu.commit.loads 9092306 # Number of loads committed -system.cpu.commit.membars 226376 # Number of memory barriers committed -system.cpu.commit.branches 8439998 # Number of branches committed +system.cpu.commit.refs 15470384 # Number of memory references committed +system.cpu.commit.loads 9092413 # Number of loads committed +system.cpu.commit.membars 226354 # Number of memory barriers committed +system.cpu.commit.branches 8439829 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019946 # Number of committed integer instructions. -system.cpu.commit.function_calls 740578 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1849174 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52019973 # Number of committed integer instructions. +system.cpu.commit.function_calls 740579 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1851514 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141757103 # The number of ROB reads -system.cpu.rob.rob_writes 128582546 # The number of ROB writes -system.cpu.timesIdled 1193264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 39285599 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599670846 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979577 # Number of Instructions Simulated -system.cpu.committedOps 52979577 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52979577 # Number of Instructions Simulated -system.cpu.cpi 2.278691 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.278691 # CPI: Total CPI of All Threads -system.cpu.ipc 0.438848 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.438848 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73899188 # number of integer regfile reads -system.cpu.int_regfile_writes 40322867 # number of integer regfile writes -system.cpu.fp_regfile_reads 166085 # number of floating regfile reads +system.cpu.rob.rob_reads 141767299 # The number of ROB reads +system.cpu.rob.rob_writes 128622610 # The number of ROB writes +system.cpu.timesIdled 1192878 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40494102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598461292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979573 # Number of Instructions Simulated +system.cpu.committedOps 52979573 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979573 # Number of Instructions Simulated +system.cpu.cpi 2.301406 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301406 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434517 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434517 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73879526 # number of integer regfile reads +system.cpu.int_regfile_writes 40317649 # number of integer regfile writes +system.cpu.fp_regfile_reads 165968 # number of floating regfile reads system.cpu.fp_regfile_writes 167427 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985758 # number of misc regfile reads -system.cpu.misc_regfile_writes 938984 # number of misc regfile writes +system.cpu.misc_regfile_reads 1984782 # number of misc regfile reads +system.cpu.misc_regfile_writes 938976 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -795,7 +843,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454551 # Throughput (bytes/s) +system.iobus.throughput 1454553 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51150 # Transaction distribution @@ -855,225 +903,225 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378268160 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377740446 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43098759 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42670757 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111927083 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2117675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2117578 # Transaction distribution +system.cpu.toL2Bus.throughput 111891693 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2116597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2116497 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301054 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2016984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678218 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5695202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64539584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143593268 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208132852 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208122804 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17856 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2479701498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1516139861 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2192873665 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009263 # number of replacements -system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7487431 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7487431 # number of overall hits -system.cpu.icache.overall_hits::total 7487431 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065872 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065872 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065872 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065872 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065872 # number of overall misses -system.cpu.icache.overall_misses::total 1065872 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14976021459 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14976021459 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14976021459 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14976021459 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14976021459 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14976021459 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8553303 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8553303 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8553303 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8553303 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8553303 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8553303 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124615 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124615 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124615 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124615 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124615 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124615 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14050.487731 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14050.487731 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14050.487731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14050.487731 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8372 # number of cycles access was blocked +system.cpu.icache.tags.replacements 1007825 # number of replacements +system.cpu.icache.tags.tagsinuse 509.660233 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7491263 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1008333 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.429354 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.660233 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7491264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7491264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7491264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7491264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7491264 # number of overall hits +system.cpu.icache.overall_hits::total 7491264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064974 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064974 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064974 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064974 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064974 # number of overall misses +system.cpu.icache.overall_misses::total 1064974 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14872208186 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14872208186 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14872208186 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14872208186 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14872208186 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14872208186 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8556238 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8556238 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8556238 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8556238 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8556238 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8556238 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124468 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124468 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124468 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124468 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124468 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124468 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13964.855655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13964.855655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13964.855655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13964.855655 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5226 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 214 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 45.010753 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.420561 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55880 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55880 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55880 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55880 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55880 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55880 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009992 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009992 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009992 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009992 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009992 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009992 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12273344851 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12273344851 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12273344851 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12273344851 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12273344851 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12273344851 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12151.922838 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12151.922838 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56421 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56421 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56421 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56421 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56421 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56421 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008553 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1008553 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1008553 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1008553 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1008553 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1008553 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12184986133 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12184986133 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12184986133 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12184986133 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12184986133 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12184986133 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117873 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.117873 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.117873 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.651765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.651765 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53859.326644 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.821828 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081004 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094224 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 994809 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 826788 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1821597 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840831 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840831 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.tags.replacements 338320 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65339.826573 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2544675 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.306724 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5511908750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53856.157750 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5301.221918 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6182.446905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.821780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.094337 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 993358 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 827156 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1820514 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 840887 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 840887 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185623 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185623 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 994809 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1012411 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2007220 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 994809 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1012411 # number of overall hits -system.cpu.l2cache.overall_hits::total 2007220 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273792 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288856 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115439 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115439 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389231 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404295 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389231 # number of overall misses -system.cpu.l2cache.overall_misses::total 404295 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1289741743 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17221594730 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18511336473 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 285497 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 285497 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9397410357 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9397410357 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1289741743 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 26619005087 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27908746830 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1289741743 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 26619005087 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27908746830 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009873 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1100580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2110453 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 840831 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 840831 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 185595 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185595 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 993358 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1012751 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2006109 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 993358 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1012751 # number of overall hits +system.cpu.l2cache.overall_hits::total 2006109 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15073 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273785 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288858 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115458 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115458 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15073 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389243 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404316 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15073 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389243 # number of overall misses +system.cpu.l2cache.overall_misses::total 404316 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1217060992 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17822778727 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19039839719 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 308496 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 308496 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9541842859 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9541842859 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1217060992 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27364621586 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28581682578 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1217060992 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27364621586 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28581682578 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1008431 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1100941 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109372 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 840887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 840887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301062 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301062 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1009873 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1401642 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2411515 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1009873 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1401642 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2411515 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014917 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248771 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136869 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383439 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383439 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014917 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277696 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014917 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277696 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 85617.481612 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62900.284632 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 64084.999006 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7513.078947 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7513.078947 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81405.853802 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81405.853802 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69030.650466 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69030.650466 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301053 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301053 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1008431 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1401994 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2410425 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1008431 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1401994 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2410425 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014947 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248683 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136940 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.619048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.619048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383514 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383514 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014947 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277635 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167736 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014947 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277635 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167736 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80744.443177 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65097.718016 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65914.185236 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7910.153846 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7910.153846 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82643.410236 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82643.410236 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80744.443177 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70302.154659 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70691.445745 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80744.443177 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70302.154659 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70691.445745 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1082,72 +1130,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75925 # number of writebacks -system.cpu.l2cache.writebacks::total 75925 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75936 # number of writebacks +system.cpu.l2cache.writebacks::total 75936 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273792 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288855 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115439 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115439 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389231 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404294 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389231 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1098682007 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13807789270 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14906471277 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 531034 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 531034 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7972002643 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7972002643 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1098682007 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21779791913 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22878473920 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1098682007 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21779791913 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22878473920 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333925000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333925000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882616000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882616000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216541000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216541000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248771 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136869 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383439 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383439 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167651 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167651 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72939.122817 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50431.675396 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51605.377359 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69058.140169 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69058.140169 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15072 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273785 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288857 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115458 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115458 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404315 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404315 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1026861258 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14410483773 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15437345031 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 542534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 542534 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8118910641 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8118910641 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1026861258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22529394414 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23556255672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1026861258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22529394414 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23556255672 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334047500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334047500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882613000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882613000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216660500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216660500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248683 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136940 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277635 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277635 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167736 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68130.391322 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52634.307113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53442.862839 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13911.128205 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13911.128205 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70319.169230 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70319.169230 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1155,161 +1203,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401048 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1401398 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994568 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11815525 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401910 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.428162 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994568 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203713 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186169 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186169 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11406177 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11406177 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11406177 # number of overall hits -system.cpu.dcache.overall_hits::total 11406177 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1806828 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1806828 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1943975 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1943975 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22707 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22707 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7210216 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7210216 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203313 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203313 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186240 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186240 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11413529 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11413529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11413529 # number of overall hits +system.cpu.dcache.overall_hits::total 11413529 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1806580 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1806580 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1944438 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1944438 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22731 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22731 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3750803 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3750803 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3750803 # number of overall misses -system.cpu.dcache.overall_misses::total 3750803 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39803546178 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39803546178 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76325479834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76325479834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321955499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 321955499 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3751018 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3751018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3751018 # number of overall misses +system.cpu.dcache.overall_misses::total 3751018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40329752439 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40329752439 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77181819403 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77181819403 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321716499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 321716499 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 116129026012 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 116129026012 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 116129026012 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 116129026012 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9009292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9009292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208876 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208876 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215522 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215522 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15156980 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15156980 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15156980 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15156980 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200552 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200552 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316212 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108710 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108710 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 117511571842 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117511571842 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117511571842 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117511571842 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208971 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208971 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215517 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215517 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15164547 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15164547 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15164547 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15164547 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200357 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200357 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316284 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316284 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108776 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247464 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247464 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247464 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247464 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22029.515913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22029.515913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39262.583024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39262.583024 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14178.689347 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14178.689347 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.247354 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247354 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247354 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247354 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22323.812086 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22323.812086 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39693.638678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39693.638678 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14153.204830 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14153.204830 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30961.110464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30961.110464 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2958985 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31327.914673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31327.914673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3032993 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 97398 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98350 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.380347 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.838770 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840831 # number of writebacks -system.cpu.dcache.writebacks::total 840831 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 723109 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 723109 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5191 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5191 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2366614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2366614 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2366614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2366614 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083719 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083719 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300470 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300470 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17516 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17516 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840887 # number of writebacks +system.cpu.dcache.writebacks::total 840887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722519 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722519 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643978 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643978 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5197 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5197 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366497 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366497 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366497 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366497 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084061 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084061 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300460 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300460 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17534 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17534 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384189 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384189 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384189 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384189 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26582228002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26582228002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11613303338 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11613303338 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201814751 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201814751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1384521 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384521 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384521 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384521 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27189046254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27189046254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11757002855 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11757002855 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761751 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761751 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38195531340 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38195531340 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38195531340 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38195531340 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424015000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424015000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997805998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997805998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421820998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421820998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083858 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083858 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38946049109 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38946049109 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38946049109 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38946049109 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424137500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424137500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997802998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997802998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421940498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421940498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120227 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048873 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048873 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24528.709012 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24528.709012 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38650.458741 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38650.458741 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11521.737326 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11521.737326 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091300 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091300 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25080.734621 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25080.734621 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39130.010168 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39130.010168 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11449.854625 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11449.854625 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1318,28 +1366,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 6437 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182247 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818706968000 97.77% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64176500 0.00% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554827000 0.03% 97.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40873882000 2.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860199853500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818037303500 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64303500 0.00% 97.74% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561270000 0.03% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41533903500 2.23% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860196780500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694268 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815393 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1378,8 +1426,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175130 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed @@ -1388,19 +1436,19 @@ system.cpu.kern.callpal::rti 5105 2.66% 99.64% # nu system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191976 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326158 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29671097000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2774842500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827753906000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29638597000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2732860000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827825315500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index f5971916a..739cb26e4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,143 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842705 # Number of seconds simulated -sim_ticks 1842705252000 # Number of ticks simulated -final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842698 # Number of seconds simulated +sim_ticks 1842698476000 # Number of ticks simulated +final_tick 1842698476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260475 # Simulator instruction rate (inst/s) -host_op_rate 260475 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6607474809 # Simulator tick rate (ticks/s) -host_mem_usage 309028 # Number of bytes of host memory used -host_seconds 278.88 # Real time elapsed on the host -sim_insts 72641883 # Number of instructions simulated -sim_ops 72641883 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20049216 # Number of bytes read from this memory +host_inst_rate 222585 # Simulator instruction rate (inst/s) +host_op_rate 222585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5605413242 # Simulator tick rate (ticks/s) +host_mem_usage 334468 # Number of bytes of host memory used +host_seconds 328.74 # Real time elapsed on the host +sim_insts 73171582 # Number of instructions simulated +sim_ops 73171582 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 489344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20103680 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2290432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 282112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2525760 # Number of bytes read from this memory -system.physmem.bytes_read::total 28435648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 282112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 917888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory -system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313269 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 144384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2235712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 284736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2526400 # Number of bytes read from this memory +system.physmem.bytes_read::total 28436608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 144384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 284736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7460736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7460736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314120 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2302 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35788 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39465 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444307 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116556 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10880316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1242973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 153097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1370680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15431468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79952 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 153097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498120 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10880316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1242973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 153097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1370680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19479638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 99238 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 44800 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 99238 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 44800 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 6351232 # Total number of bytes read from memory -system.physmem.bytesWritten 2867200 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6351232 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2867200 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6043 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6348 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6059 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6008 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5967 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6045 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2861 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2670 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2847 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3000 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2942 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2703 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2468 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2705 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2852 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2761 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1841692926500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 99238 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 44800 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 67489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.num_reads::cpu1.inst 2256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34933 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39475 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444322 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116574 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116574 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 265558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 78355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1213282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 154521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1371033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15432046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 78355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 154521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 78355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1213282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 154521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1371033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19480856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98004 # Number of read requests accepted +system.physmem.writeReqs 44399 # Number of write requests accepted +system.physmem.readBursts 98004 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44399 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6271808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 2840768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6272256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2841536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6232 # Per bank write bursts +system.physmem.perBankRdBursts::1 6028 # Per bank write bursts +system.physmem.perBankRdBursts::2 6221 # Per bank write bursts +system.physmem.perBankRdBursts::3 6513 # Per bank write bursts +system.physmem.perBankRdBursts::4 5794 # Per bank write bursts +system.physmem.perBankRdBursts::5 6242 # Per bank write bursts +system.physmem.perBankRdBursts::6 5925 # Per bank write bursts +system.physmem.perBankRdBursts::7 6039 # Per bank write bursts +system.physmem.perBankRdBursts::8 6348 # Per bank write bursts +system.physmem.perBankRdBursts::9 6026 # Per bank write bursts +system.physmem.perBankRdBursts::10 6373 # Per bank write bursts +system.physmem.perBankRdBursts::11 5867 # Per bank write bursts +system.physmem.perBankRdBursts::12 5876 # Per bank write bursts +system.physmem.perBankRdBursts::13 6234 # Per bank write bursts +system.physmem.perBankRdBursts::14 6235 # Per bank write bursts +system.physmem.perBankRdBursts::15 6044 # Per bank write bursts +system.physmem.perBankWrBursts::0 2859 # Per bank write bursts +system.physmem.perBankWrBursts::1 2656 # Per bank write bursts +system.physmem.perBankWrBursts::2 2839 # Per bank write bursts +system.physmem.perBankWrBursts::3 3122 # Per bank write bursts +system.physmem.perBankWrBursts::4 2688 # Per bank write bursts +system.physmem.perBankWrBursts::5 2969 # Per bank write bursts +system.physmem.perBankWrBursts::6 2850 # Per bank write bursts +system.physmem.perBankWrBursts::7 2699 # Per bank write bursts +system.physmem.perBankWrBursts::8 3075 # Per bank write bursts +system.physmem.perBankWrBursts::9 2558 # Per bank write bursts +system.physmem.perBankWrBursts::10 2888 # Per bank write bursts +system.physmem.perBankWrBursts::11 2432 # Per bank write bursts +system.physmem.perBankWrBursts::12 2458 # Per bank write bursts +system.physmem.perBankWrBursts::13 2707 # Per bank write bursts +system.physmem.perBankWrBursts::14 2844 # Per bank write bursts +system.physmem.perBankWrBursts::15 2743 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 1841686150500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 98004 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 44399 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -149,362 +151,413 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 15760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 584.832487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.909397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1926.760563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 6603 41.90% 41.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2572 16.32% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1454 9.23% 67.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 899 5.70% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 642 4.07% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 535 3.39% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 370 2.35% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 312 1.98% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 250 1.59% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 195 1.24% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 235 1.49% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 190 1.21% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 101 0.64% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 71 0.45% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 63 0.40% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 80 0.51% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 51 0.32% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 28 0.18% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 32 0.20% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 74 0.47% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 51 0.32% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 34 0.22% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 173 1.10% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 86 0.55% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 27 0.17% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 14 0.09% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 12 0.08% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 22 0.14% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 10 0.06% 96.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 4 0.03% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 2 0.01% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 6 0.04% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 7 0.04% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 1 0.01% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 3 0.02% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 1 0.01% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 2 0.01% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.01% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 2 0.01% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 1 0.01% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 1 0.01% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 2 0.01% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.01% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.01% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.01% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.01% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.01% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.01% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.01% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.01% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.01% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.01% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.01% 96.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 383 2.43% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 6 0.04% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 111 0.70% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 1 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 2 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.02% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 15760 # Bytes accessed per row activation -system.physmem.totQLat 1910826000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3572864750 # Sum of mem lat for all requests -system.physmem.totBusLat 496135000 # Total cycles spent in databus access -system.physmem.totBankLat 1165903750 # Total cycles spent in bank access -system.physmem.avgQLat 19257.12 # Average queueing delay per request -system.physmem.avgBankLat 11749.86 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 36006.98 # Average memory access latency -system.physmem.avgRdBW 3.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 17930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 508.141439 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.008973 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1572.275953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 7528 41.99% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2973 16.58% 58.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1838 10.25% 68.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 1006 5.61% 74.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 670 3.74% 78.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 572 3.19% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 359 2.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 327 1.82% 85.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 240 1.34% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 222 1.24% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 225 1.25% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 213 1.19% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 93 0.52% 90.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 79 0.44% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 78 0.44% 91.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 102 0.57% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 45 0.25% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 56 0.31% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 39 0.22% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 53 0.30% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 119 0.66% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 70 0.39% 94.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 89 0.50% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 16 0.09% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 5 0.03% 95.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 36 0.20% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 6 0.03% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 15 0.08% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 5 0.03% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 11 0.06% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 11 0.06% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 2 0.01% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 1 0.01% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 2 0.01% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.01% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 4 0.02% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 10 0.06% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 3 0.02% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 13 0.07% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 7 0.04% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 13 0.07% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 2 0.01% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 23 0.13% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.01% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 14 0.08% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.01% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 76 0.42% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.01% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 4 0.02% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.01% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 9 0.05% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 5 0.03% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.01% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 8 0.04% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 8 0.04% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 3 0.02% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 4 0.02% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 5 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 20 0.11% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 2 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 4 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.08% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 76 0.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 17930 # Bytes accessed per row activation +system.physmem.totQLat 2684942500 # Total ticks spent queuing +system.physmem.totMemAccLat 4336678750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 489985000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1161751250 # Total ticks spent accessing banks +system.physmem.avgQLat 27398.21 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11854.97 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 44253.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.17 # Average write queue length over time -system.physmem.readRowHits 92920 # Number of row buffer hits during reads -system.physmem.writeRowHits 35346 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.90 # Row buffer hit rate for writes -system.physmem.avgGap 12786160.09 # Average gap between requests -system.membus.throughput 19523578 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 45592 # Transaction distribution -system.membus.trans_dist::ReadResp 45560 # Transaction distribution -system.membus.trans_dist::WriteReq 3756 # Transaction distribution -system.membus.trans_dist::WriteResp 3756 # Transaction distribution -system.membus.trans_dist::Writeback 44800 # Transaction distribution -system.membus.trans_dist::UpgradeReq 46 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47 # Transaction distribution -system.membus.trans_dist::ReadExReq 56741 # Transaction distribution -system.membus.trans_dist::ReadExResp 56741 # Transaction distribution -system.membus.trans_dist::BadAddressError 32 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 191660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 64 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 205046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51865 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 51865 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 256911 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15754 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7009472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 7025226 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2208960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2208960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9234186 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35966088 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12465000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.18 # Average write queue length when enqueuing +system.physmem.readRowHits 89612 # Number of row buffer hits during reads +system.physmem.writeRowHits 34842 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.47 # Row buffer hit rate for writes +system.physmem.avgGap 12932916.80 # Average gap between requests +system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19524796 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44746 # Transaction distribution +system.membus.trans_dist::ReadResp 44539 # Transaction distribution +system.membus.trans_dist::WriteReq 3750 # Transaction distribution +system.membus.trans_dist::WriteResp 3750 # Transaction distribution +system.membus.trans_dist::Writeback 44399 # Transaction distribution +system.membus.trans_dist::UpgradeReq 43 # Transaction distribution +system.membus.trans_dist::UpgradeResp 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 56527 # Transaction distribution +system.membus.trans_dist::ReadExResp 56527 # Transaction distribution +system.membus.trans_dist::BadAddressError 207 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 203660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 254372 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15690 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6953984 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6969674 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9129482 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35968328 # Total data (bytes) +system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12460500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 516080000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 511769750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 39000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 256500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 771793954 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 762797456 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 156435750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 153003500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 337384 # number of replacements -system.l2c.tags.tagsinuse 65423.390976 # Cycle average of tags in use -system.l2c.tags.total_refs 2471195 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402547 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.138898 # Average number of references to valid blocks. +system.l2c.tags.replacements 337399 # number of replacements +system.l2c.tags.tagsinuse 65421.710089 # Cycle average of tags in use +system.l2c.tags.total_refs 2471820 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402562 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.140222 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54840.022307 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2455.785986 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2733.317890 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 573.564095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 593.217562 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2104.783507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2122.699630 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836792 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.037472 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009052 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032116 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.032390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998282 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 518817 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124693 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 293247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239325 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1753041 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits -system.l2c.Writeback_hits::total 835257 # number of Writeback hits +system.l2c.tags.occ_blocks::writebacks 54901.425298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2456.924718 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2698.289857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 528.309889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 619.621947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2142.597203 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2074.541175 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837729 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041173 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032693 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.031655 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998256 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 520374 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 492975 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124091 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 84248 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 292559 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239147 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1753394 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835552 # number of Writeback hits +system.l2c.Writeback_hits::total 835552 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92556 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26552 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67733 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186841 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 518817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 585785 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 110282 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 293247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 307058 # number of demand (read+write) hits -system.l2c.demand_hits::total 1939882 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 518817 # number of overall hits -system.l2c.overall_hits::cpu0.data 585785 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124693 # number of overall hits -system.l2c.overall_hits::cpu1.data 110282 # number of overall hits -system.l2c.overall_hits::cpu2.inst 293247 # number of overall hits -system.l2c.overall_hits::cpu2.data 307058 # number of overall hits -system.l2c.overall_hits::total 1939882 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7632 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 237318 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2302 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 17365 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4408 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 18542 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287567 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 92855 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26292 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67775 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186922 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 520374 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 585830 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 124091 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 110540 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 292559 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 306922 # number of demand (read+write) hits +system.l2c.demand_hits::total 1940316 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 520374 # number of overall hits +system.l2c.overall_hits::cpu0.data 585830 # number of overall hits +system.l2c.overall_hits::cpu1.inst 124091 # number of overall hits +system.l2c.overall_hits::cpu1.data 110540 # number of overall hits +system.l2c.overall_hits::cpu2.inst 292559 # number of overall hits +system.l2c.overall_hits::cpu2.data 306922 # number of overall hits +system.l2c.overall_hits::total 1940316 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7646 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 238323 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2256 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 16912 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4449 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 18154 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287740 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76225 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 18470 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 21026 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115721 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7632 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 313543 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2302 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 35835 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4408 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 39568 # number of demand (read+write) misses -system.l2c.demand_misses::total 403288 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7632 # number of overall misses -system.l2c.overall_misses::cpu0.data 313543 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2302 # number of overall misses -system.l2c.overall_misses::cpu1.data 35835 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4408 # number of overall misses -system.l2c.overall_misses::cpu2.data 39568 # number of overall misses -system.l2c.overall_misses::total 403288 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 186892499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1138263250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 380152250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1198688249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2903996248 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 263498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 263498 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1209958491 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1715474224 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2925432715 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 186892499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2348221741 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 380152250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2914162473 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5829428963 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 186892499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2348221741 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 380152250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2914162473 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5829428963 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 526449 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 730547 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 126995 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 101095 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 297655 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 257867 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2040608 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_misses::cpu2.data 10 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 76073 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 18069 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 21595 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115737 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7646 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 314396 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2256 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 34981 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4449 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 39749 # number of demand (read+write) misses +system.l2c.demand_misses::total 403477 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7646 # number of overall misses +system.l2c.overall_misses::cpu0.data 314396 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2256 # number of overall misses +system.l2c.overall_misses::cpu1.data 34981 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4449 # number of overall misses +system.l2c.overall_misses::cpu2.data 39749 # number of overall misses +system.l2c.overall_misses::total 403477 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 174436247 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1133429750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 361724750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1201174749 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2870765496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 294997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 294997 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1255826741 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1783349726 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3039176467 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 174436247 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2389256491 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 361724750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2984524475 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 5909941963 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 174436247 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2389256491 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 361724750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2984524475 # number of overall miss cycles +system.l2c.overall_miss_latency::total 5909941963 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 528020 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 731298 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 126347 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 101160 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 297008 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 257301 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2041134 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835552 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835552 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 168781 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 45022 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 88759 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302562 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 526449 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 899328 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 126995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 146117 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 297655 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 346626 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2343170 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 526449 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 899328 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 126995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 146117 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 297655 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 346626 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2343170 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014497 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.324850 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018127 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.171769 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014809 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.071905 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.140922 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_accesses::cpu2.data 13 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 168928 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 44361 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 89370 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302659 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 528020 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 900226 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 126347 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 145521 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 297008 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 346671 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2343793 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 528020 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 900226 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 126347 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 145521 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 297008 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 346671 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2343793 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014481 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.325890 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.017856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.167181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.014979 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.070555 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.140971 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.785714 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.730769 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.500000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.451621 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.410244 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.236889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382470 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014497 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.348641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018127 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.245249 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014809 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.114152 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172112 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014497 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.348641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018127 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.245249 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014809 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.114152 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172112 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81187.010860 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 65549.280161 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86241.436025 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 64647.192806 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 10098.503124 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 23954.363636 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 13868.315789 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 65509.393124 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81588.234757 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 25280.050423 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81187.010860 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 65528.721669 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 86241.436025 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 73649.476168 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 14454.754327 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81187.010860 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 65528.721669 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 86241.436025 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 73649.476168 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 14454.754327 # average overall miss latency +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.769231 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.720000 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.450328 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.407317 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.241636 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382401 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014481 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.349241 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.017856 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.240385 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014979 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.114659 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172147 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014481 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.349241 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.017856 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.240385 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014979 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.114659 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172147 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77321.031472 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 67019.261471 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 81304.731400 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 66165.844938 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9976.942712 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29499.700000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16388.722222 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69501.728983 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82581.603427 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 26259.333377 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77321.031472 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 68301.549155 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 81304.731400 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75084.265642 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 14647.531242 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77321.031472 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 68301.549155 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 81304.731400 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75084.265642 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 14647.531242 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,105 +566,97 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75044 # number of writebacks -system.l2c.writebacks::total 75044 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2302 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 17365 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4408 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 18542 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 42617 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 18470 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 21026 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 39496 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2302 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 35835 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4408 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 39568 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 82113 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2302 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 35835 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4408 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 39568 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 82113 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 157803001 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 920718250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 324243750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 970102251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2372867252 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 261008 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 261008 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 978413509 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1456000776 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2434414285 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 157803001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1899131759 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 324243750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2426103027 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4807281537 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 157803001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1899131759 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 324243750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2426103027 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4807281537 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 275693000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 292819000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 568512000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 341668500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 404628500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 746297000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 617361500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 697447500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1314809000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018127 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.171769 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.071905 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020884 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.785714 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.423077 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.410244 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.236889 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.130539 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018127 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.245249 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014809 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.114152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.035044 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018127 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.245249 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014809 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.114152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.035044 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 53021.494385 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 52319.180833 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 55678.889927 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23728 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23728 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 52973.119058 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69247.635118 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61636.983112 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52996.560876 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61314.775248 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58544.707135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68550.391399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52996.560876 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73558.019510 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61314.775248 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58544.707135 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75062 # number of writebacks +system.l2c.writebacks::total 75062 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2256 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 16912 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4449 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 18154 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41771 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 10 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 18069 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 21595 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 39664 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2256 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 34981 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4449 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 39749 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 81435 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2256 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 34981 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4449 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 39749 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 81435 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 146027753 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 921761250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 305687750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 999134251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2372611004 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 259007 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 259007 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1029550759 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1518288274 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2547839033 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 146027753 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1951312009 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 305687750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2517422525 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4920450037 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 146027753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1951312009 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 305687750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2517422525 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4920450037 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277798500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 291495500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 569294000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 343775500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402311000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 746086500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 621574000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 693806500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1315380500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167181 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.070555 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020465 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.769231 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407317 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241636 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.131052 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034745 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034745 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54503.385170 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55036.589787 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 56800.435805 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 25900.700000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 25900.700000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56978.845481 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70307.398657 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64235.554483 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55782.053372 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55782.053372 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -623,14 +668,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254957 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254914 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694872745000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254957 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078435 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078435 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694870261000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254914 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078432 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078432 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -639,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9629212 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9629212 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4353407559 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4353407559 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4363036771 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4363036771 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4363036771 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4363036771 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9304463 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9304463 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5314395237 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5314395237 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5323699700 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5323699700 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5323699700 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5323699700 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -663,56 +708,56 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55660.184971 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 55660.184971 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104770.108755 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 104770.108755 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 104566.489419 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 104566.489419 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 104566.489419 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 114649 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53783.023121 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53783.023121 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127897.459497 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127897.459497 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127590.166567 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127590.166567 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 168405 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11461 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12345 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.003403 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.641555 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17350 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 17350 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5987712 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5987712 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3454277559 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3454277559 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3460265271 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3460265271 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3460265271 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3460265271 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.415818 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415818 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.415818 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85538.742857 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 85538.742857 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199900.321701 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199900.321701 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199438.920519 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 199438.920519 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5715463 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5715463 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435167237 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4435167237 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4440882700 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4440882700 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4440882700 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4440882700 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82832.797101 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82832.797101 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262498.060902 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 262498.060902 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -730,22 +775,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4909978 # DTB read hits -system.cpu0.dtb.read_misses 6100 # DTB read misses +system.cpu0.dtb.read_hits 4920992 # DTB read hits +system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428319 # DTB read accesses -system.cpu0.dtb.write_hits 3504299 # DTB write hits -system.cpu0.dtb.write_misses 671 # DTB write misses +system.cpu0.dtb.read_accesses 428234 # DTB read accesses +system.cpu0.dtb.write_hits 3511178 # DTB write hits +system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 163761 # DTB write accesses -system.cpu0.dtb.data_hits 8414277 # DTB hits -system.cpu0.dtb.data_misses 6771 # DTB misses +system.cpu0.dtb.write_accesses 163777 # DTB write accesses +system.cpu0.dtb.data_hits 8432170 # DTB hits +system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592080 # DTB accesses -system.cpu0.itb.fetch_hits 2758234 # ITB hits +system.cpu0.dtb.data_accesses 592011 # DTB accesses +system.cpu0.itb.fetch_hits 2763046 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2761268 # ITB accesses +system.cpu0.itb.fetch_accesses 2766080 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -758,51 +803,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928316891 # number of cpu cycles simulated +system.cpu0.numCycles 928344318 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33736461 # Number of instructions committed -system.cpu0.committedOps 33736461 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31599588 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169686 # Number of float alu accesses -system.cpu0.num_func_calls 810809 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4665593 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31599588 # number of integer instructions -system.cpu0.num_fp_insts 169686 # number of float instructions -system.cpu0.num_int_register_reads 44374544 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23060255 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87629 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89168 # number of times the floating registers were written -system.cpu0.num_mem_refs 8444409 # number of memory refs -system.cpu0.num_load_insts 4931349 # Number of load instructions -system.cpu0.num_store_insts 3513060 # Number of store instructions -system.cpu0.num_idle_cycles 903633014.989213 # Number of idle cycles -system.cpu0.num_busy_cycles 24683876.010787 # Number of busy cycles -system.cpu0.not_idle_fraction 0.026590 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.973410 # Percentage of idle cycles +system.cpu0.committedInsts 33880492 # Number of instructions committed +system.cpu0.committedOps 33880492 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31739536 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169894 # Number of float alu accesses +system.cpu0.num_func_calls 813170 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4699422 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31739536 # number of integer instructions +system.cpu0.num_fp_insts 169894 # number of float instructions +system.cpu0.num_int_register_reads 44596322 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23159667 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87728 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89270 # number of times the floating registers were written +system.cpu0.num_mem_refs 8462332 # number of memory refs +system.cpu0.num_load_insts 4942381 # Number of load instructions +system.cpu0.num_store_insts 3519951 # Number of store instructions +system.cpu0.num_idle_cycles 904625586.132235 # Number of idle cycles +system.cpu0.num_busy_cycles 23718731.867765 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211396 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6416 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211386 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182586 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819515680500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39349500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365678500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22783774000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842704482500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819501633500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38918500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365019000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22792135500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842697706500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694800 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815835 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694791 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815828 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -841,7 +886,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175327 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -850,20 +895,20 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192242 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1909 +system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29786026000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2614250500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810304201500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391309 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29773270000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2593332500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810331099500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -896,444 +941,427 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110422039 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 786602 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 786555 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3756 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3756 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371447 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 15 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 151061 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133781 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 32 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 849315 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370344 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2219659 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27177600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55325386 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82502986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203464200 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 11072 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2135432500 # Layer occupancy (ticks) +system.toL2Bus.throughput 110448008 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 784800 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 784578 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3750 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3750 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371852 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150627 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133731 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 207 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846719 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1369630 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2216349 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27094720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55304714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82399434 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203511688 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10688 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2136322000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1913139810 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1907046997 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2237602233 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2233138904 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469136 # Throughput (bytes/s) +system.iobus.throughput 1469141 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 2975 # Transaction distribution system.iobus.trans_dist::ReadResp 2975 # Transaction distribution -system.iobus.trans_dist::WriteReq 21036 # Transaction distribution -system.iobus.trans_dist::WriteResp 21036 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 20646 # Transaction distribution +system.iobus.trans_dist::WriteResp 20646 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8320 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2420 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13322 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 48022 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47242 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4186 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15754 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1123130 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15690 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098482 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6200000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6239000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1827000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 157303021 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 153606200 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9566000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9562000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17990250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17411500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 950451 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.192015 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43221003 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 950962 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.449769 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10381115250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 246.999230 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.674980 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.517805 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.482420 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194678 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321324 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998422 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 33216972 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7763860 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2240171 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43221003 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33216972 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7763860 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2240171 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43221003 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33216972 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7763860 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2240171 # number of overall hits -system.cpu0.icache.overall_hits::total 43221003 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 526470 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 126995 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 313704 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 967169 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 526470 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 126995 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 313704 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 967169 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 526470 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 126995 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 313704 # number of overall misses -system.cpu0.icache.overall_misses::total 967169 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1823123501 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4463889198 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6287012699 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1823123501 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4463889198 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6287012699 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1823123501 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4463889198 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6287012699 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33743442 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7890855 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2553875 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44188172 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33743442 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7890855 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2553875 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44188172 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33743442 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7890855 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2553875 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44188172 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015602 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016094 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122835 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021888 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015602 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016094 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122835 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021888 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015602 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016094 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122835 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021888 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14355.868349 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14229.621548 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6500.428259 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14355.868349 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14229.621548 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6500.428259 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14355.868349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14229.621548 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6500.428259 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4785 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 202 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.688119 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 950723 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.190316 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43428114 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 951234 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.654501 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10399272250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.695807 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.603495 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 159.891014 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.491593 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194538 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312287 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 33359431 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7828902 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2239781 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43428114 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 33359431 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7828902 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2239781 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43428114 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 33359431 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7828902 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2239781 # number of overall hits +system.cpu0.icache.overall_hits::total 43428114 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 528040 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 126347 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 313191 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 967578 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 528040 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 126347 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 313191 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 967578 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 528040 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 126347 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 313191 # number of overall misses +system.cpu0.icache.overall_misses::total 967578 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1802440753 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4440627379 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6243068132 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1802440753 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4440627379 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6243068132 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1802440753 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4440627379 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6243068132 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 33887471 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7955249 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2552972 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44395692 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 33887471 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7955249 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2552972 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44395692 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 33887471 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7955249 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2552972 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44395692 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015582 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015882 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122677 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.021794 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015582 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015882 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122677 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.021794 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015582 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015882 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122677 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.021794 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14265.797787 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14178.655769 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6452.263416 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14265.797787 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14178.655769 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6452.263416 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14265.797787 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14178.655769 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6452.263416 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4969 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 740 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 199 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.969849 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 740 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16034 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16034 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16034 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16034 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16034 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16034 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126995 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297670 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 424665 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 126995 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 297670 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 424665 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 126995 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 297670 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 424665 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1568013499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3675865433 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5243878932 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1568013499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3675865433 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5243878932 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1568013499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3675865433 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5243878932 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016094 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116556 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009610 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016094 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116556 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009610 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016094 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116556 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009610 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12347.049089 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.272007 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12347.049089 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12347.049089 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12348.793741 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.272007 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16174 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16174 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16174 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16174 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16174 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16174 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126347 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297017 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 423364 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 126347 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 297017 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 423364 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 126347 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 297017 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 423364 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1548840247 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3650495745 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5199335992 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1548840247 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3650495745 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5199335992 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1548840247 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3650495745 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5199335992 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009536 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009536 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009536 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12281.006396 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12281.006396 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12281.006396 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1391525 # number of replacements +system.cpu0.dcache.tags.replacements 1391697 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13285085 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1392037 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.543629 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13286622 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1392209 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.543554 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 250.196143 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.348399 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.453270 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.488664 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254587 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.256745 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 248.161883 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.279675 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 133.556253 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.484691 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254452 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.260852 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4073389 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1086662 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2399601 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7559652 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3208453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 837545 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1295843 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5341841 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116948 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19346 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47955 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184249 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126113 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21379 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51797 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199289 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7281842 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1924207 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3695444 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12901493 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7281842 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1924207 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3695444 # number of overall hits -system.cpu0.dcache.overall_hits::total 12901493 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 720818 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 98930 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 533963 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1353711 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 168792 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 45023 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 591984 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 805799 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9729 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4083341 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1084976 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2395652 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7563969 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3214796 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 832699 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1291573 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5339068 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117279 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19300 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47662 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184241 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126504 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21337 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51447 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199288 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7298137 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1917675 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3687225 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12903037 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7298137 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1917675 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3687225 # number of overall hits +system.cpu0.dcache.overall_hits::total 12903037 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 721507 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 98995 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 533015 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1353517 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 168939 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44362 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 596400 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 809701 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9791 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2165 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6797 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18691 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 889610 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 143953 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1125947 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2159510 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 889610 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 143953 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1125947 # number of overall misses -system.cpu0.dcache.overall_misses::total 2159510 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2262060250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9361678086 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11623738336 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1620272009 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17690504226 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19310776235 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28582500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102574499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 131156999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 38001 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 38001 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3882332259 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27052182312 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 30934514571 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3882332259 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27052182312 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 30934514571 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4794207 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1185592 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2933564 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8913363 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3377245 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 882568 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1887827 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6147640 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126677 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21511 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54752 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 202940 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126113 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21379 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51799 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199291 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8171452 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2068160 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4821391 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15061003 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8171452 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2068160 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4821391 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15061003 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150352 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083444 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182019 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151874 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049979 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051014 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.313580 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131075 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076802 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100646 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124142 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092101 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000039 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108868 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069604 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233532 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143384 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108868 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069604 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233532 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.143384 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22865.260790 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17532.447166 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8586.573010 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35987.650956 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 29883.416150 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23964.755770 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13202.078522 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15091.143004 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7017.120486 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 19000.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26969.443214 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24026.159590 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14324.784127 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26969.443214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24026.159590 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14324.784127 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 557875 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 852 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 17918 # number of cycles access was blocked +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6803 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18759 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 890446 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 143357 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1129415 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2163218 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 890446 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 143357 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1129415 # number of overall misses +system.cpu0.dcache.overall_misses::total 2163218 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2262107000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9348260996 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11610367996 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1660998759 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18147263609 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19808262368 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28538250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102812500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 131350750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 3923105759 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27495524605 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31418630364 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3923105759 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27495524605 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31418630364 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4804848 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1183971 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 2928667 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8917486 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383735 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 877061 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1887973 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6148769 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127070 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21465 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54465 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203000 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21337 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51447 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199288 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8188583 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2061032 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 4816640 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15066255 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8188583 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2061032 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 4816640 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15066255 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150162 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083613 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181999 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.151782 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049927 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050580 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315894 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131685 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077052 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100862 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124906 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092409 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108742 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069556 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234482 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.143580 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108742 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069556 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234482 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.143580 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22850.719733 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17538.457634 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8577.925505 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37441.926852 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30428.007393 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24463.675317 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.639723 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15112.817874 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7002.012367 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14524.024099 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14524.024099 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 591087 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 822 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 17697 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 31.134892 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 121.714286 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33.400407 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 117.428571 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835257 # number of writebacks -system.cpu0.dcache.writebacks::total 835257 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 281255 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 281255 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 503456 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 503456 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1394 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1394 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 784711 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 784711 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 784711 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 784711 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98930 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252708 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 351638 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 45023 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88528 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133551 # number of WriteReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 835552 # number of writebacks +system.cpu0.dcache.writebacks::total 835552 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280898 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 280898 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507265 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 507265 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1373 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 788163 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 788163 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 788163 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 788163 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98995 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252117 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 351112 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44362 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89135 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133497 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2165 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5403 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7568 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 143953 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 341236 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 485189 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 143953 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 341236 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 485189 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2055649750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4240939408 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6296589158 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1521155991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2563125747 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4084281738 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24249500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66698251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90947751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3576805741 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6804065155 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10380870896 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3576805741 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6804065155 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10380870896 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 294283500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312003000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 606286500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 361937500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429433000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791370500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 656221000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 741436000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397657000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083444 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086144 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051014 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046894 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098681 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037292 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032215 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069604 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070775 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032215 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20778.830992 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16781.975276 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17906.452539 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33786.197965 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28952.712667 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30582.187614 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11200.692841 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12344.669813 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12017.408959 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16999.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24847.038554 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19939.470498 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21395.519882 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5430 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7595 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 143357 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 341252 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484609 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 143357 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341252 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484609 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2056105000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4263367239 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6319472239 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1563762241 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2632845749 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4196607990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24206750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66163500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90370250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3619867241 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6896212988 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10516080229 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3619867241 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6896212988 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10516080229 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296519000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310561500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607080500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364164500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426924000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791088500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660683500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737485500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1398169000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083613 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086086 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039373 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047212 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021711 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100862 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099697 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037414 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032165 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032165 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20769.786353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16910.272766 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.451318 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35250.039245 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29537.732081 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31435.972269 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11180.946882 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12184.806630 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.650428 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1348,22 +1376,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1205047 # DTB read hits -system.cpu1.dtb.read_misses 1367 # DTB read misses +system.cpu1.dtb.read_hits 1203387 # DTB read hits +system.cpu1.dtb.read_misses 1366 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142944 # DTB read accesses -system.cpu1.dtb.write_hits 904403 # DTB write hits -system.cpu1.dtb.write_misses 185 # DTB write misses -system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58533 # DTB write accesses -system.cpu1.dtb.data_hits 2109450 # DTB hits -system.cpu1.dtb.data_misses 1552 # DTB misses -system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 201477 # DTB accesses -system.cpu1.itb.fetch_hits 861634 # ITB hits -system.cpu1.itb.fetch_misses 693 # ITB misses +system.cpu1.dtb.read_accesses 142939 # DTB read accesses +system.cpu1.dtb.write_hits 898859 # DTB write hits +system.cpu1.dtb.write_misses 183 # DTB write misses +system.cpu1.dtb.write_acv 22 # DTB write access violations +system.cpu1.dtb.write_accesses 58529 # DTB write accesses +system.cpu1.dtb.data_hits 2102246 # DTB hits +system.cpu1.dtb.data_misses 1549 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 201468 # DTB accesses +system.cpu1.itb.fetch_hits 859133 # ITB hits +system.cpu1.itb.fetch_misses 692 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 862327 # ITB accesses +system.cpu1.itb.fetch_accesses 859825 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1376,28 +1404,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953630418 # number of cpu cycles simulated +system.cpu1.numCycles 953620014 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7889245 # Number of instructions committed -system.cpu1.committedOps 7889245 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7344952 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44937 # Number of float alu accesses -system.cpu1.num_func_calls 213049 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 993802 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7344952 # number of integer instructions -system.cpu1.num_fp_insts 44937 # number of float instructions -system.cpu1.num_int_register_reads 10269748 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5343251 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24271 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24577 # number of times the floating registers were written -system.cpu1.num_mem_refs 2116682 # number of memory refs -system.cpu1.num_load_insts 1209934 # Number of load instructions -system.cpu1.num_store_insts 906748 # Number of store instructions -system.cpu1.num_idle_cycles 923700977.463911 # Number of idle cycles -system.cpu1.num_busy_cycles 29929440.536089 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031385 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968615 # Percentage of idle cycles +system.cpu1.committedInsts 7953643 # Number of instructions committed +system.cpu1.committedOps 7953643 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7410219 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45003 # Number of float alu accesses +system.cpu1.num_func_calls 212713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1020267 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7410219 # number of integer instructions +system.cpu1.num_fp_insts 45003 # number of float instructions +system.cpu1.num_int_register_reads 10384111 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5386902 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24304 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24611 # number of times the floating registers were written +system.cpu1.num_mem_refs 2109479 # number of memory refs +system.cpu1.num_load_insts 1208276 # Number of load instructions +system.cpu1.num_store_insts 901203 # Number of store instructions +system.cpu1.num_idle_cycles 922135498.680812 # Number of idle cycles +system.cpu1.num_busy_cycles 31484515.319188 # Number of busy cycles +system.cpu1.not_idle_fraction 0.033016 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.966984 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1415,35 +1443,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9022316 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8342315 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 122648 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7529449 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6410701 # Number of BTB hits +system.cpu2.branchPred.lookups 9128355 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8449925 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 124319 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7461780 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6520544 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.141702 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 283187 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 12478 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 87.385905 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 281902 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13317 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3192037 # DTB read hits -system.cpu2.dtb.read_misses 11608 # DTB read misses +system.cpu2.dtb.read_hits 3185589 # DTB read hits +system.cpu2.dtb.read_misses 11798 # DTB read misses system.cpu2.dtb.read_acv 121 # DTB read access violations -system.cpu2.dtb.read_accesses 216573 # DTB read accesses -system.cpu2.dtb.write_hits 2009173 # DTB write hits -system.cpu2.dtb.write_misses 2522 # DTB write misses +system.cpu2.dtb.read_accesses 217406 # DTB read accesses +system.cpu2.dtb.write_hits 2009886 # DTB write hits +system.cpu2.dtb.write_misses 2608 # DTB write misses system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 81978 # DTB write accesses -system.cpu2.dtb.data_hits 5201210 # DTB hits -system.cpu2.dtb.data_misses 14130 # DTB misses +system.cpu2.dtb.write_accesses 82301 # DTB write accesses +system.cpu2.dtb.data_hits 5195475 # DTB hits +system.cpu2.dtb.data_misses 14406 # DTB misses system.cpu2.dtb.data_acv 227 # DTB access violations -system.cpu2.dtb.data_accesses 298551 # DTB accesses -system.cpu2.itb.fetch_hits 369667 # ITB hits -system.cpu2.itb.fetch_misses 5681 # ITB misses -system.cpu2.itb.fetch_acv 262 # ITB acv -system.cpu2.itb.fetch_accesses 375348 # ITB accesses +system.cpu2.dtb.data_accesses 299707 # DTB accesses +system.cpu2.itb.fetch_hits 369992 # ITB hits +system.cpu2.itb.fetch_misses 5727 # ITB misses +system.cpu2.itb.fetch_acv 273 # ITB acv +system.cpu2.itb.fetch_accesses 375719 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1456,270 +1484,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31245078 # number of cpu cycles simulated +system.cpu2.numCycles 31308710 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8348883 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36663716 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9022316 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6693888 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8736568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 602984 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9694630 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 11222 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1957 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63711 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 86195 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2553880 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 85053 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27335965 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.341226 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.294449 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8320877 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36988805 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9128355 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6802446 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8846835 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 603748 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9639992 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 11047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63718 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87241 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2552980 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 86276 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27364450 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.351710 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.294118 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18599397 68.04% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269863 0.99% 69.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 429102 1.57% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4885317 17.87% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 756803 2.77% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 166340 0.61% 91.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 191609 0.70% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 429140 1.57% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1608394 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18517615 67.67% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 268760 0.98% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 429758 1.57% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4997201 18.26% 88.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 759565 2.78% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 164512 0.60% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 190396 0.70% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 427414 1.56% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1609229 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27335965 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288760 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.173424 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8495766 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9778515 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8128034 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 307242 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 380496 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165135 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12538 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36269918 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39153 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 380496 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8853799 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2797423 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5789351 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7998658 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1270334 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35131949 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2438 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 231189 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 444117 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23541427 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 43931372 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43874902 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52705 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21760313 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1781114 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 501831 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59191 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3719256 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3350609 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2097879 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 369762 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 260934 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32641753 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 622044 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32196803 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34835 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2138258 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1073109 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 438824 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27335965 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.177818 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.573987 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27364450 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.291560 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.181422 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8471005 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9721532 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8236973 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308822 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 380199 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165870 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12770 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36596033 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40157 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 380199 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8829996 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2781091 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5750095 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8109315 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1267845 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35455371 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2432 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 230458 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 443882 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23756988 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44373855 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44317462 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52634 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21971271 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1785717 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 500561 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59005 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3706520 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3341982 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2099682 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 368903 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 258103 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32963824 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 619272 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32519364 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 32677 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2138512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1074729 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 437003 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27364450 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.188380 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.575952 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15167963 55.49% 55.49% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3067850 11.22% 66.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1557003 5.70% 72.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5712284 20.90% 93.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 903378 3.30% 96.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480833 1.76% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 285081 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142652 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18921 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15094542 55.16% 55.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3058510 11.18% 66.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1555503 5.68% 72.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5825063 21.29% 93.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 904805 3.31% 96.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480018 1.75% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 285628 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141467 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18914 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27335965 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27364450 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33684 13.60% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113022 45.64% 59.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100957 40.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33388 13.55% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112327 45.58% 59.13% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100703 40.87% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26526068 82.39% 82.39% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20082 0.06% 82.46% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8432 0.03% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3318552 10.31% 92.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2030927 6.31% 99.10% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289082 0.90% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26855600 82.58% 82.59% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20032 0.06% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8424 0.03% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3311528 10.18% 92.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2031960 6.25% 99.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288160 0.89% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32196803 # Type of FU issued -system.cpu2.iq.rate 1.030460 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 247663 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007692 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 91777621 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35291242 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 31803164 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234448 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114643 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110912 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32319915 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122111 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186470 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32519364 # Type of FU issued +system.cpu2.iq.rate 1.038668 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 246418 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007578 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92448223 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35610975 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32122316 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234050 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114559 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110669 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32641435 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121907 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186593 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 409308 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1087 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 154806 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 407978 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1104 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4025 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 156833 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4179 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 28515 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4157 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 26970 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 380496 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2018433 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 205280 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34533473 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 223572 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3350609 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2097879 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 552418 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 143005 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2030 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3940 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62474 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127218 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 189692 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32041792 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3211958 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 155011 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 380199 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2010765 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204147 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34852291 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 222063 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3341982 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2099682 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 549953 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 141753 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1988 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4025 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63582 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127875 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 191457 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32361861 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3205658 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 157503 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1269676 # number of nop insts executed -system.cpu2.iew.exec_refs 5228104 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7451179 # Number of branches executed -system.cpu2.iew.exec_stores 2016146 # Number of stores executed -system.cpu2.iew.exec_rate 1.025499 # Inst execution rate -system.cpu2.iew.wb_sent 31946323 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31914076 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18560539 # num instructions producing a value -system.cpu2.iew.wb_consumers 21756623 # num instructions consuming a value +system.cpu2.iew.exec_nop 1269195 # number of nop insts executed +system.cpu2.iew.exec_refs 5222587 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7560841 # Number of branches executed +system.cpu2.iew.exec_stores 2016929 # Number of stores executed +system.cpu2.iew.exec_rate 1.033638 # Inst execution rate +system.cpu2.iew.wb_sent 32266608 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32232985 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18776213 # num instructions producing a value +system.cpu2.iew.wb_consumers 21965918 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.021411 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.853098 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.029521 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.854788 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2307107 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 183220 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 175579 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26955469 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.193861 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846623 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2305690 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182269 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 176747 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26984251 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.204438 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.848007 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16175286 60.01% 60.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2330504 8.65% 68.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1226068 4.55% 73.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5456953 20.24% 93.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503178 1.87% 95.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186113 0.69% 96.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 177622 0.66% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179384 0.67% 97.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 720361 2.67% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16102351 59.67% 59.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2321930 8.60% 68.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1225737 4.54% 72.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5569081 20.64% 93.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 502606 1.86% 95.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185666 0.69% 96.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 176683 0.65% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180209 0.67% 97.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 719988 2.67% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26955469 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32181084 # Number of instructions committed -system.cpu2.commit.committedOps 32181084 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26984251 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32500866 # Number of instructions committed +system.cpu2.commit.committedOps 32500866 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4884374 # Number of memory references committed -system.cpu2.commit.loads 2941301 # Number of loads committed -system.cpu2.commit.membars 64148 # Number of memory barriers committed -system.cpu2.commit.branches 7305681 # Number of branches committed -system.cpu2.commit.fp_insts 109768 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30735120 # Number of committed integer instructions. -system.cpu2.commit.function_calls 229363 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 720361 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4876853 # Number of memory references committed +system.cpu2.commit.loads 2934004 # Number of loads committed +system.cpu2.commit.membars 63840 # Number of memory barriers committed +system.cpu2.commit.branches 7415854 # Number of branches committed +system.cpu2.commit.fp_insts 109494 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31057555 # Number of committed integer instructions. +system.cpu2.commit.function_calls 228510 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 719988 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60649307 # The number of ROB reads -system.cpu2.rob.rob_writes 69356385 # The number of ROB writes -system.cpu2.timesIdled 245741 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3909113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746532644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31016177 # Number of Instructions Simulated -system.cpu2.committedOps 31016177 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31016177 # Number of Instructions Simulated -system.cpu2.cpi 1.007380 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.007380 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.992674 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.992674 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42141472 # number of integer regfile reads -system.cpu2.int_regfile_writes 22438304 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67749 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68082 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5235386 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258296 # number of misc regfile writes +system.cpu2.rob.rob_reads 60996891 # The number of ROB reads +system.cpu2.rob.rob_writes 69992925 # The number of ROB writes +system.cpu2.timesIdled 244953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3944260 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746464525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31337447 # Number of Instructions Simulated +system.cpu2.committedOps 31337447 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31337447 # Number of Instructions Simulated +system.cpu2.cpi 0.999083 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.999083 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.000918 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.000918 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42570866 # number of integer regfile reads +system.cpu2.int_regfile_writes 22648106 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67644 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67951 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5345306 # number of misc regfile reads +system.cpu2.misc_regfile_writes 257045 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 5c2619e22..8cfdfc3f7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,132 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.524310 # Number of seconds simulated -sim_ticks 2524309551500 # Number of ticks simulated -final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525141 # Number of seconds simulated +sim_ticks 2525141046500 # Number of ticks simulated +final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55803 # Simulator instruction rate (inst/s) -host_op_rate 71803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2335855340 # Simulator tick rate (ticks/s) -host_mem_usage 401408 # Number of bytes of host memory used -host_seconds 1080.68 # Real time elapsed on the host -sim_insts 60305560 # Number of instructions simulated -sim_ops 77596391 # Number of ops (including micro ops) simulated +host_inst_rate 50522 # Simulator instruction rate (inst/s) +host_op_rate 65007 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2115457252 # Simulator tick rate (ticks/s) +host_mem_usage 427804 # Number of bytes of host memory used +host_seconds 1193.66 # Real time elapsed on the host +sim_insts 60305756 # Number of instructions simulated +sim_ops 77596741 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 966197440 # Total number of bytes read from memory -system.physmem.bytesWritten 52040704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2524308440000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154591 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096843 # Number of read requests accepted +system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue +system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943145 # Per bank write bursts +system.physmem.perBankRdBursts::2 939291 # Per bank write bursts +system.physmem.perBankRdBursts::3 939307 # Per bank write bursts +system.physmem.perBankRdBursts::4 943115 # Per bank write bursts +system.physmem.perBankRdBursts::5 943141 # Per bank write bursts +system.physmem.perBankRdBursts::6 939138 # Per bank write bursts +system.physmem.perBankRdBursts::7 938546 # Per bank write bursts +system.physmem.perBankRdBursts::8 943996 # Per bank write bursts +system.physmem.perBankRdBursts::9 943390 # Per bank write bursts +system.physmem.perBankRdBursts::10 938426 # Per bank write bursts +system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.perBankRdBursts::12 943928 # Per bank write bursts +system.physmem.perBankRdBursts::13 943533 # Per bank write bursts +system.physmem.perBankRdBursts::14 939234 # Per bank write bursts +system.physmem.perBankRdBursts::15 938672 # Per bank write bursts +system.physmem.perBankWrBursts::0 6704 # Per bank write bursts +system.physmem.perBankWrBursts::1 6457 # Per bank write bursts +system.physmem.perBankWrBursts::2 6598 # Per bank write bursts +system.physmem.perBankWrBursts::3 6635 # Per bank write bursts +system.physmem.perBankWrBursts::4 6561 # Per bank write bursts +system.physmem.perBankWrBursts::5 6794 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6723 # Per bank write bursts +system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankWrBursts::9 6877 # Per bank write bursts +system.physmem.perBankWrBursts::10 6538 # Per bank write bursts +system.physmem.perBankWrBursts::11 6183 # Per bank write bursts +system.physmem.perBankWrBursts::12 7149 # Per bank write bursts +system.physmem.perBankWrBursts::13 6765 # Per bank write bursts +system.physmem.perBankWrBursts::14 7038 # Per bank write bursts +system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::3 14942208 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59125 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -140,294 +142,604 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation -system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests -system.physmem.totBusLat 75453215000 # Total cycles spent in databus access -system.physmem.totBankLat 15307050000 # Total cycles spent in bank access -system.physmem.avgQLat 19314.15 # Average queueing delay per request -system.physmem.avgBankLat 1014.34 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25328.49 # Average memory access latency -system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 14.41 # Average write queue length over time -system.physmem.readRowHits 15065383 # Number of row buffer hits during reads -system.physmem.writeRowHits 94229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes -system.physmem.avgGap 158662.04 # Average gap between requests +system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation +system.physmem.totQLat 365610387500 # Total ticks spent queuing +system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks +system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing +system.physmem.readRowHits 14986740 # Number of row buffer hits during reads +system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes +system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -440,50 +752,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.throughput 54899945 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16149440 # Transaction distribution system.membus.trans_dist::ReadResp 16149440 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution +system.membus.trans_dist::ReadExReq 131442 # Transaction distribution +system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138629141 # Total data (bytes) +system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630105 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -491,13 +803,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48301509 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -519,12 +831,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -546,14 +858,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121927961 # Total data (bytes) +system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927965 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -599,41 +911,41 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14390442 # Number of BP lookups -system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits +system.cpu.branchPred.lookups 14384905 # Number of BP lookups +system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986742 # DTB read hits -system.cpu.checker.dtb.read_misses 7308 # DTB read misses -system.cpu.checker.dtb.write_hits 11227334 # DTB write hits -system.cpu.checker.dtb.write_misses 2189 # DTB write misses +system.cpu.checker.dtb.read_hits 14986852 # DTB read hits +system.cpu.checker.dtb.read_misses 7306 # DTB read misses +system.cpu.checker.dtb.write_hits 11227410 # DTB write hits +system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994050 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229523 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994158 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229601 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214076 # DTB hits +system.cpu.checker.dtb.hits 26214262 # DTB hits system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26223573 # DTB accesses -system.cpu.checker.itb.inst_hits 61479547 # ITB inst hits +system.cpu.checker.dtb.accesses 26223759 # DTB accesses +system.cpu.checker.itb.inst_hits 61479743 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -650,36 +962,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484018 # ITB inst accesses -system.cpu.checker.itb.hits 61479547 # DTB hits +system.cpu.checker.itb.inst_accesses 61484214 # ITB inst accesses +system.cpu.checker.itb.hits 61479743 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61484018 # DTB accesses -system.cpu.checker.numCycles 77882185 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484214 # DTB accesses +system.cpu.checker.numCycles 77882535 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51188083 # DTB read hits -system.cpu.dtb.read_misses 64353 # DTB read misses -system.cpu.dtb.write_hits 11697459 # DTB write hits -system.cpu.dtb.write_misses 15788 # DTB write misses +system.cpu.dtb.read_hits 51179212 # DTB read hits +system.cpu.dtb.read_misses 64531 # DTB read misses +system.cpu.dtb.write_hits 11698539 # DTB write hits +system.cpu.dtb.write_misses 15837 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6568 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252436 # DTB read accesses -system.cpu.dtb.write_accesses 11713247 # DTB write accesses +system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51243743 # DTB read accesses +system.cpu.dtb.write_accesses 11714376 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62885542 # DTB hits -system.cpu.dtb.misses 80141 # DTB misses -system.cpu.dtb.accesses 62965683 # DTB accesses -system.cpu.itb.inst_hits 11520428 # ITB inst hits -system.cpu.itb.inst_misses 11439 # ITB inst misses +system.cpu.dtb.hits 62877751 # DTB hits +system.cpu.dtb.misses 80368 # DTB misses +system.cpu.dtb.accesses 62958119 # DTB accesses +system.cpu.itb.inst_hits 11513998 # ITB inst hits +system.cpu.itb.inst_misses 11344 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -688,114 +1000,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4968 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4962 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11531867 # ITB inst accesses -system.cpu.itb.hits 11520428 # DTB hits -system.cpu.itb.misses 11439 # DTB misses -system.cpu.itb.accesses 11531867 # DTB accesses -system.cpu.numCycles 473080437 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11525342 # ITB inst accesses +system.cpu.itb.hits 11513998 # DTB hits +system.cpu.itb.misses 11344 # DTB misses +system.cpu.itb.accesses 11525342 # DTB accesses +system.cpu.numCycles 474882944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -823,13 +1135,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -842,397 +1154,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued -system.cpu.iq.rate 0.259812 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued +system.cpu.iq.rate 0.258795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221034 # number of nop insts executed -system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed -system.cpu.iew.exec_branches 11474602 # Number of branches executed -system.cpu.iew.exec_stores 12209197 # Number of stores executed -system.cpu.iew.exec_rate 0.255417 # Inst execution rate -system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47030253 # num instructions producing a value -system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value +system.cpu.iew.exec_nop 221869 # number of nop insts executed +system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475076 # Number of branches executed +system.cpu.iew.exec_stores 12210518 # Number of stores executed +system.cpu.iew.exec_rate 0.254424 # Inst execution rate +system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47026181 # num instructions producing a value +system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60455941 # Number of instructions committed -system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456137 # Number of instructions committed +system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385481 # Number of memory references committed -system.cpu.commit.loads 15653838 # Number of loads committed -system.cpu.commit.membars 403568 # Number of memory barriers committed -system.cpu.commit.branches 9961054 # Number of branches committed +system.cpu.commit.refs 27385736 # Number of memory references committed +system.cpu.commit.loads 15654008 # Number of loads committed +system.cpu.commit.membars 403573 # Number of memory barriers committed +system.cpu.commit.branches 9961077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. -system.cpu.commit.function_calls 991205 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. +system.cpu.commit.function_calls 991208 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239241509 # The number of ROB reads -system.cpu.rob.rob_writes 195965670 # The number of ROB writes -system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305560 # Number of Instructions Simulated -system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated -system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547265504 # number of integer regfile reads -system.cpu.int_regfile_writes 87536110 # number of integer regfile writes -system.cpu.fp_regfile_reads 8349 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads -system.cpu.misc_regfile_writes 831835 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.rob.rob_reads 240636318 # The number of ROB reads +system.cpu.rob.rob_writes 195934369 # The number of ROB writes +system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305756 # Number of Instructions Simulated +system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated +system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547208472 # number of integer regfile reads +system.cpu.int_regfile_writes 87526189 # number of integer regfile writes +system.cpu.fp_regfile_reads 8624 # number of floating regfile reads +system.cpu.fp_regfile_writes 3008 # number of floating regfile writes +system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.misc_regfile_writes 831837 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 979660 # number of replacements -system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits -system.cpu.icache.overall_hits::total 10456897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses -system.cpu.icache.overall_misses::total 1059959 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980741 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits +system.cpu.icache.overall_hits::total 10449649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses +system.cpu.icache.overall_misses::total 1060761 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64363 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64371 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses -system.cpu.l2cache.overall_misses::total 156307 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits +system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses +system.cpu.l2cache.overall_misses::total 156313 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1241,109 +1553,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks -system.cpu.l2cache.writebacks::total 59118 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks +system.cpu.l2cache.writebacks::total 59125 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1353,161 +1665,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643614 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits -system.cpu.dcache.overall_hits::total 21018772 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses -system.cpu.dcache.overall_misses::total 3700946 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits +system.cpu.dcache.overall_hits::total 21010251 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses +system.cpu.dcache.overall_misses::total 3701471 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks -system.cpu.dcache.writebacks::total 607864 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks +system.cpu.dcache.writebacks::total 607699 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1529,10 +1841,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 99b249a14..22f0dd0ff 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,154 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.104038 # Number of seconds simulated -sim_ticks 1104038330000 # Number of ticks simulated -final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.104766 # Number of seconds simulated +sim_ticks 1104765949000 # Number of ticks simulated +final_tick 1104765949000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65967 # Simulator instruction rate (inst/s) -host_op_rate 84921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1182267512 # Simulator tick rate (ticks/s) -host_mem_usage 404512 # Number of bytes of host memory used -host_seconds 933.83 # Real time elapsed on the host -sim_insts 61602211 # Number of instructions simulated -sim_ops 79302243 # Number of ops (including micro ops) simulated +host_inst_rate 62642 # Simulator instruction rate (inst/s) +host_op_rate 80640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1123477436 # Simulator tick rate (ticks/s) +host_mem_usage 430892 # Number of bytes of host memory used +host_seconds 983.35 # Real time elapsed on the host +sim_insts 61598253 # Number of instructions simulated +sim_ops 79296895 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 410368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory -system.physmem.bytes_read::total 59194084 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 410368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 816192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 408192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366132 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 406848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5251248 # Number of bytes read from this memory +system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4268480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7294544 # Number of bytes written to this memory +system.physmem.bytes_written::total 7295824 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257998 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66675 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82077 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66695 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823511 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44164032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 696 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823531 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44134945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3955272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4755646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371697 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3865083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2726666 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6607147 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3865083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44164032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 369483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4753267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53579613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 369483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 737749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3863696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6603954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3863696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44134945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3970670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7482313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60223116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257998 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 823511 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 6257998 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 823511 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 400511872 # Total number of bytes read from memory -system.physmem.bytesWritten 52704704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59194084 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7294544 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4191 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 12574 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391051 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 391031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 390511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391821 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 391470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 391242 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 390250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 391418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 389084 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 390982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 391146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 389937 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7320 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7419 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7389 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7529 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6626 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7205 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1104037196000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 6094848 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163045 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66675 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 510579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 438231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 410611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1497375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1129368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1114937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1085131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.bw_total::cpu0.inst 369483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3967476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 368266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7478138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60183567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257980 # Number of read requests accepted +system.physmem.writeReqs 823531 # Number of write requests accepted +system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823531 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 398200448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2310272 # Total number of bytes read from write queue +system.physmem.bytesWritten 7402624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7295824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36098 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707850 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12605 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 391110 # Per bank write bursts +system.physmem.perBankRdBursts::1 390863 # Per bank write bursts +system.physmem.perBankRdBursts::2 386866 # Per bank write bursts +system.physmem.perBankRdBursts::3 386878 # Per bank write bursts +system.physmem.perBankRdBursts::4 391778 # Per bank write bursts +system.physmem.perBankRdBursts::5 391417 # Per bank write bursts +system.physmem.perBankRdBursts::6 386925 # Per bank write bursts +system.physmem.perBankRdBursts::7 386783 # Per bank write bursts +system.physmem.perBankRdBursts::8 391442 # Per bank write bursts +system.physmem.perBankRdBursts::9 391216 # Per bank write bursts +system.physmem.perBankRdBursts::10 386574 # Per bank write bursts +system.physmem.perBankRdBursts::11 385570 # Per bank write bursts +system.physmem.perBankRdBursts::12 390981 # Per bank write bursts +system.physmem.perBankRdBursts::13 390596 # Per bank write bursts +system.physmem.perBankRdBursts::14 386700 # Per bank write bursts +system.physmem.perBankRdBursts::15 386183 # Per bank write bursts +system.physmem.perBankWrBursts::0 7188 # Per bank write bursts +system.physmem.perBankWrBursts::1 7193 # Per bank write bursts +system.physmem.perBankWrBursts::2 7297 # Per bank write bursts +system.physmem.perBankWrBursts::3 7231 # Per bank write bursts +system.physmem.perBankWrBursts::4 7835 # Per bank write bursts +system.physmem.perBankWrBursts::5 7450 # Per bank write bursts +system.physmem.perBankWrBursts::6 7370 # Per bank write bursts +system.physmem.perBankWrBursts::7 7176 # Per bank write bursts +system.physmem.perBankWrBursts::8 7508 # Per bank write bursts +system.physmem.perBankWrBursts::9 7517 # Per bank write bursts +system.physmem.perBankWrBursts::10 6849 # Per bank write bursts +system.physmem.perBankWrBursts::11 6596 # Per bank write bursts +system.physmem.perBankWrBursts::12 7160 # Per bank write bursts +system.physmem.perBankWrBursts::13 6824 # Per bank write bursts +system.physmem.perBankWrBursts::14 7287 # Per bank write bursts +system.physmem.perBankWrBursts::15 7185 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1104764856500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 105 # Read request sizes (log2) +system.physmem.readPktSize::3 6094848 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 163027 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66695 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 548369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 494073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 445478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1468713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1058783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1047686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1043195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 25416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,312 +159,563 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11560.822642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 608.575977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 24356.197009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 8749 24.81% 24.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 4356 12.35% 37.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2652 7.52% 44.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 2010 5.70% 50.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1437 4.08% 54.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1214 3.44% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 927 2.63% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 1120 3.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 659 1.87% 65.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 617 1.75% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 450 1.28% 68.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 454 1.29% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 302 0.86% 70.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 302 0.86% 71.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 179 0.51% 72.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 219 0.62% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 133 0.38% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 156 0.44% 73.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 97 0.28% 73.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 134 0.38% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 73 0.21% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 395 1.12% 75.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 262 0.74% 76.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 538 1.53% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 109 0.31% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 178 0.50% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 51 0.14% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 128 0.36% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 49 0.14% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 68 0.19% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 39 0.11% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 74 0.21% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 17 0.05% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 56 0.16% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 22 0.06% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.09% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 13 0.04% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 29 0.08% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 10 0.03% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 19 0.05% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 9 0.03% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 17 0.05% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 14 0.04% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 6 0.02% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 10 0.03% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 4 0.01% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 17 0.05% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 3 0.01% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 15 0.04% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 7 0.02% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 9 0.03% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 11 0.03% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 3 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 7 0.02% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 3 0.01% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 11 0.03% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 4 0.01% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 5 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 13 0.04% 80.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 3 0.01% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 28 0.08% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 4 0.01% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 7 0.02% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 4 0.01% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 3 0.01% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 1 0.00% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 6 0.02% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 4 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 2 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 6 0.02% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 4 0.01% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 5 0.01% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 3 0.01% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 4 0.01% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5199 4 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 2 0.01% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 5 0.01% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5583 4 0.01% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 3 0.01% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 4 0.01% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5839 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 2 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 2 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6095 1 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 2 0.01% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 3 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 2 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6351 3 0.01% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 3 0.01% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 1 0.00% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6671 2 0.01% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 16 0.05% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 3 0.01% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6927 5 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6991 3 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 1 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 8 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7247 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 1 0.00% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 3 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 5 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7631 2 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 3 0.01% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7759 2 0.01% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 1 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 4 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 6 0.02% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 5 0.01% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 318 0.90% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8399 1 0.00% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.12% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 122 0.35% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 8 0.02% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 3 0.01% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 3 0.01% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 1 0.00% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 2 0.01% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10767 2 0.01% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11023 1 0.00% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11279 2 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11535 2 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12047 2 0.01% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 1 0.00% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12751 1 0.00% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 1 0.00% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 1 0.00% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 2 0.01% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15631 1 0.00% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 2 0.01% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16527 1 0.00% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18895 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19151 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19919 1 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20239 1 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20495 2 0.01% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20943 1 0.00% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21007 2 0.01% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21327 1 0.00% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 2 0.01% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22031 1 0.00% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 3 0.01% 83.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23823 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24143 1 0.00% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 4 0.01% 83.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24847 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25024-25039 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25103 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 1 0.00% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26319 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26703 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27215 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27407 1 0.00% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27983 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28111 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 3 0.01% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29711 1 0.00% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29967 3 0.01% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30415 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31247 2 0.01% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32015 1 0.00% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32271 1 0.00% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32527 1 0.00% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32655 1 0.00% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32911 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33039 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33295 1 0.00% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 9 0.03% 83.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 9 0.03% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33679 3 0.01% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 3 0.01% 83.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 23 0.07% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36879 1 0.00% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37568-37583 1 0.00% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37903 2 0.01% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39247 1 0.00% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39695 1 0.00% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43535 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44239 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44559 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45583 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46400-46415 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46863 1 0.00% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47119 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47311 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47439 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47887 1 0.00% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48143 2 0.01% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48335 2 0.01% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49039 1 0.00% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49600-49615 1 0.00% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49935 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52864-52879 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53519 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54287 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54464-54479 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54784-54799 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60160-60175 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60672-60687 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60928-60943 1 0.00% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 10 0.03% 83.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65423 6 0.02% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 5666 16.07% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::68672-68687 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69120-69135 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::72128-72143 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73088-73103 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 20 0.06% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 91 0.26% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 61 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35262 # Bytes accessed per row activation -system.physmem.totQLat 121597245250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 160506894000 # Sum of mem lat for all requests -system.physmem.totBusLat 31269035000 # Total cycles spent in databus access -system.physmem.totBankLat 7640613750 # Total cycles spent in bank access -system.physmem.avgQLat 19443.72 # Average queueing delay per request -system.physmem.avgBankLat 1221.75 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25665.47 # Average memory access latency -system.physmem.avgRdBW 362.77 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.74 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.62 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 12.74 # Average write queue length over time -system.physmem.readRowHits 6235456 # Number of row buffer hits during reads -system.physmem.writeRowHits 98940 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes -system.physmem.avgGap 155904.23 # Average gap between requests +system.physmem.bytesPerActivate::samples 71125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5702.673097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 368.783347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 12967.835637 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25909 36.43% 36.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14850 20.88% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3162 4.45% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2234 3.14% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1545 2.17% 67.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1302 1.83% 68.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 996 1.40% 70.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1191 1.67% 71.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 629 0.88% 72.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 663 0.93% 73.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 567 0.80% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 536 0.75% 75.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 288 0.40% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 263 0.37% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 175 0.25% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 373 0.52% 76.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 125 0.18% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 132 0.19% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 91 0.13% 77.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 197 0.28% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 57 0.08% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 541 0.76% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 41 0.06% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 225 0.32% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 27 0.04% 78.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 110 0.15% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 22 0.03% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 16 0.02% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 61 0.09% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 267 0.38% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 16 0.02% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 40 0.06% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 17 0.02% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 50 0.07% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 11 0.02% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.03% 79.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 7 0.01% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 43 0.06% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 4 0.01% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 15 0.02% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 8 0.01% 80.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 32 0.04% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 30 0.04% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 157 0.22% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 6 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 17 0.02% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 2 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 36 0.05% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 17 0.02% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 7 0.01% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 8 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 39 0.05% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 6 0.01% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 181 0.25% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 9 0.01% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.02% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 12 0.02% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 102 0.14% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 17 0.02% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 25 0.04% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 7 0.01% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 11 0.02% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 5 0.01% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.03% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 161 0.23% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 9 0.01% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 14 0.02% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 3 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 16 0.02% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 18 0.03% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 5 0.01% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 8 0.01% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 150 0.21% 81.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 2 0.00% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 12 0.02% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 13 0.02% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 95 0.13% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 7 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 23 0.03% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 11 0.02% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 3 0.00% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 112 0.16% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 9 0.01% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 20 0.03% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 8 0.01% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 28 0.04% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 4 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 2 0.00% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 94 0.13% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 6 0.01% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 10 0.01% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 92 0.13% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 3 0.00% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 3 0.00% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 20 0.03% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 4 0.01% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 6 0.01% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 249 0.35% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 31 0.04% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 16 0.02% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 3 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 75 0.11% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 93 0.13% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9415 1 0.00% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 20 0.03% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 102 0.14% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 14 0.02% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 94 0.13% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 94 0.13% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 15 0.02% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10823 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10887 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 6 0.01% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 2 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 147 0.21% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 3 0.00% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11847 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 79 0.11% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 162 0.23% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 20 0.03% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 68 0.10% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 1 0.00% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 148 0.21% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13511 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 19 0.03% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 18 0.03% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 11 0.02% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 228 0.32% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 27 0.04% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 14 0.02% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 73 0.10% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 2 0.00% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 145 0.20% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 10 0.01% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 1 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 20 0.03% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 17 0.02% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 273 0.38% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16455 1 0.00% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 1 0.00% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 21 0.03% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 13 0.02% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 156 0.22% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 2 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 80 0.11% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 1 0.00% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 14 0.02% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 31 0.04% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 2 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 219 0.31% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 6 0.01% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18759 1 0.00% 87.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 15 0.02% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 4 0.01% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 13 0.02% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 1 0.00% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 140 0.20% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 17 0.02% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 2 0.00% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 68 0.10% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 17 0.02% 87.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 157 0.22% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 82 0.12% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 4 0.01% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 14 0.02% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 2 0.00% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 145 0.20% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21696-21703 1 0.00% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 4 0.01% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 1 0.00% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 14 0.02% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 2 0.00% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 92 0.13% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 85 0.12% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 14 0.02% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 102 0.14% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 2 0.00% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23232-23239 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 91 0.13% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23744-23751 4 0.01% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 75 0.11% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23879 2 0.00% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 21 0.03% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 31 0.04% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 139 0.20% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 29 0.04% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 2 0.00% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 18 0.03% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 77 0.11% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 90 0.13% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 104 0.15% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 14 0.02% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 87 0.12% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 2 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 94 0.13% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 2 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27335 1 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 5 0.01% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 143 0.20% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 1 0.00% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 5 0.01% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 82 0.12% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 1 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 157 0.22% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 2 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 22 0.03% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 2 0.00% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 67 0.09% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29383 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 16 0.02% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 3 0.00% 90.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 139 0.20% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 3 0.00% 90.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30023 1 0.00% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 17 0.02% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 4 0.01% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 11 0.02% 90.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 213 0.30% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 2 0.00% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 26 0.04% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 1 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 17 0.02% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 70 0.10% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 147 0.21% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 14 0.02% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 20 0.03% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 14 0.02% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 271 0.38% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 20 0.03% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 20 0.03% 92.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 153 0.22% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 71 0.10% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 15 0.02% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 26 0.04% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34624-34631 2 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 211 0.30% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 7 0.01% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 15 0.02% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 136 0.19% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 19 0.03% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36288-36295 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 67 0.09% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 18 0.03% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 155 0.22% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 79 0.11% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 3 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 12 0.02% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 1 0.00% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 140 0.20% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 3 0.00% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 13 0.02% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 93 0.13% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 85 0.12% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 15 0.02% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39360-39367 2 0.00% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 104 0.15% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 19 0.03% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 90 0.13% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 75 0.11% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 16 0.02% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 2 0.00% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 30 0.04% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40832-40839 1 0.00% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 138 0.19% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 29 0.04% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 18 0.03% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 74 0.10% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41792-41799 2 0.00% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 2 0.00% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 90 0.13% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 19 0.03% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 98 0.14% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 15 0.02% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 82 0.12% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 90 0.13% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43392-43399 1 0.00% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 4 0.01% 95.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 144 0.20% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 2 0.00% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 2 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 5 0.01% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 85 0.12% 95.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 155 0.22% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 16 0.02% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 2 0.00% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 71 0.10% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 2 0.00% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 19 0.03% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 138 0.19% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 14 0.02% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 15 0.02% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 10 0.01% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 214 0.30% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 31 0.04% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 15 0.02% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 70 0.10% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 146 0.21% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 10 0.01% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 20 0.03% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48832-48839 2 0.00% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 13 0.02% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 1979 2.78% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 4 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52352-52359 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52672-52679 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71125 # Bytes accessed per row activation +system.physmem.totQLat 151840872500 # Total ticks spent queuing +system.physmem.totMemAccLat 191562815000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 31109410000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8612532500 # Total ticks spent accessing banks +system.physmem.avgQLat 24404.33 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1384.23 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30788.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.87 # Data bus utilization in percentage +system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.06 # Average write queue length when enqueuing +system.physmem.readRowHits 6168484 # Number of row buffer hits during reads +system.physmem.writeRowHits 97939 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.66 # Row buffer hit rate for writes +system.physmem.avgGap 156006.94 # Average gap between requests +system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 3.92 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -485,300 +734,286 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62410733 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306749 # Transaction distribution -system.membus.trans_dist::ReadResp 7306749 # Transaction distribution +system.membus.throughput 62369736 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306752 # Transaction distribution +system.membus.trans_dist::ReadResp 7306752 # Transaction distribution system.membus.trans_dist::WriteReq 767894 # Transaction distribution system.membus.trans_dist::WriteResp 767894 # Transaction distribution -system.membus.trans_dist::Writeback 66675 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33869 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17715 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12574 # Transaction distribution -system.membus.trans_dist::ReadExReq 138085 # Transaction distribution -system.membus.trans_dist::ReadExResp 137703 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382522 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 66695 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33888 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17695 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12605 # Transaction distribution +system.membus.trans_dist::ReadExReq 138070 # Transaction distribution +system.membus.trans_dist::ReadExResp 137680 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382518 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971187 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366229 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555907 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389789 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555925 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389781 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729844 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20145057 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729972 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20145177 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68903841 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68903841 # Total data (bytes) +system.membus.tot_pkt_size::total 68903961 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68903961 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475612500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487006499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9865000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9880000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 750000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 749500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8618805999 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8612723499 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4854602214 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4837509170 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13760099489 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13760375954 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 72758 # number of replacements -system.l2c.tags.tagsinuse 53808.125296 # Cycle average of tags in use -system.l2c.tags.total_refs 1836602 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137939 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.314596 # Average number of references to valid blocks. +system.l2c.tags.replacements 72740 # number of replacements +system.l2c.tags.tagsinuse 53853.567584 # Cycle average of tags in use +system.l2c.tags.total_refs 1839137 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.334423 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39514.415699 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.446892 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257540 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4002.916228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2827.365052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.413975 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.918976 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3679.171285 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3769.219649 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602942 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000068 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 39512.680536 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.162068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257969 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4009.847433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2829.767621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.955070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3709.355619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3778.541270 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.602916 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043142 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057514 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821047 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21860 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386435 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166509 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30879 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 588366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198248 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1401466 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581263 # number of Writeback hits -system.l2c.Writeback_hits::total 581263 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2078 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 202 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 141 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48314 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58639 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106953 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4237 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386435 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30879 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4932 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 588366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256887 # number of demand (read+write) hits -system.l2c.demand_hits::total 1508419 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21860 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4237 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386435 # number of overall hits -system.l2c.overall_hits::cpu0.data 214823 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30879 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4932 # number of overall hits -system.l2c.overall_hits::cpu1.inst 588366 # number of overall hits -system.l2c.overall_hits::cpu1.data 256887 # number of overall hits -system.l2c.overall_hits::total 1508419 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.061185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056600 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057656 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821740 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22065 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386342 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166614 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30647 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5089 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 590258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198399 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403772 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581386 # number of Writeback hits +system.l2c.Writeback_hits::total 581386 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2084 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48317 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58643 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22065 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386342 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214931 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30647 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5089 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 590258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 257042 # number of demand (read+write) hits +system.l2c.demand_hits::total 1510732 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22065 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386342 # number of overall hits +system.l2c.overall_hits::cpu0.data 214931 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30647 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5089 # number of overall hits +system.l2c.overall_hits::cpu1.inst 590258 # number of overall hits +system.l2c.overall_hits::cpu1.data 257042 # number of overall hits +system.l2c.overall_hits::total 1510732 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6295 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6381 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6308 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6244 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25258 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5140 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3782 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8922 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 633 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 424 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77006 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140298 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 6260 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6384 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6325 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6267 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25263 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5164 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3801 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8965 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 637 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 413 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1050 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63263 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77007 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140270 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6295 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69673 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6308 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83250 # number of demand (read+write) misses -system.l2c.demand_misses::total 165556 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6260 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69647 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6325 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83274 # number of demand (read+write) misses +system.l2c.demand_misses::total 165533 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6295 # number of overall misses -system.l2c.overall_misses::cpu0.data 69673 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6308 # number of overall misses -system.l2c.overall_misses::cpu1.data 83250 # number of overall misses -system.l2c.overall_misses::total 165556 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 956500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 219500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 459403500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 469850249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1252250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 486933250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 475323500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1894027999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8999593 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12092485 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21092078 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 513478 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3097867 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3611345 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4257399342 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5547277314 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9804676656 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 956500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 219500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 459403500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4727249591 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1252250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 486933250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6022600814 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11698704655 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 956500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 219500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 459403500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4727249591 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1252250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 486933250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6022600814 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11698704655 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 21872 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4240 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392730 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172890 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30893 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 4933 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 594674 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204492 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1426724 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 581263 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 581263 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6475 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4525 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11000 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 835 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 565 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1400 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111606 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135645 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247251 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 21872 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4240 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392730 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284496 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30893 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 4933 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 594674 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 340137 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1673975 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 21872 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4240 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392730 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284496 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30893 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 4933 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 594674 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 340137 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1673975 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000708 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016029 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036908 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000203 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030534 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017703 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.793822 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835801 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.811091 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.758084 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750442 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.755000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567102 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567702 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567431 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000708 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016029 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244900 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000203 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010607 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.244754 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098900 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000708 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016029 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244900 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000203 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010607 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.244754 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098900 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 73166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72979.110405 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73632.698480 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77192.969245 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76124.839846 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 74987.251524 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1750.893580 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3197.378371 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2364.052679 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 811.181675 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7306.290094 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3416.598865 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67265.994786 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72036.949251 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69884.650216 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 73166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72979.110405 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 67849.089188 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 77192.969245 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 72343.553321 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70663.127008 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 73166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72979.110405 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 67849.089188 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 77192.969245 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 72343.553321 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70663.127008 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 6260 # number of overall misses +system.l2c.overall_misses::cpu0.data 69647 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6325 # number of overall misses +system.l2c.overall_misses::cpu1.data 83274 # number of overall misses +system.l2c.overall_misses::total 165533 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1016250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 477500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 449841750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 482248247 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 862750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 476239250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 488675250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1899360997 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8963096 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12325976 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21289072 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 488979 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2955872 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3444851 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4446470608 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 6273738055 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10720208663 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1016250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 477500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 449841750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4928718855 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 862750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 476239250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6762413305 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12619569660 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1016250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 477500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 449841750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4928718855 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 862750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 476239250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6762413305 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12619569660 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22078 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4361 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392602 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 172998 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30658 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5089 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 596583 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204666 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1429035 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581386 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581386 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6498 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4551 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11049 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 828 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 550 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1378 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111580 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135650 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247230 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22078 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4361 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392602 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284578 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30658 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5089 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 596583 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 340316 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1676265 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22078 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4361 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392602 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284578 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30658 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5089 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 596583 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 340316 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1676265 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015945 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036902 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010602 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030621 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017678 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.794706 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835201 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.811386 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.769324 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750909 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.761974 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.566974 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.567689 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.567366 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015945 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.244738 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010602 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244696 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098751 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015945 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.244738 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010602 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244696 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098751 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 159166.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71859.704473 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75540.138941 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75294.743083 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77975.945428 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 75183.509362 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1735.688613 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3242.824520 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2374.687340 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 767.627943 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7157.075061 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3280.810476 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70285.484533 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81469.711260 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76425.526934 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 159166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71859.704473 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70767.137924 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75294.743083 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81206.778887 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 76235.975062 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 159166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71859.704473 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70767.137924 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75294.743083 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81206.778887 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 76235.975062 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -787,180 +1022,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66675 # number of writebacks -system.l2c.writebacks::total 66675 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 66695 # number of writebacks +system.l2c.writebacks::total 66695 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 77 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 12 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6291 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6342 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6301 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6217 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25181 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5140 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3782 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8922 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 633 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 424 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63292 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77006 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140298 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 12 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6257 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6345 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6317 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6240 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25186 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5164 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3801 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8965 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 637 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 413 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1050 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63263 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 77007 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140270 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 13 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6291 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69634 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6301 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83223 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165479 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 12 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6257 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69608 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6317 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83247 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165456 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6291 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69634 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6301 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83223 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165479 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 805500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 182000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 379474750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 387080999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 406686000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 393745000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1569124749 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51534074 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 37985753 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89519827 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6330633 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4257919 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10588552 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3457418648 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4568436180 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8025854828 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 805500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 379474750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3844499647 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 406686000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4962181180 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9594979577 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 805500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 182000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 379474750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3844499647 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 406686000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4962181180 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9594979577 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6406999 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399719988 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2451249 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154593049986 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167001628222 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1006386499 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16503554515 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17509941014 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6406999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13406106487 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2451249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171096604501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184511569236 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036682 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030402 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017650 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793822 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835801 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.811091 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758084 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750442 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567102 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567702 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567431 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098854 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098854 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61034.531536 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63333.601415 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62313.837775 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10026.084436 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.826811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.605358 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.261792 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.551561 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54626.471718 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59325.717217 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57205.767923 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 6257 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69608 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6317 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83247 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165456 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 853750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 440500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 370880500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 400730997 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 728750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 396408250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 408765250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1578807997 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51771606 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38348722 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 90120328 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6378635 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4156405 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10535040 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3652529888 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5315357439 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8967887327 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 853750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 440500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 370880500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4053260885 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 728750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 396408250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5724122689 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10546695324 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 853750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 440500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 370880500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4053260885 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 728750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 396408250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5724122689 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10546695324 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6382249 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399939239 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2397749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603749244 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167012468481 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1006407999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16511968075 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17518376074 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6382249 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13406347238 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2397749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171115717319 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184530844555 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036677 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017624 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.794706 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835201 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.811386 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769324 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750909 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.761974 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566974 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567689 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567366 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098705 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098705 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63156.973522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65507.251603 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62685.936512 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.485283 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10089.113917 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.462688 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.555730 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.934625 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10033.371429 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57735.641497 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69024.341151 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63933.038618 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -981,62 +1204,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136659470 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2706207 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2706206 # Transaction distribution +system.toL2Bus.throughput 136691596 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2708551 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2708550 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581263 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33352 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18058 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51410 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258939 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258939 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 786305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13268 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55413 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1190023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801593 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14394 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72130 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8006701 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25142464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34843867 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38062080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47776006 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 19732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 123572 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146072169 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146072169 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4805124 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4892877936 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 581386 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18023 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51405 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258959 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258959 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13547 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1193885 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4802054 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14684 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 71694 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8011498 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25134272 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847315 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38184256 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47797126 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20356 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 122632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146211713 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146211713 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4800508 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4894625900 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1772488367 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1771371395 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1516304011 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514575770 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9043467 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9208452 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33687702 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34011429 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2681029210 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2689519761 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3243394678 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3237226447 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9483701 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9617950 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41522672 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41300207 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46328621 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278159 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278159 # Transaction distribution +system.iobus.throughput 46298101 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution system.iobus.trans_dist::WriteReq 7950 # Transaction distribution system.iobus.trans_dist::WriteResp 7950 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1058,12 +1281,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 14572214 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1085,14 +1308,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389789 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389781 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148573 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148573 # Total data (bytes) +system.iobus.tot_pkt_size::total 51148565 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148565 # Total data (bytes) system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4019000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1138,42 +1361,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374572000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374568000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16699589511 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16664438046 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6002321 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4576737 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295742 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3785758 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2914394 # Number of BTB hits +system.cpu0.branchPred.lookups 6002691 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4577903 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294712 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3771820 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2913648 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.983104 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673290 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28745 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.247801 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672509 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28479 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907919 # DTB read hits -system.cpu0.dtb.read_misses 28331 # DTB read misses -system.cpu0.dtb.write_hits 5140728 # DTB write hits -system.cpu0.dtb.write_misses 5464 # DTB write misses +system.cpu0.dtb.read_hits 8905508 # DTB read hits +system.cpu0.dtb.read_misses 28991 # DTB read misses +system.cpu0.dtb.write_hits 5140500 # DTB write hits +system.cpu0.dtb.write_misses 5723 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1828 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 958 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1824 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 969 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 551 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936250 # DTB read accesses -system.cpu0.dtb.write_accesses 5146192 # DTB write accesses +system.cpu0.dtb.perms_faults 556 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8934499 # DTB read accesses +system.cpu0.dtb.write_accesses 5146223 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14048647 # DTB hits -system.cpu0.dtb.misses 33795 # DTB misses -system.cpu0.dtb.accesses 14082442 # DTB accesses -system.cpu0.itb.inst_hits 4222709 # ITB inst hits -system.cpu0.itb.inst_misses 5005 # ITB inst misses +system.cpu0.dtb.hits 14046008 # DTB hits +system.cpu0.dtb.misses 34714 # DTB misses +system.cpu0.dtb.accesses 14080722 # DTB accesses +system.cpu0.itb.inst_hits 4219281 # ITB inst hits +system.cpu0.itb.inst_misses 5089 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1182,114 +1405,114 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1348 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1343 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1494 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1465 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4227714 # ITB inst accesses -system.cpu0.itb.hits 4222709 # DTB hits -system.cpu0.itb.misses 5005 # DTB misses -system.cpu0.itb.accesses 4227714 # DTB accesses -system.cpu0.numCycles 69175889 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4224370 # ITB inst accesses +system.cpu0.itb.hits 4219281 # DTB hits +system.cpu0.itb.misses 5089 # DTB misses +system.cpu0.itb.accesses 4224370 # DTB accesses +system.cpu0.numCycles 69432037 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11717201 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32026454 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6002321 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3587684 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7519324 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1452827 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60860 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19607589 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5035 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47006 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1325879 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 324 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4221110 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157905 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2000 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41325646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.001484 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381957 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11713503 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32019404 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6002691 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3586157 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516730 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1449804 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61386 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19631994 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46872 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1335943 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4217707 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157539 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41351812 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.000563 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381156 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33813760 81.82% 81.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565868 1.37% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 817164 1.98% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676151 1.64% 86.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772838 1.87% 88.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 560246 1.36% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669817 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351583 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098219 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33842541 81.84% 81.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565579 1.37% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816874 1.98% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676358 1.64% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772843 1.87% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558608 1.35% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669211 1.62% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351371 0.85% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098427 7.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41325646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086769 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.462971 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12221128 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20791110 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6824454 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510238 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 978716 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935346 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64732 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40027040 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212951 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 978716 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12790081 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5972534 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12789547 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6714080 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2080688 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38920228 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 41351812 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086454 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461162 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12216999 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20826551 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6820783 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 510850 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 976629 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935170 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64759 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40012064 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213022 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 976629 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12786291 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5985032 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12800887 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6711570 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2091403 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38907337 # Number of instructions processed by rename system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 436221 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1152507 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161860177 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4025 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370279 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5370420 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7651291 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5689186 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1120456 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1254854 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36835170 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895288 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37251130 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81272 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6287660 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13163035 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256365 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41325646 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901405 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514906 # Number of insts issued each cycle +system.cpu0.rename.IQFullEvents 435425 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1163203 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 107 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39252215 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175728295 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 161804372 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3955 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30935092 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8317122 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411284 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370379 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5367119 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7645996 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5688511 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1121166 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1220161 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36823164 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895382 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37236653 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80347 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6279547 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13158300 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256522 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41351812 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.900484 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.514831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26248472 63.52% 63.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5690851 13.77% 77.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3114453 7.54% 84.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2470786 5.98% 90.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2128163 5.15% 95.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 926108 2.24% 98.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 506651 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185379 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54783 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26282952 63.56% 63.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5688374 13.76% 77.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3116432 7.54% 84.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2466494 5.96% 90.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2112034 5.11% 95.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 939185 2.27% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 506930 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184996 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54415 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41325646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41351812 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27685 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27736 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.04% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available @@ -1317,395 +1540,395 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842164 78.64% 81.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200566 18.73% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842113 78.49% 81.12% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202594 18.88% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22335497 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46969 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22326150 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46947 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9366005 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5449722 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9362954 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5447671 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37251130 # Type of FU issued -system.cpu0.iq.rate 0.538499 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070867 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028747 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117005145 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44025943 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34344840 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8484 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3874 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38265319 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4464 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307168 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37236653 # Type of FU issued +system.cpu0.iq.rate 0.536304 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1072896 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028813 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117004426 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44005967 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34332716 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8422 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4624 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3857 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38252914 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4421 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307648 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372814 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2493 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13018 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537400 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1368398 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2491 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13086 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537466 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192818 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5781 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192854 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5939 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 978716 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4319425 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 103424 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37848942 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83231 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7651291 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5689186 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571145 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39872 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13404 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13018 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150227 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117595 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267822 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36871306 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9223534 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 379824 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 976629 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4337522 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100010 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37836354 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83498 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7645996 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5688511 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571219 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39755 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6621 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13086 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149491 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117486 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266977 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36859042 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9220953 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 377611 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118484 # number of nop insts executed -system.cpu0.iew.exec_refs 14624342 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4855002 # Number of branches executed -system.cpu0.iew.exec_stores 5400808 # Number of stores executed -system.cpu0.iew.exec_rate 0.533008 # Inst execution rate -system.cpu0.iew.wb_sent 36677174 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34348714 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18316479 # num instructions producing a value -system.cpu0.iew.wb_consumers 35213732 # num instructions consuming a value +system.cpu0.iew.exec_nop 117808 # number of nop insts executed +system.cpu0.iew.exec_refs 14621413 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4853789 # Number of branches executed +system.cpu0.iew.exec_stores 5400460 # Number of stores executed +system.cpu0.iew.exec_rate 0.530865 # Inst execution rate +system.cpu0.iew.wb_sent 36664720 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34336573 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18306413 # num instructions producing a value +system.cpu0.iew.wb_consumers 35193198 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496542 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520152 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.494535 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520169 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6093987 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638923 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232030 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40346930 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775643 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740681 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6085996 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638860 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231074 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40375183 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775004 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.739173 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28704762 71.14% 71.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5702920 14.13% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1886389 4.68% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 981050 2.43% 92.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 790069 1.96% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 509429 1.26% 95.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395100 0.98% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 219754 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1157457 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28737053 71.18% 71.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5697190 14.11% 85.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1882101 4.66% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 980199 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 786708 1.95% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 526531 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 398386 0.99% 96.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216969 0.54% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1150046 2.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40346930 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23686340 # Number of instructions committed -system.cpu0.commit.committedOps 31294803 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40375183 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23683551 # Number of instructions committed +system.cpu0.commit.committedOps 31290943 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11430263 # Number of memory references committed -system.cpu0.commit.loads 6278477 # Number of loads committed -system.cpu0.commit.membars 229716 # Number of memory barriers committed -system.cpu0.commit.branches 4246456 # Number of branches committed +system.cpu0.commit.refs 11428643 # Number of memory references committed +system.cpu0.commit.loads 6277598 # Number of loads committed +system.cpu0.commit.membars 229694 # Number of memory barriers committed +system.cpu0.commit.branches 4245889 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27650320 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489514 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1157457 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27646853 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489416 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1150046 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75726854 # The number of ROB reads -system.cpu0.rob.rob_writes 75758265 # The number of ROB writes -system.cpu0.timesIdled 367474 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27850243 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138859041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23605598 # Number of Instructions Simulated -system.cpu0.committedOps 31214061 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23605598 # Number of Instructions Simulated -system.cpu0.cpi 2.930487 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.930487 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341240 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171860544 # number of integer regfile reads -system.cpu0.int_regfile_writes 34096305 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads -system.cpu0.fp_regfile_writes 892 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13010065 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451140 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392795 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.002835 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3796668 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393307 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.653192 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6982777250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.002835 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998052 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3796668 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3796668 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3796668 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3796668 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3796668 # number of overall hits -system.cpu0.icache.overall_hits::total 3796668 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424314 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424314 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424314 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424314 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424314 # number of overall misses -system.cpu0.icache.overall_misses::total 424314 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5901888496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5901888496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5901888496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5901888496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5901888496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5901888496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4220982 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4220982 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4220982 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4220982 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4220982 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4220982 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100525 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100525 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100525 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100525 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100525 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100525 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.247623 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.247623 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13909.247623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13909.247623 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3930 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75750709 # The number of ROB reads +system.cpu0.rob.rob_writes 75732466 # The number of ROB writes +system.cpu0.timesIdled 364061 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28080225 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2140058132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23602809 # Number of Instructions Simulated +system.cpu0.committedOps 31210201 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23602809 # Number of Instructions Simulated +system.cpu0.cpi 2.941685 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.941685 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.339941 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.339941 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171807193 # number of integer regfile reads +system.cpu0.int_regfile_writes 34081987 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3237 # number of floating regfile reads +system.cpu0.fp_regfile_writes 886 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13003191 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451099 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392605 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.965142 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3793600 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 393117 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.650053 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7051834000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.965142 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997979 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997979 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3793600 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3793600 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3793600 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3793600 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3793600 # number of overall hits +system.cpu0.icache.overall_hits::total 3793600 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423979 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423979 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423979 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423979 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423979 # number of overall misses +system.cpu0.icache.overall_misses::total 423979 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5892352014 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5892352014 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5892352014 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5892352014 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5892352014 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5892352014 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4217579 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4217579 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4217579 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4217579 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4217579 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4217579 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100527 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100527 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100527 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100527 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100527 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100527 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13897.744969 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13897.744969 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3802 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 194 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 164 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.257732 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.182927 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30982 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30982 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30982 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30982 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30982 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30982 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393332 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393332 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393332 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393332 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393332 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393332 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4803860873 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4803860873 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4803860873 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4803860873 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4803860873 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4803860873 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8948750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8948750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8948750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8948750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093185 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093185 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093185 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12213.247010 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12213.247010 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12213.247010 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30839 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30839 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30839 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30839 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30839 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30839 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393140 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393140 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393140 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393140 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393140 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393140 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4794002596 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4794002596 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4794002596 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4794002596 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4794002596 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4794002596 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093215 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093215 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093215 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12194.135921 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276222 # number of replacements -system.cpu0.dcache.tags.tagsinuse 460.530312 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9262144 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276734 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.469483 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42960250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 460.530312 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.899473 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.899473 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5781621 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5781621 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159389 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159389 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139147 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139147 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137077 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137077 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8941010 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8941010 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8941010 # number of overall hits -system.cpu0.dcache.overall_hits::total 8941010 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 391790 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 391790 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1584826 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1584826 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7480 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7480 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1976616 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1976616 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1976616 # number of overall misses -system.cpu0.dcache.overall_misses::total 1976616 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5523901183 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5523901183 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77315448541 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77315448541 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88125732 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88125732 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45924629 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 45924629 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 82839349724 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 82839349724 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 82839349724 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 82839349724 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6173411 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6173411 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744215 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4744215 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147889 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147889 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144557 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144557 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10917626 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10917626 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10917626 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10917626 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063464 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334054 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.334054 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059112 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059112 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051744 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051744 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14099.137760 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14099.137760 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48784.818359 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48784.818359 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10080.728895 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10080.728895 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6139.656283 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6139.656283 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41909.682874 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41909.682874 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 11704 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6407 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 613 # number of cycles access was blocked +system.cpu0.dcache.tags.replacements 276287 # number of replacements +system.cpu0.dcache.tags.tagsinuse 459.684046 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9258198 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276799 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.447368 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.684046 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897820 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.897820 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5778274 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5778274 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3158747 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3158747 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139141 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139141 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137092 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137092 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8937021 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8937021 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8937021 # number of overall hits +system.cpu0.dcache.overall_hits::total 8937021 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392090 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392090 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1584925 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1584925 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8730 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8730 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7451 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7451 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977015 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977015 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977015 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977015 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5539255201 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5539255201 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79907349135 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79907349135 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90050735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 90050735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45818635 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45818635 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85446604336 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85446604336 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85446604336 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85446604336 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6170364 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6170364 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743672 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4743672 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147871 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147871 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144543 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144543 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10914036 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10914036 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10914036 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10914036 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063544 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063544 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334114 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334114 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059038 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059038 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051549 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051549 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181144 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181144 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181144 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181144 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14127.509503 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14127.509503 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50417.116983 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50417.116983 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10315.089920 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10315.089920 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6149.326936 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6149.326936 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43220.008111 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43220.008111 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9481 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 10276 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 609 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.092985 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 48.908397 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.568144 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 78.442748 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks -system.cpu0.dcache.writebacks::total 256512 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203095 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203095 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454344 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454344 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 453 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 453 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657439 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657439 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188695 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188695 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130482 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130482 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7480 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7480 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319177 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319177 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319177 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319177 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2406687867 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2406687867 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110325446 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110325446 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66640768 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66640768 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30961371 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30961371 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7517013313 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7517013313 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7517013313 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7517013313 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504611525 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504611525 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131834379 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131834379 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636445904 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636445904 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030566 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030566 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027503 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051744 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051744 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029235 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029235 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.380704 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.380704 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39164.984028 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39164.984028 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.663168 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.663168 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4139.220722 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4139.220722 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256484 # number of writebacks +system.cpu0.dcache.writebacks::total 256484 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203289 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203289 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454440 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454440 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657729 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657729 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657729 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657729 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188801 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188801 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130485 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130485 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7449 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7449 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319286 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319286 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319286 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319286 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2419086873 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2419086873 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5310990170 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5310990170 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68672765 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68672765 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30919365 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30919365 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7730077043 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7730077043 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7730077043 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7730077043 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504888791 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504888791 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131913883 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131913883 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636802674 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636802674 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056029 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056029 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051535 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051535 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029255 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029255 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8288.806880 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.806880 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4150.807491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4150.807491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1713,38 +1936,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8782132 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7168426 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 407819 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5819499 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4955017 # Number of BTB hits +system.cpu1.branchPred.lookups 8781819 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7169373 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 406881 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5765537 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4953289 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.145079 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773793 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42171 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.912015 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772113 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42948 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42691295 # DTB read hits -system.cpu1.dtb.read_misses 36496 # DTB read misses -system.cpu1.dtb.write_hits 6824033 # DTB write hits -system.cpu1.dtb.write_misses 10597 # DTB write misses +system.cpu1.dtb.read_hits 42694682 # DTB read hits +system.cpu1.dtb.read_misses 36199 # DTB read misses +system.cpu1.dtb.write_hits 6825983 # DTB write hits +system.cpu1.dtb.write_misses 10603 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2020 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2612 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2691 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 287 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42727791 # DTB read accesses -system.cpu1.dtb.write_accesses 6834630 # DTB write accesses +system.cpu1.dtb.perms_faults 664 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42730881 # DTB read accesses +system.cpu1.dtb.write_accesses 6836586 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49515328 # DTB hits -system.cpu1.dtb.misses 47093 # DTB misses -system.cpu1.dtb.accesses 49562421 # DTB accesses -system.cpu1.itb.inst_hits 7577708 # ITB inst hits -system.cpu1.itb.inst_misses 5297 # ITB inst misses +system.cpu1.dtb.hits 49520665 # DTB hits +system.cpu1.dtb.misses 46802 # DTB misses +system.cpu1.dtb.accesses 49567467 # DTB accesses +system.cpu1.itb.inst_hits 7578103 # ITB inst hits +system.cpu1.itb.inst_misses 5415 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1753,114 +1976,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1529 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1545 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1496 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583005 # ITB inst accesses -system.cpu1.itb.hits 7577708 # DTB hits -system.cpu1.itb.misses 5297 # DTB misses -system.cpu1.itb.accesses 7583005 # DTB accesses -system.cpu1.numCycles 408491180 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583518 # ITB inst accesses +system.cpu1.itb.hits 7578103 # DTB hits +system.cpu1.itb.misses 5415 # DTB misses +system.cpu1.itb.accesses 7583518 # DTB accesses +system.cpu1.numCycles 409882606 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18854224 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60287918 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8782132 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5728810 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13124144 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3307681 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 62009 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77240238 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42673 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1437796 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7575877 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 546214 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2648 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 113028448 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.652235 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.978835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18878139 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60299044 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8781819 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5725402 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13123323 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3309042 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63154 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78443797 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42366 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1440662 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7576329 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 547353 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2737 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114261108 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.645293 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.969526 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99911588 88.40% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796149 0.70% 89.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 938672 0.83% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1688468 1.49% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1396344 1.24% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570472 0.50% 93.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1929580 1.71% 94.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410359 0.36% 95.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5386816 4.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101145087 88.52% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796077 0.70% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 936773 0.82% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1687391 1.48% 91.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1395150 1.22% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 571856 0.50% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1930284 1.69% 94.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 409373 0.36% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5389117 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 113028448 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021499 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147587 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20182430 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78186513 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11968696 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524734 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2166075 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1104186 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 97997 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69821372 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 325725 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2166075 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21372370 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33233612 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40763249 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11209012 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4284130 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65907040 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18855 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668466 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3042854 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280703259 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6508 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387840 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7873214 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12591353 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7935523 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1036537 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1457992 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60681374 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157953 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87712578 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93570 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13421216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35924412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277156 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 113028448 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.776022 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519284 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114261108 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021425 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147113 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20196476 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 79405562 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11967958 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523276 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2167836 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1103528 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98181 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69822224 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 326370 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2167836 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21386304 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34427825 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40782107 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11206546 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4290490 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65904089 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18821 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 671145 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3046869 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 355 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69217965 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302501585 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 280690851 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6493 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49057579 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20160386 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444741 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387793 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7877859 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12590402 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7938263 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1041211 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1447247 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60694774 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157845 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87723814 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94478 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13427979 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35976172 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277080 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114261108 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.767749 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513486 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83202776 73.61% 73.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8275815 7.32% 80.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4119768 3.64% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3698740 3.27% 87.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10372542 9.18% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1968067 1.74% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1039899 0.92% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 275618 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75223 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84436887 73.90% 73.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8271726 7.24% 81.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4125209 3.61% 84.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3692140 3.23% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10373138 9.08% 97.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1967895 1.72% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1041724 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 276233 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 76156 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 113028448 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114261108 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32070 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32226 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 994 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -1888,395 +2111,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7550021 95.87% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292311 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551636 95.89% 96.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 290793 3.69% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36603154 41.73% 42.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59244 0.07% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36606472 41.73% 42.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59249 0.07% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.16% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43563118 49.67% 91.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171472 8.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43568189 49.67% 91.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7174305 8.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87712578 # Type of FU issued -system.cpu1.iq.rate 0.214723 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7875398 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089786 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 296453915 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75268930 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53141218 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15550 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8086 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6819 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95265602 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8312 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 341261 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87723814 # Type of FU issued +system.cpu1.iq.rate 0.214022 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7875649 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089778 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297709996 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75289267 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53144243 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15477 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8000 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95277128 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8273 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 341654 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2835568 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17004 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1095143 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2834942 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3919 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1098203 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31913350 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 674872 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31919752 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 674526 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2166075 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25455774 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 362563 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61943028 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112233 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12591353 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7935523 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869270 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64753 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6199 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17004 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201423 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154723 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 356146 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85989556 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43061283 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1723022 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2167836 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26657812 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 361941 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61957280 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112544 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12590402 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7938263 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869014 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64925 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17226 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 200285 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154811 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355096 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85998990 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43064757 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1724824 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103701 # number of nop insts executed -system.cpu1.iew.exec_refs 50171461 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6912906 # Number of branches executed -system.cpu1.iew.exec_stores 7110178 # Number of stores executed -system.cpu1.iew.exec_rate 0.210505 # Inst execution rate -system.cpu1.iew.wb_sent 85230378 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53148037 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29710424 # num instructions producing a value -system.cpu1.iew.wb_consumers 52969976 # num instructions consuming a value +system.cpu1.iew.exec_nop 104661 # number of nop insts executed +system.cpu1.iew.exec_refs 50176981 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6911907 # Number of branches executed +system.cpu1.iew.exec_stores 7112224 # Number of stores executed +system.cpu1.iew.exec_rate 0.209814 # Inst execution rate +system.cpu1.iew.wb_sent 85240093 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53151046 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29713379 # num instructions producing a value +system.cpu1.iew.wb_consumers 52980753 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.130108 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560892 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.129674 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560833 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13294883 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880797 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311444 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 110862373 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.434393 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.404754 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13311701 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880765 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310263 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112093272 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.429609 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.397405 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94147475 84.92% 84.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8220753 7.42% 92.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2089215 1.88% 94.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1249683 1.13% 95.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1247924 1.13% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 575753 0.52% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 991767 0.89% 97.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 529898 0.48% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1809905 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95372912 85.08% 85.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8221460 7.33% 92.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2092695 1.87% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254196 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1248841 1.11% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 572620 0.51% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 992421 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531111 0.47% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1807016 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 110862373 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38066252 # Number of instructions committed -system.cpu1.commit.committedOps 48157821 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112093272 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38065083 # Number of instructions committed +system.cpu1.commit.committedOps 48156333 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16596165 # Number of memory references committed -system.cpu1.commit.loads 9755785 # Number of loads committed -system.cpu1.commit.membars 190126 # Number of memory barriers committed -system.cpu1.commit.branches 5967905 # Number of branches committed +system.cpu1.commit.refs 16595520 # Number of memory references committed +system.cpu1.commit.loads 9755460 # Number of loads committed +system.cpu1.commit.membars 190120 # Number of memory barriers committed +system.cpu1.commit.branches 5967695 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42692526 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534650 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1809905 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42691207 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534629 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1807016 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 169461098 # The number of ROB reads -system.cpu1.rob.rob_writes 125154390 # The number of ROB writes -system.cpu1.timesIdled 1414583 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295462732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1798949280 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37996613 # Number of Instructions Simulated -system.cpu1.committedOps 48088182 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37996613 # Number of Instructions Simulated -system.cpu1.cpi 10.750726 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.750726 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093017 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093017 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384900722 # number of integer regfile reads -system.cpu1.int_regfile_writes 55276259 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5045 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18451458 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405460 # number of misc regfile writes -system.cpu1.icache.tags.replacements 594712 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.460982 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6935744 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 595224 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.652326 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74833132000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.460982 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938400 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938400 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6935744 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6935744 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6935744 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6935744 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6935744 # number of overall hits -system.cpu1.icache.overall_hits::total 6935744 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 640085 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 640085 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 640085 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 640085 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 640085 # number of overall misses -system.cpu1.icache.overall_misses::total 640085 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8700934064 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8700934064 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8700934064 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8700934064 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8700934064 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8700934064 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7575829 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7575829 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7575829 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7575829 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7575829 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7575829 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084490 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084490 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084490 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084490 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084490 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084490 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13593.404101 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13593.404101 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13593.404101 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13593.404101 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2623 # number of cycles access was blocked +system.cpu1.rob.rob_reads 170710273 # The number of ROB reads +system.cpu1.rob.rob_writes 125186848 # The number of ROB writes +system.cpu1.timesIdled 1415125 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295621498 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1799013115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37995444 # Number of Instructions Simulated +system.cpu1.committedOps 48086694 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37995444 # Number of Instructions Simulated +system.cpu1.cpi 10.787678 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.787678 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092698 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092698 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384930549 # number of integer regfile reads +system.cpu1.int_regfile_writes 55277579 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5074 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18448778 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405411 # number of misc regfile writes +system.cpu1.icache.tags.replacements 596659 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.521199 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6934084 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 597171 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.611555 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74930526000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.521199 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938518 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938518 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6934084 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6934084 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6934084 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6934084 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6934084 # number of overall hits +system.cpu1.icache.overall_hits::total 6934084 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 642197 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 642197 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 642197 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 642197 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 642197 # number of overall misses +system.cpu1.icache.overall_misses::total 642197 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8716898620 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8716898620 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8716898620 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8716898620 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8716898620 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8716898620 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576281 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7576281 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7576281 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7576281 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7576281 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7576281 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084764 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084764 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084764 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084764 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084764 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084764 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.558612 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.558612 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13573.558612 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13573.558612 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3156 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.333333 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.610526 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44828 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44828 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44828 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44828 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44828 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44828 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595257 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 595257 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 595257 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 595257 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 595257 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 595257 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7103878279 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7103878279 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7103878279 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7103878279 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7103878279 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7103878279 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3410750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3410750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3410750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3410750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078573 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078573 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11934.136481 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11934.136481 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11934.136481 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44987 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44987 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44987 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44987 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44987 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44987 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597210 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597210 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597210 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597210 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597210 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597210 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7115046481 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7115046481 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7115046481 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7115046481 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7115046481 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7115046481 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078826 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078826 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.078826 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11913.810018 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360690 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.926621 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12678192 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 361043 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.115463 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70882645000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.926621 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925638 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.925638 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8311339 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8311339 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138952 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138952 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97545 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97545 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94900 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94900 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12450291 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12450291 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12450291 # number of overall hits -system.cpu1.dcache.overall_hits::total 12450291 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 397118 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 397118 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1557827 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1557827 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13956 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13956 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10582 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10582 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1954945 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1954945 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1954945 # number of overall misses -system.cpu1.dcache.overall_misses::total 1954945 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6022716747 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6022716747 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 76093468282 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 76093468282 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129448993 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129448993 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53146420 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53146420 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 82116185029 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 82116185029 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 82116185029 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 82116185029 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8708457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696779 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5696779 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111501 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111501 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105482 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105482 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14405236 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14405236 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14405236 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14405236 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045601 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045601 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273458 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273458 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125165 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100320 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100320 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15166.063354 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15166.063354 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48845.904123 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 48845.904123 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9275.508240 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9275.508240 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5022.341712 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5022.341712 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 42004.345406 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 42004.345406 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29557 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18184 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3279 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.014029 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 108.238095 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360813 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.792536 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12672687 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 361164 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.088456 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70971728000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.792536 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925376 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.925376 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8306232 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8306232 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138701 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138701 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97355 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97355 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94895 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94895 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12444933 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12444933 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12444933 # number of overall hits +system.cpu1.dcache.overall_hits::total 12444933 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 398716 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 398716 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1557859 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1557859 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13937 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10575 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10575 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1956575 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1956575 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1956575 # number of overall misses +system.cpu1.dcache.overall_misses::total 1956575 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6078170016 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6078170016 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80199088679 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 80199088679 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128606244 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 128606244 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52837907 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 52837907 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 86277258695 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 86277258695 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 86277258695 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 86277258695 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8704948 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8704948 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5696560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111292 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111292 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105470 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105470 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14401508 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14401508 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14401508 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14401508 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045803 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045803 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273474 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273474 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125229 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125229 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100265 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100265 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135859 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135859 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135859 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135859 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.359434 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.359434 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51480.325677 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 51480.325677 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9227.684868 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9227.684868 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 4996.492388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4996.492388 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 44096.065162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 44096.065162 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 31164 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18449 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3306 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.426497 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 111.138554 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324751 # number of writebacks -system.cpu1.dcache.writebacks::total 324751 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168850 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 168850 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396175 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1396175 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565025 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1565025 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565025 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1565025 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161652 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161652 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12509 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12509 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10578 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10578 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389920 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389920 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389920 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389920 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2830993566 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2830993566 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6516328872 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6516328872 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88639506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88639506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31988580 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31988580 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9347322438 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9347322438 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9347322438 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9347322438 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168914513007 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168914513007 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25825904490 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25825904490 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194740417497 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194740417497 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026212 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026212 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028376 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028376 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112187 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112187 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027068 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027068 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12402.060587 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12402.060587 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40310.845965 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40310.845965 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7086.058518 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7086.058518 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.066931 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.066931 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324902 # number of writebacks +system.cpu1.dcache.writebacks::total 324902 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170345 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170345 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396167 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1396167 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1435 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1435 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566512 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566512 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566512 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566512 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228371 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228371 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161692 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161692 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12502 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12502 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10574 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10574 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 390063 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 390063 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 390063 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 390063 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2847018297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2847018297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7247965426 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7247965426 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87929505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87929505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31688093 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31688093 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10094983723 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 10094983723 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10094983723 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 10094983723 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925175261 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925175261 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25838951416 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25838951416 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194764126677 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194764126677 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026235 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028384 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028384 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112335 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112335 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100256 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027085 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027085 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12466.636731 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12466.636731 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44825.751589 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44825.751589 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7033.235082 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7033.235082 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 2996.793361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2996.793361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2298,18 +2521,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 582931892511 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 582931892511 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 582931892511 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 582931892511 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 612781961046 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41731 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41730 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48851 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ab328c798..b60e42a06 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,132 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.524310 # Number of seconds simulated -sim_ticks 2524309551500 # Number of ticks simulated -final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525141 # Number of seconds simulated +sim_ticks 2525141046500 # Number of ticks simulated +final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65403 # Simulator instruction rate (inst/s) -host_op_rate 84155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2737677908 # Simulator tick rate (ticks/s) -host_mem_usage 401408 # Number of bytes of host memory used -host_seconds 922.06 # Real time elapsed on the host -sim_insts 60305560 # Number of instructions simulated -sim_ops 77596391 # Number of ops (including micro ops) simulated +host_inst_rate 61643 # Simulator instruction rate (inst/s) +host_op_rate 79318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581152882 # Simulator tick rate (ticks/s) +host_mem_usage 426780 # Number of bytes of host memory used +host_seconds 978.30 # Real time elapsed on the host +sim_insts 60305756 # Number of instructions simulated +sim_ops 77596741 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 966197440 # Total number of bytes read from memory -system.physmem.bytesWritten 52040704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2524308440000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154591 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096843 # Number of read requests accepted +system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue +system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943145 # Per bank write bursts +system.physmem.perBankRdBursts::2 939291 # Per bank write bursts +system.physmem.perBankRdBursts::3 939307 # Per bank write bursts +system.physmem.perBankRdBursts::4 943115 # Per bank write bursts +system.physmem.perBankRdBursts::5 943141 # Per bank write bursts +system.physmem.perBankRdBursts::6 939138 # Per bank write bursts +system.physmem.perBankRdBursts::7 938546 # Per bank write bursts +system.physmem.perBankRdBursts::8 943996 # Per bank write bursts +system.physmem.perBankRdBursts::9 943390 # Per bank write bursts +system.physmem.perBankRdBursts::10 938426 # Per bank write bursts +system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.perBankRdBursts::12 943928 # Per bank write bursts +system.physmem.perBankRdBursts::13 943533 # Per bank write bursts +system.physmem.perBankRdBursts::14 939234 # Per bank write bursts +system.physmem.perBankRdBursts::15 938672 # Per bank write bursts +system.physmem.perBankWrBursts::0 6704 # Per bank write bursts +system.physmem.perBankWrBursts::1 6457 # Per bank write bursts +system.physmem.perBankWrBursts::2 6598 # Per bank write bursts +system.physmem.perBankWrBursts::3 6635 # Per bank write bursts +system.physmem.perBankWrBursts::4 6561 # Per bank write bursts +system.physmem.perBankWrBursts::5 6794 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6723 # Per bank write bursts +system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankWrBursts::9 6877 # Per bank write bursts +system.physmem.perBankWrBursts::10 6538 # Per bank write bursts +system.physmem.perBankWrBursts::11 6183 # Per bank write bursts +system.physmem.perBankWrBursts::12 7149 # Per bank write bursts +system.physmem.perBankWrBursts::13 6765 # Per bank write bursts +system.physmem.perBankWrBursts::14 7038 # Per bank write bursts +system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::3 14942208 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59125 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -140,294 +142,604 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation -system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests -system.physmem.totBusLat 75453215000 # Total cycles spent in databus access -system.physmem.totBankLat 15307050000 # Total cycles spent in bank access -system.physmem.avgQLat 19314.15 # Average queueing delay per request -system.physmem.avgBankLat 1014.34 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25328.49 # Average memory access latency -system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 14.41 # Average write queue length over time -system.physmem.readRowHits 15065383 # Number of row buffer hits during reads -system.physmem.writeRowHits 94229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes -system.physmem.avgGap 158662.04 # Average gap between requests +system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation +system.physmem.totQLat 365610387500 # Total ticks spent queuing +system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks +system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing +system.physmem.readRowHits 14986740 # Number of row buffer hits during reads +system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes +system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -440,50 +752,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.throughput 54899945 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16149440 # Transaction distribution system.membus.trans_dist::ReadResp 16149440 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution +system.membus.trans_dist::ReadExReq 131442 # Transaction distribution +system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138629141 # Total data (bytes) +system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630105 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -491,13 +803,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48301509 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -519,12 +831,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -546,14 +858,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121927961 # Total data (bytes) +system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927965 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -599,42 +911,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14390442 # Number of BP lookups -system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits +system.cpu.branchPred.lookups 14384905 # Number of BP lookups +system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51188083 # DTB read hits -system.cpu.dtb.read_misses 64353 # DTB read misses -system.cpu.dtb.write_hits 11697459 # DTB write hits -system.cpu.dtb.write_misses 15788 # DTB write misses +system.cpu.dtb.read_hits 51179212 # DTB read hits +system.cpu.dtb.read_misses 64531 # DTB read misses +system.cpu.dtb.write_hits 11698539 # DTB write hits +system.cpu.dtb.write_misses 15837 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252436 # DTB read accesses -system.cpu.dtb.write_accesses 11713247 # DTB write accesses +system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51243743 # DTB read accesses +system.cpu.dtb.write_accesses 11714376 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62885542 # DTB hits -system.cpu.dtb.misses 80141 # DTB misses -system.cpu.dtb.accesses 62965683 # DTB accesses -system.cpu.itb.inst_hits 11520428 # ITB inst hits -system.cpu.itb.inst_misses 11439 # ITB inst misses +system.cpu.dtb.hits 62877751 # DTB hits +system.cpu.dtb.misses 80368 # DTB misses +system.cpu.dtb.accesses 62958119 # DTB accesses +system.cpu.itb.inst_hits 11513998 # ITB inst hits +system.cpu.itb.inst_misses 11344 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -643,114 +955,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11531867 # ITB inst accesses -system.cpu.itb.hits 11520428 # DTB hits -system.cpu.itb.misses 11439 # DTB misses -system.cpu.itb.accesses 11531867 # DTB accesses -system.cpu.numCycles 473080437 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11525342 # ITB inst accesses +system.cpu.itb.hits 11513998 # DTB hits +system.cpu.itb.misses 11344 # DTB misses +system.cpu.itb.accesses 11525342 # DTB accesses +system.cpu.numCycles 474882944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -778,13 +1090,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -797,397 +1109,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued -system.cpu.iq.rate 0.259812 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued +system.cpu.iq.rate 0.258795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221034 # number of nop insts executed -system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed -system.cpu.iew.exec_branches 11474602 # Number of branches executed -system.cpu.iew.exec_stores 12209197 # Number of stores executed -system.cpu.iew.exec_rate 0.255417 # Inst execution rate -system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47030253 # num instructions producing a value -system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value +system.cpu.iew.exec_nop 221869 # number of nop insts executed +system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475076 # Number of branches executed +system.cpu.iew.exec_stores 12210518 # Number of stores executed +system.cpu.iew.exec_rate 0.254424 # Inst execution rate +system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47026181 # num instructions producing a value +system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60455941 # Number of instructions committed -system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456137 # Number of instructions committed +system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385481 # Number of memory references committed -system.cpu.commit.loads 15653838 # Number of loads committed -system.cpu.commit.membars 403568 # Number of memory barriers committed -system.cpu.commit.branches 9961054 # Number of branches committed +system.cpu.commit.refs 27385736 # Number of memory references committed +system.cpu.commit.loads 15654008 # Number of loads committed +system.cpu.commit.membars 403573 # Number of memory barriers committed +system.cpu.commit.branches 9961077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. -system.cpu.commit.function_calls 991205 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. +system.cpu.commit.function_calls 991208 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239241509 # The number of ROB reads -system.cpu.rob.rob_writes 195965670 # The number of ROB writes -system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305560 # Number of Instructions Simulated -system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated -system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547265501 # number of integer regfile reads -system.cpu.int_regfile_writes 87536109 # number of integer regfile writes -system.cpu.fp_regfile_reads 8349 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads -system.cpu.misc_regfile_writes 831835 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.rob.rob_reads 240636318 # The number of ROB reads +system.cpu.rob.rob_writes 195934369 # The number of ROB writes +system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305756 # Number of Instructions Simulated +system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated +system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547208469 # number of integer regfile reads +system.cpu.int_regfile_writes 87526188 # number of integer regfile writes +system.cpu.fp_regfile_reads 8624 # number of floating regfile reads +system.cpu.fp_regfile_writes 3008 # number of floating regfile writes +system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.misc_regfile_writes 831837 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 979660 # number of replacements -system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits -system.cpu.icache.overall_hits::total 10456897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses -system.cpu.icache.overall_misses::total 1059959 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980741 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits +system.cpu.icache.overall_hits::total 10449649 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses +system.cpu.icache.overall_misses::total 1060761 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64363 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64371 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses -system.cpu.l2cache.overall_misses::total 156307 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits +system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses +system.cpu.l2cache.overall_misses::total 156313 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1196,109 +1508,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks -system.cpu.l2cache.writebacks::total 59118 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks +system.cpu.l2cache.writebacks::total 59125 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1308,161 +1620,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643614 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits -system.cpu.dcache.overall_hits::total 21018772 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses -system.cpu.dcache.overall_misses::total 3700946 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits +system.cpu.dcache.overall_hits::total 21010251 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses +system.cpu.dcache.overall_misses::total 3701471 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks -system.cpu.dcache.writebacks::total 607864 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks +system.cpu.dcache.writebacks::total 607699 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1484,10 +1796,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 2afd1181d..506582551 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,182 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403596 # Number of seconds simulated -sim_ticks 2403595690000 # Number of ticks simulated -final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403658 # Number of seconds simulated +sim_ticks 2403657545000 # Number of ticks simulated +final_tick 2403657545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196358 # Simulator instruction rate (inst/s) -host_op_rate 252199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7823307249 # Simulator tick rate (ticks/s) -host_mem_usage 401444 # Number of bytes of host memory used -host_seconds 307.24 # Real time elapsed on the host -sim_insts 60328186 # Number of instructions simulated -sim_ops 77484426 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 183148 # Simulator instruction rate (inst/s) +host_op_rate 235229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7297160965 # Simulator tick rate (ticks/s) +host_mem_usage 427808 # Number of bytes of host memory used +host_seconds 329.40 # Real time elapsed on the host +sim_insts 60328152 # Number of instructions simulated +sim_ops 77483430 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7050896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7048656 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 677568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 675392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1347680 # Number of bytes read from this memory -system.physmem.bytes_read::total 124659728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.data 1353632 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743680 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298324 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759496 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 763936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3744384 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298192 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558320 # Number of bytes written to this memory +system.physmem.bytes_written::total 6760200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10587 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10553 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21065 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58495 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324581 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389548 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812449 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47769711 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.data 21158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58506 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324548 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389580 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812460 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768482 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 212814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2933478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932471 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 560693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77963 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557533 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 563155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557786 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540090 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47769711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648312 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768482 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3473637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1208969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54676094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13479442 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 446461 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 13479442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 446461 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 862684288 # Total number of bytes read from memory -system.physmem.bytesWritten 28573504 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 109828768 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2811124 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 837727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 837365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 837535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 838843 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 839834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 839919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 839832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 840753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 841921 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 844340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 845026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 846543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 848256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 848014 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 846904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 846630 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2603 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2565 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 3057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 3449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2572 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3826 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 3451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2556 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2402560453500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 8 # Categorize read packet sizes -system.physmem.readPktSize::3 13443840 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35594 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 429373 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17088 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 871692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 848345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 868847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3321058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2492431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2492072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2465727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 13341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 347261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1211467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54675779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13467317 # Number of read requests accepted +system.physmem.writeReqs 446508 # Number of write requests accepted +system.physmem.readBursts 13467317 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446508 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 861908288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 2866432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109734624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2812152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 401719 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2372 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837719 # Per bank write bursts +system.physmem.perBankRdBursts::1 837389 # Per bank write bursts +system.physmem.perBankRdBursts::2 837556 # Per bank write bursts +system.physmem.perBankRdBursts::3 837999 # Per bank write bursts +system.physmem.perBankRdBursts::4 838842 # Per bank write bursts +system.physmem.perBankRdBursts::5 838880 # Per bank write bursts +system.physmem.perBankRdBursts::6 838796 # Per bank write bursts +system.physmem.perBankRdBursts::7 839742 # Per bank write bursts +system.physmem.perBankRdBursts::8 840911 # Per bank write bursts +system.physmem.perBankRdBursts::9 843323 # Per bank write bursts +system.physmem.perBankRdBursts::10 844015 # Per bank write bursts +system.physmem.perBankRdBursts::11 845500 # Per bank write bursts +system.physmem.perBankRdBursts::12 847242 # Per bank write bursts +system.physmem.perBankRdBursts::13 846993 # Per bank write bursts +system.physmem.perBankRdBursts::14 845867 # Per bank write bursts +system.physmem.perBankRdBursts::15 846543 # Per bank write bursts +system.physmem.perBankWrBursts::0 2729 # Per bank write bursts +system.physmem.perBankWrBursts::1 2587 # Per bank write bursts +system.physmem.perBankWrBursts::2 2574 # Per bank write bursts +system.physmem.perBankWrBursts::3 3045 # Per bank write bursts +system.physmem.perBankWrBursts::4 3468 # Per bank write bursts +system.physmem.perBankWrBursts::5 3206 # Per bank write bursts +system.physmem.perBankWrBursts::6 2544 # Per bank write bursts +system.physmem.perBankWrBursts::7 2321 # Per bank write bursts +system.physmem.perBankWrBursts::8 2236 # Per bank write bursts +system.physmem.perBankWrBursts::9 2427 # Per bank write bursts +system.physmem.perBankWrBursts::10 2367 # Per bank write bursts +system.physmem.perBankWrBursts::11 2798 # Per bank write bursts +system.physmem.perBankWrBursts::12 3813 # Per bank write bursts +system.physmem.perBankWrBursts::13 3444 # Per bank write bursts +system.physmem.perBankWrBursts::14 2680 # Per bank write bursts +system.physmem.perBankWrBursts::15 2549 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2402622305000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 8 # Read request sizes (log2) +system.physmem.readPktSize::3 13431664 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 35645 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 429406 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 17102 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 965936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 937737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3274872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2367219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2366833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2384991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 47923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 55146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -190,30 +176,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -222,473 +208,633 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22080 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 39201.023188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 6463.207550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31878.388388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 3036 13.75% 13.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 1347 6.10% 19.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 793 3.59% 23.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 589 2.67% 26.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 391 1.77% 27.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 355 1.61% 29.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 279 1.26% 30.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 235 1.06% 31.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 172 0.78% 32.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 146 0.66% 33.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 130 0.59% 33.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 164 0.74% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 77 0.35% 34.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 80 0.36% 35.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 63 0.29% 35.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 74 0.34% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 30 0.14% 36.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 39 0.18% 36.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 22 0.10% 36.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 39 0.18% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 28 0.13% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 83 0.38% 37.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 95 0.43% 37.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 108 0.49% 37.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 17 0.08% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 45 0.20% 38.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 23 0.10% 38.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 32 0.14% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 10 0.05% 38.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 20 0.09% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 6 0.03% 38.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 23 0.10% 38.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 8 0.04% 38.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 15 0.07% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 1 0.00% 38.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 6 0.03% 38.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 4 0.02% 38.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 10 0.05% 38.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 3 0.01% 38.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 2 0.01% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 1 0.00% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 3 0.01% 38.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 5 0.02% 38.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 8 0.04% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 3 0.01% 39.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 3 0.01% 39.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 1 0.00% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 6 0.03% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 2 0.01% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 2 0.01% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 5 0.02% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 6 0.03% 39.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 2 0.01% 39.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 3 0.01% 39.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 1 0.00% 39.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 2 0.01% 39.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 2 0.01% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 2 0.01% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 39.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 1 0.00% 39.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 3 0.01% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 7 0.03% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 3 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 1 0.00% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 2 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 2 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 1 0.00% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 2 0.01% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 1 0.00% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 2 0.01% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 1 0.00% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 1 0.00% 39.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 15 0.07% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 2 0.01% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6991 1 0.00% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 3 0.01% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 2 0.01% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 1 0.00% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7759 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 2 0.01% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 1 0.00% 39.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 3 0.01% 39.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 45 0.20% 39.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 150 0.68% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 12 0.05% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8975 1 0.00% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 1 0.00% 40.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 1 0.00% 40.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12047 2 0.01% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14863 1 0.00% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16335 1 0.00% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 1 0.00% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 1 0.00% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20239 1 0.00% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 1 0.00% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 1 0.00% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25871 1 0.00% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 1 0.00% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 2 0.01% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31247 1 0.00% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33039 1 0.00% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33295 3 0.01% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 1 0.00% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34319 1 0.00% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35855 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37903 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38927 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40207 1 0.00% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40975 1 0.00% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41999 1 0.00% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47887 1 0.00% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53519 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56079 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 1 0.00% 40.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 13109 59.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22080 # Bytes accessed per row activation -system.physmem.totQLat 259652718750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 339530350000 # Sum of mem lat for all requests -system.physmem.totBusLat 67397210000 # Total cycles spent in databus access -system.physmem.totBankLat 12480421250 # Total cycles spent in bank access -system.physmem.avgQLat 19262.87 # Average queueing delay per request -system.physmem.avgBankLat 925.89 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25188.75 # Average memory access latency -system.physmem.avgRdBW 358.91 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 11.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 45.69 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.17 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.90 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 13462207 # Number of row buffer hits during reads -system.physmem.writeRowHits 40077 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes -system.physmem.avgGap 172524.57 # Average gap between requests -system.membus.throughput 55673401 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13817014 # Transaction distribution -system.membus.trans_dist::ReadResp 13817014 # Transaction distribution -system.membus.trans_dist::WriteReq 432240 # Transaction distribution -system.membus.trans_dist::WriteResp 432240 # Transaction distribution -system.membus.trans_dist::Writeback 17088 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2349 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2349 # Transaction distribution -system.membus.trans_dist::ReadExReq 28007 # Transaction distribution -system.membus.trans_dist::ReadExResp 28007 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1688628 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26887680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28576308 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740538 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5089172 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5830178 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107550720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113380898 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816346 # Total data (bytes) +system.physmem.bytesPerActivate::samples 48451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17848.429795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3200.071202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18346.519598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8608 17.77% 17.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4824 9.96% 27.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 1006 2.08% 29.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 654 1.35% 31.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 399 0.82% 31.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 406 0.84% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 283 0.58% 33.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 297 0.61% 34.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 176 0.36% 34.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 170 0.35% 34.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 172 0.35% 35.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 155 0.32% 35.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 77 0.16% 35.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 80 0.17% 35.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 48 0.10% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 416 0.86% 36.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 18 0.04% 36.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 23 0.05% 36.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 23 0.05% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 108 0.22% 37.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 17 0.04% 37.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 165 0.34% 37.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 12 0.02% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 112 0.23% 37.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 15 0.03% 37.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 32 0.07% 37.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 7 0.01% 37.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 140 0.29% 38.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 6 0.01% 38.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 13 0.03% 38.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 455 0.94% 39.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 12 0.02% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 2 0.00% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 72 0.15% 39.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 5 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 6 0.01% 39.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 5 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 10 0.02% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 5 0.01% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 505 1.04% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 5 0.01% 40.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 5 0.01% 40.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 65 0.13% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 5 0.01% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.02% 40.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 15 0.03% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 3 0.01% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 4 0.01% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 6 0.01% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 66 0.14% 40.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 3 0.01% 40.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 327 0.67% 41.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 8 0.02% 41.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 41.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 130 0.27% 41.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 41.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 4 0.01% 41.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.01% 41.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 68 0.14% 41.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.01% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 5 0.01% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 4 0.01% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.01% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 42.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 258 0.53% 42.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 42.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 4 0.01% 42.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 3 0.01% 42.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 88 0.18% 42.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 3 0.01% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 8 0.02% 42.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 92 0.19% 42.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 4 0.01% 43.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 7 0.01% 43.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 43.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 102 0.21% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 2 0.00% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 3 0.01% 43.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 481 0.99% 44.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 2 0.00% 44.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 3 0.01% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 1 0.00% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.01% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 67 0.14% 44.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 5 0.01% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 6 0.01% 44.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 131 0.27% 44.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 1 0.00% 44.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 1 0.00% 44.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 72 0.15% 44.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 13 0.03% 44.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 133 0.27% 45.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 66 0.14% 45.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 64 0.13% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 385 0.79% 46.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 65 0.13% 46.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 128 0.26% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 73 0.15% 46.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 128 0.26% 47.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 64 0.13% 47.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 478 0.99% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 63 0.13% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 89 0.18% 48.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 86 0.18% 48.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 257 0.53% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 1 0.00% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 65 0.13% 49.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 320 0.66% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 64 0.13% 50.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 14 0.03% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 64 0.13% 50.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 499 1.03% 51.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 64 0.13% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 442 0.91% 52.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 66 0.14% 53.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 72 0.15% 53.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 362 0.75% 54.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 2 0.00% 54.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 6 0.01% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 781 1.61% 55.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 7 0.01% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 362 0.75% 56.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 72 0.15% 56.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 64 0.13% 56.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 128 0.26% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 57.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 442 0.91% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 499 1.03% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 64 0.13% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 12 0.02% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 66 0.14% 59.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 320 0.66% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 128 0.26% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 256 0.53% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 85 0.18% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 87 0.18% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 64 0.13% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 478 0.99% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 67 0.14% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 128 0.26% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 71 0.15% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 129 0.27% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 64 0.13% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 384 0.79% 64.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 64 0.13% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 64 0.13% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 129 0.27% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 70 0.14% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 128 0.26% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 1 0.00% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 66 0.14% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 480 0.99% 66.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 64 0.13% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 89 0.18% 66.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 86 0.18% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 1 0.00% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 67.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 127 0.26% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 320 0.66% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 65 0.13% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 13 0.03% 68.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 64 0.13% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 497 1.03% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 64 0.13% 69.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 442 0.91% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 65 0.13% 71.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 72 0.15% 71.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 362 0.75% 72.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 6 0.01% 72.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 778 1.61% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 5 0.01% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 1 0.00% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 2 0.00% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 362 0.75% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 72 0.15% 74.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 66 0.14% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 443 0.91% 75.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 499 1.03% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.13% 77.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 13 0.03% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 321 0.66% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 127 0.26% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 1 0.00% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 257 0.53% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 79.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 86 0.18% 79.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 89 0.18% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 479 0.99% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39495 1 0.00% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 128 0.26% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 71 0.15% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 128 0.26% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 64 0.13% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 64 0.13% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 384 0.79% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 129 0.27% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 71 0.15% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 128 0.26% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 67 0.14% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 477 0.98% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 64 0.13% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 87 0.18% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 84 0.17% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 128 0.26% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 320 0.66% 86.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 65 0.13% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 12 0.02% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 64 0.13% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 498 1.03% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 1 0.00% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 443 0.91% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 66 0.14% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 72 0.15% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 362 0.75% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 2 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 2 0.00% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 1 0.00% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 7 0.01% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4749 9.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48451 # Bytes accessed per row activation +system.physmem.totQLat 326245474250 # Total ticks spent queuing +system.physmem.totMemAccLat 407559786750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67336585000 # Total ticks spent in databus transfers +system.physmem.totBankLat 13977727500 # Total ticks spent accessing banks +system.physmem.avgQLat 24224.98 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1037.90 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30262.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.81 # Data bus utilization in percentage +system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing +system.physmem.readRowHits 13424164 # Number of row buffer hits during reads +system.physmem.writeRowHits 39490 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 88.17 # Row buffer hit rate for writes +system.physmem.avgGap 172678.78 # Average gap between requests +system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.76 # Percentage of time for which DRAM has all the banks in precharge state +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55673060 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13803640 # Transaction distribution +system.membus.trans_dist::ReadResp 13803640 # Transaction distribution +system.membus.trans_dist::WriteReq 432247 # Transaction distribution +system.membus.trans_dist::WriteResp 432247 # Transaction distribution +system.membus.trans_dist::Writeback 17102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2372 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2372 # Transaction distribution +system.membus.trans_dist::ReadExReq 28053 # Transaction distribution +system.membus.trans_dist::ReadExResp 28053 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 734214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1686398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26863328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26863328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28549726 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 738102 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5093464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5832006 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107453312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107453312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113285318 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133818970 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 415555000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 417653000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 219000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14607219000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14595653500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602404901 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1597948868 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30345557250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30334798000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63232 # number of replacements -system.l2c.tags.tagsinuse 50385.545216 # Cycle average of tags in use -system.l2c.tags.total_refs 1748703 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128626 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.595253 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375561795000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36863.517049 # Average occupied blocks per requestor +system.l2c.tags.replacements 63262 # number of replacements +system.l2c.tags.tagsinuse 50391.923695 # Cycle average of tags in use +system.l2c.tags.total_refs 1749292 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128659 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.596344 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375568862000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36846.357046 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5225.910742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3838.689123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 514.601539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 693.553663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.833611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1665.560742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1574.910611 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562493 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5224.016956 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3834.498559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 503.830830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 691.484420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832714 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1696.766805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1584.142905 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562231 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079741 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079712 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058510 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007852 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010583 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768822 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8792 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468268 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177348 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1162 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 128925 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64565 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18612 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4274 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131110 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290694 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597529 # number of Writeback hits -system.l2c.Writeback_hits::total 597529 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010551 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768920 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8708 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3160 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 467622 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176862 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2604 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 130139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64269 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18599 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4205 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 132179 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290754 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597747 # number of Writeback hits +system.l2c.Writeback_hits::total 597747 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61796 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18660 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33186 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113642 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8792 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 468268 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239144 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1162 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 128925 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 83225 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18612 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4274 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 281840 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 164296 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404336 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8792 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3229 # number of overall hits -system.l2c.overall_hits::cpu0.inst 468268 # number of overall hits -system.l2c.overall_hits::cpu0.data 239144 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2569 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1162 # number of overall hits -system.l2c.overall_hits::cpu1.inst 128925 # number of overall hits -system.l2c.overall_hits::cpu1.data 83225 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18612 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4274 # number of overall hits -system.l2c.overall_hits::cpu2.inst 281840 # number of overall hits -system.l2c.overall_hits::cpu2.data 164296 # number of overall hits -system.l2c.overall_hits::total 1404336 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 61947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18483 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33173 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113603 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8708 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3160 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 467622 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 238809 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2604 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1190 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 130139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 82752 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4205 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 281217 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 165352 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404357 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8708 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3160 # number of overall hits +system.l2c.overall_hits::cpu0.inst 467622 # number of overall hits +system.l2c.overall_hits::cpu0.data 238809 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2604 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1190 # number of overall hits +system.l2c.overall_hits::cpu1.inst 130139 # number of overall hits +system.l2c.overall_hits::cpu1.data 82752 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18599 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4205 # number of overall hits +system.l2c.overall_hits::cpu2.inst 281217 # number of overall hits +system.l2c.overall_hits::cpu2.data 165352 # number of overall hits +system.l2c.overall_hits::total 1404357 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7579 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6466 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7593 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6471 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1013 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1126 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1002 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 11 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.inst 2929 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2523 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21648 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1417 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 474 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1014 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 104500 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9736 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 19132 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu2.data 2540 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21672 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1412 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 467 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1028 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2907 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 104452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9703 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 19227 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133382 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7579 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 110966 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7593 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 110923 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1013 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10862 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1002 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10825 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 11 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 2929 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21655 # number of demand (read+write) misses -system.l2c.demand_misses::total 155016 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21767 # number of demand (read+write) misses +system.l2c.demand_misses::total 155054 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7579 # number of overall misses -system.l2c.overall_misses::cpu0.data 110966 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7593 # number of overall misses +system.l2c.overall_misses::cpu0.data 110923 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1013 # number of overall misses -system.l2c.overall_misses::cpu1.data 10862 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1002 # number of overall misses +system.l2c.overall_misses::cpu1.data 10825 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 11 # number of overall misses system.l2c.overall_misses::cpu2.inst 2929 # number of overall misses -system.l2c.overall_misses::cpu2.data 21655 # number of overall misses -system.l2c.overall_misses::total 155016 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 75420750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 83519750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 595250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 229132750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 191859499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 580705499 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu2.data 21767 # number of overall misses +system.l2c.overall_misses::total 155054 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 71455000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 85190000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 823000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 219607750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 196366750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 573517000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 163493 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 257489 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 623287225 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1332698664 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1955985889 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 75420750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 706806975 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 595250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 229132750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1524558163 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2536691388 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 75420750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 706806975 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 595250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 229132750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1524558163 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2536691388 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8793 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3231 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 475847 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 183814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2570 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1162 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 129938 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 65691 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18619 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4275 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 284769 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 133633 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1312342 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597529 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597529 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1431 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 478 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1025 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28396 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 52318 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247010 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8793 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3231 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 475847 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 350110 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2570 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1162 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 129938 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 94087 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18619 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4275 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 284769 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 185951 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1559352 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8793 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3231 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 475847 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 350110 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2570 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1162 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 129938 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 94087 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18619 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4275 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 284769 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 185951 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1559352 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000619 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015927 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.035177 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007796 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017141 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000234 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.010286 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018880 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016496 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990217 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991632 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.989268 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.990116 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.628398 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.342865 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.365687 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539930 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000619 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015927 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.316946 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007796 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.115446 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000234 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.010286 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.116455 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099411 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000619 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015927 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.316946 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007796 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.115446 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000234 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.010286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.116455 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099411 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74452.862784 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74173.845471 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78229.003073 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 76044.193024 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 26824.902947 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 198.303797 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 161.235700 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 88.636489 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64018.819330 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 69658.094501 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 14666.080986 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74452.862784 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 65071.531486 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 78229.003073 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 70402.131748 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 16364.061697 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74452.862784 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 65071.531486 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 78229.003073 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 70402.131748 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 16364.061697 # average overall miss latency +system.l2c.UpgradeReq_miss_latency::cpu2.data 92996 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 186992 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 728546978 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1457919895 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2186466873 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 71455000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 813736978 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 823000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 219607750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1654286645 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2759983873 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 71455000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 813736978 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 823000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 219607750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1654286645 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2759983873 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8709 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3162 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 475215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 183333 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2605 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1190 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 131141 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 65391 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18610 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4205 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 284146 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 134719 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1312426 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597747 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597747 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1426 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 471 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1042 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 166399 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28186 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 52400 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246985 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8709 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3162 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 475215 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 349732 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2605 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1190 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 131141 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 93577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18610 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4205 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 284146 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 187119 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1559411 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8709 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3162 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 475215 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 349732 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2605 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1190 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 131141 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 93577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18610 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4205 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 284146 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 187119 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1559411 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.035296 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007641 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017158 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.010308 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016513 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990182 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991507 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.986564 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989112 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.627720 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.344249 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.366927 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540041 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.317166 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.115680 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.010308 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.116327 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099431 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.317166 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.115680 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.010308 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.116327 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099431 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71312.375250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 75926.916221 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 74977.039945 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 77309.744094 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 26463.501292 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 201.276231 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 90.463035 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 64.324733 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75084.713800 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75826.696573 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 16392.518278 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71312.375250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75172.007206 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 74977.039945 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75999.753985 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 17800.146226 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71312.375250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75172.007206 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 74977.039945 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75999.753985 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 17800.146226 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,8 +843,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58495 # number of writebacks -system.l2c.writebacks::total 58495 # number of writebacks +system.l2c.writebacks::writebacks 58506 # number of writebacks +system.l2c.writebacks::total 58506 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2.data 12 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits @@ -709,134 +855,122 @@ system.l2c.overall_mshr_hits::cpu2.inst 1 # nu system.l2c.overall_mshr_hits::cpu2.data 12 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1013 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1126 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1002 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1122 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 11 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.inst 2928 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2511 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7587 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 474 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1014 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1488 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9736 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 19132 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 28868 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2528 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7592 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 467 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1028 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1495 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9703 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 19227 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 28930 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1013 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10862 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1002 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10825 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 11 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.inst 2928 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 21643 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 36455 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 21755 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 36522 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1013 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10862 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1002 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10825 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 11 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.inst 2928 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 21643 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 36455 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 62622750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 69218750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 506250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 191992000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 159345749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 483837999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4740474 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10141014 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14881488 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 500926275 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1090069836 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1590996111 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 62622750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 570145025 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 506250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 191992000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1249415585 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2074834110 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 62622750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 570145025 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 506250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 191992000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1249415585 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2074834110 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25122070000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26464740500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51586810500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 939177000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8518259500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9457436500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26061247000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34983000000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 61044247000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017141 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018790 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005781 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991632 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.989268 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.507157 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.342865 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365687 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.116870 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.115446 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.116391 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023378 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.115446 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.116391 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023378 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61473.134991 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63459.079650 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63771.978252 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51450.932108 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 56976.261551 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 55112.793093 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52489.875253 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52489.875253 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu2.data 21755 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 36522 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 58877500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 71259000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 687500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 182826500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 164184000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 477897000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4670967 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10281528 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14952495 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606681022 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1218059105 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1824740127 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 58877500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 677940022 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 687500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 182826500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1382243105 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2302637127 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 58877500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 677940022 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 687500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 182826500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1382243105 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2302637127 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25057289000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26363515500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51420804500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935323010 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8517824000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9453147010 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25992612010 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34881339500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60873951510 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017158 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005785 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991507 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986564 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.508676 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366927 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117133 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023420 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023420 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63510.695187 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64946.202532 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62947.444679 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.070664 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001.486381 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.668896 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62525.097599 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 63351.490352 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63074.321708 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -853,52 +987,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58805533 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021031 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021030 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432240 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432240 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 264941 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1503 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1506 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80714 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80714 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830128 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423683 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15492 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51832 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3321135 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26541184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37337186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 63984874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141242678 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 102048 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176255494 # Layer occupancy (ticks) +system.toL2Bus.throughput 58815755 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021426 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021425 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432247 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432247 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1513 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1515 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80586 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80586 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831264 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15497 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52067 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3322064 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26578304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37416070 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21580 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84860 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64100814 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141271334 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 101600 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2179143758 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870489205 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872769954 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1849664390 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1848854181 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10070717 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10116966 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30771737 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30973250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48764104 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13809372 # Transaction distribution -system.iobus.trans_dist::ReadResp 13809372 # Transaction distribution -system.iobus.trans_dist::WriteReq 2797 # Transaction distribution -system.iobus.trans_dist::WriteResp 2797 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11494 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 22 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762849 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13795996 # Transaction distribution +system.iobus.trans_dist::ReadResp 13795996 # Transaction distribution +system.iobus.trans_dist::WriteReq 2775 # Transaction distribution +system.iobus.trans_dist::WriteResp 2775 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11418 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721570 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 719202 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -914,18 +1048,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 736658 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887680 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26887680 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27624338 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6052 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 44 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 734214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26863328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26863328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27597542 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15382 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715532 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -941,18 +1075,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 740538 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108291258 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 738102 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107453312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107453312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108191414 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 8031000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 7974000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1513000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1515000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 128000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -960,7 +1094,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 361287000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 360101000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -992,444 +1126,444 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443840000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13431664000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 733861000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 731439000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36856295750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36823110000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8004008 # DTB read hits -system.cpu0.dtb.read_misses 6222 # DTB read misses -system.cpu0.dtb.write_hits 6595133 # DTB write hits -system.cpu0.dtb.write_misses 2001 # DTB write misses +system.cpu0.dtb.read_hits 7991455 # DTB read hits +system.cpu0.dtb.read_misses 6184 # DTB read misses +system.cpu0.dtb.write_hits 6591541 # DTB write hits +system.cpu0.dtb.write_misses 1989 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5693 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8010230 # DTB read accesses -system.cpu0.dtb.write_accesses 6597134 # DTB write accesses +system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7997639 # DTB read accesses +system.cpu0.dtb.write_accesses 6593530 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14599141 # DTB hits -system.cpu0.dtb.misses 8223 # DTB misses -system.cpu0.dtb.accesses 14607364 # DTB accesses -system.cpu0.itb.inst_hits 32379967 # ITB inst hits -system.cpu0.itb.inst_misses 3492 # ITB inst misses +system.cpu0.dtb.hits 14582996 # DTB hits +system.cpu0.dtb.misses 8173 # DTB misses +system.cpu0.dtb.accesses 14591169 # DTB accesses +system.cpu0.itb.inst_hits 32325256 # ITB inst hits +system.cpu0.itb.inst_misses 3454 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2598 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2571 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32383459 # ITB inst accesses -system.cpu0.itb.hits 32379967 # DTB hits -system.cpu0.itb.misses 3492 # DTB misses -system.cpu0.itb.accesses 32383459 # DTB accesses -system.cpu0.numCycles 113662532 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32328710 # ITB inst accesses +system.cpu0.itb.hits 32325256 # DTB hits +system.cpu0.itb.misses 3454 # DTB misses +system.cpu0.itb.accesses 32328710 # DTB accesses +system.cpu0.numCycles 113673861 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31896171 # Number of instructions committed -system.cpu0.committedOps 42061376 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37196625 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses -system.cpu0.num_func_calls 1200231 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4252287 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37196625 # number of integer instructions -system.cpu0.num_fp_insts 5021 # number of float instructions -system.cpu0.num_int_register_reads 189594254 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39319391 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu0.num_mem_refs 15267333 # number of memory refs -system.cpu0.num_load_insts 8373046 # Number of load instructions -system.cpu0.num_store_insts 6894287 # Number of store instructions -system.cpu0.num_idle_cycles 110849279.389256 # Number of idle cycles -system.cpu0.num_busy_cycles 2813252.610744 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024751 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975249 # Percentage of idle cycles +system.cpu0.committedInsts 31847112 # Number of instructions committed +system.cpu0.committedOps 42008964 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37152656 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses +system.cpu0.num_func_calls 1198427 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4245737 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37152656 # number of integer instructions +system.cpu0.num_fp_insts 5018 # number of float instructions +system.cpu0.num_int_register_reads 189368889 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39264582 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written +system.cpu0.num_mem_refs 15250074 # number of memory refs +system.cpu0.num_load_insts 8359762 # Number of load instructions +system.cpu0.num_store_insts 6890312 # Number of store instructions +system.cpu0.num_idle_cycles 110868175.114613 # Number of idle cycles +system.cpu0.num_busy_cycles 2805685.885387 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024682 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975318 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891479 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.603901 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43691974 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891991 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.982528 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8175687500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.614782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.336202 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.652916 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964091 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014329 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020806 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31906072 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8054900 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3731002 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43691974 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31906072 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8054900 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3731002 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43691974 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31906072 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8054900 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3731002 # number of overall hits -system.cpu0.icache.overall_hits::total 43691974 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476577 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 130192 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 309459 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916228 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476577 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 130192 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 309459 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916228 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 476577 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 130192 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 309459 # number of overall misses -system.cpu0.icache.overall_misses::total 916228 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1761830250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4180298881 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5942129131 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1761830250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4180298881 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5942129131 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1761830250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4180298881 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5942129131 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32382649 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8185092 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4040461 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44608202 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32382649 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8185092 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4040461 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44608202 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32382649 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8185092 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4040461 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44608202 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014717 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015906 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076590 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020539 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014717 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015906 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076590 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020539 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014717 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015906 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076590 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020539 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13532.553844 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.409453 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6485.426260 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6485.426260 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6485.426260 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4261 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 891412 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602619 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43641790 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891924 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.929942 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8178595250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 492.265032 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.623785 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 11.713802 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.961455 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014890 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.022879 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31851952 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8051251 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3738587 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43641790 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31851952 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8051251 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3738587 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43641790 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31851952 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8051251 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3738587 # number of overall hits +system.cpu0.icache.overall_hits::total 43641790 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 475959 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 131403 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 308483 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915845 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 475959 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 131403 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 308483 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915845 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 475959 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 131403 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 308483 # number of overall misses +system.cpu0.icache.overall_misses::total 915845 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1773590500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4162650116 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5936240616 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1773590500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4162650116 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5936240616 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1773590500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4162650116 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5936240616 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32327911 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8182654 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4047070 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44557635 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32327911 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8182654 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4047070 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44557635 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32327911 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8182654 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4047070 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44557635 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014723 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016059 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076224 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020554 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014723 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016059 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076224 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020554 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014723 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016059 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076224 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020554 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13497.336438 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13493.936833 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6481.708822 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13497.336438 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13493.936833 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6481.708822 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13497.336438 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13493.936833 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6481.708822 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3646 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 235 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.131915 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.128631 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24229 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 24229 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 24229 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 24229 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 24229 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 24229 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 130192 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 285230 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 415422 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 130192 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 285230 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 415422 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 130192 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 285230 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 415422 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1500951750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3402203278 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4903155028 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1500951750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3402203278 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4903155028 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1500951750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3402203278 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4903155028 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009313 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009313 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009313 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11802.829479 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11802.829479 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11802.829479 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23908 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23908 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23908 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23908 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23908 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23908 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 131403 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 284575 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 415978 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 131403 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 284575 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 415978 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 131403 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 284575 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 415978 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1510394500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3385597029 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4895991529 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1510394500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3385597029 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4895991529 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1510394500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3385597029 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4895991529 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009336 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009336 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009336 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11769.832849 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11769.832849 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11769.832849 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629636 # number of replacements +system.cpu0.dcache.tags.replacements 629916 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997119 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23222123 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630148 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.851855 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23219265 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630428 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.830955 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.117005 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.034615 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.845498 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970932 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015693 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013370 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.028749 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.124022 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.844348 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970759 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015867 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013368 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6875315 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1820667 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4627275 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13323257 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5963983 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1316466 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2129753 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9410202 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131811 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33157 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73317 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238285 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138270 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34889 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74229 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247388 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12839298 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3137133 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6757028 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22733459 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12839298 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3137133 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6757028 # number of overall hits -system.cpu0.dcache.overall_hits::total 22733459 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 177356 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 63959 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 269175 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 510490 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167727 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 28874 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 609519 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 806120 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6458 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1732 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3768 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11958 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 345083 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92833 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 878694 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1316610 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 345083 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92833 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 878694 # number of overall misses -system.cpu0.dcache.overall_misses::total 1316610 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 908429000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3875625037 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4784054037 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 912156249 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22615267762 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 23527424011 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22739750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50485499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 73225249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1820585249 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 26490892799 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28311478048 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1820585249 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 26490892799 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28311478048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7052671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1884626 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4896450 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13833747 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6131710 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1345340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2739272 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216322 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138269 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34889 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77085 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250243 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138270 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34889 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74232 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits::cpu0.data 6862135 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1819979 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4638838 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13320952 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5960420 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1315170 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2133916 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9409506 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131682 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33066 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73671 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238419 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138143 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34804 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74442 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247389 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12822555 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3135149 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6772754 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22730458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12822555 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3135149 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6772754 # number of overall hits +system.cpu0.dcache.overall_hits::total 22730458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 176872 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 63653 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 271744 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 512269 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167825 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 28657 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 610336 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 806818 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6461 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1738 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3756 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11955 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 344697 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 92310 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 882080 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1319087 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 344697 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 92310 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 882080 # number of overall misses +system.cpu0.dcache.overall_misses::total 1319087 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905796750 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3920290585 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4826087335 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1012897489 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23468295787 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24481193276 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22815750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50223749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 73039499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1918694239 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27388586372 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 29307280611 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1918694239 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27388586372 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 29307280611 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7039007 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1883632 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4910582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13833221 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6128245 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1343827 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2744252 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216324 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138143 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34804 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77427 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250374 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34804 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74444 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247391 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13184381 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3229966 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7635722 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24050069 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13184381 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3229966 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7635722 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24050069 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025147 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033937 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.054974 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036902 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027354 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021462 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222511 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078905 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046706 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049643 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048881 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047786 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026174 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028741 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115077 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054745 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026174 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028741 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115077 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054745 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14203.302115 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14398.161185 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9371.494127 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31590.920863 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37103.466442 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29186.007060 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13129.185912 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13398.486996 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6123.536461 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 13167252 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3227459 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7654834 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24049545 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13167252 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3227459 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7654834 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24049545 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033793 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055338 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037032 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027385 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021325 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222405 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078973 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046770 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049937 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048510 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047749 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026178 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028601 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115232 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054849 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026178 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028601 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115232 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054849 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14230.228740 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14426.410832 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9421.002120 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35345.552186 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38451.436237 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30342.894279 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.589183 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13371.605165 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6109.535675 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19611.401646 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30148.029688 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21503.313850 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19611.401646 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30148.029688 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21503.313850 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7835 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2458 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 871 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 50 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.995408 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 49.160000 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20785.334622 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31050.002689 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22217.852659 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20785.334622 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31050.002689 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22217.852659 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8471 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 892 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.496637 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 52.367347 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597529 # number of writebacks -system.cpu0.dcache.writebacks::total 597529 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 138849 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 138849 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556206 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 556206 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 431 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 431 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 695055 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 695055 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 695055 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 695055 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63959 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 130326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 194285 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28874 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53313 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82187 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1732 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3337 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5069 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 92833 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 183639 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 276472 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 92833 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 183639 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 276472 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779964000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1680980850 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460944850 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 849834751 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1771488501 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2621323252 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19274250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38952001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58226251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1629798751 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3452469351 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5082268102 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1629798751 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3452469351 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5082268102 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27446152500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893354250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56339506750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1446442000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341405748 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14787847748 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28892594500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42234759998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71127354498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033937 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026616 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014044 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008045 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043290 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011496 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011496 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12194.749762 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12898.277013 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12666.674473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29432.525836 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33228.077598 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31894.621436 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11128.319861 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11672.760264 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11486.733281 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597747 # number of writebacks +system.cpu0.dcache.writebacks::total 597747 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 140335 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 140335 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556925 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 556925 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 697260 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 697260 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 697260 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 697260 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63653 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131409 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 195062 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28657 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53411 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82068 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1738 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3341 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92310 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184820 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 277130 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92310 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184820 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 277130 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 778293250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1698666084 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2476959334 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 952956511 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1898218478 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2851174989 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19339250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38699751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58039001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1731249761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3596884562 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5328134323 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1731249761 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3596884562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5328134323 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27375287500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28782575500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56157863000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442314990 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341314242 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14783629232 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817602490 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42123889742 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70941492232 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033793 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026760 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014101 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019463 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043150 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011523 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011523 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12227.125980 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12926.558181 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12698.318145 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33253.882507 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35539.841568 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34741.616574 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.301496 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11583.283747 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11427.249655 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1442,388 +1576,388 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2098287 # DTB read hits -system.cpu1.dtb.read_misses 2070 # DTB read misses -system.cpu1.dtb.write_hits 1420937 # DTB write hits -system.cpu1.dtb.write_misses 371 # DTB write misses +system.cpu1.dtb.read_hits 2096740 # DTB read hits +system.cpu1.dtb.read_misses 2075 # DTB read misses +system.cpu1.dtb.write_hits 1419315 # DTB write hits +system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1726 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1735 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2100357 # DTB read accesses -system.cpu1.dtb.write_accesses 1421308 # DTB write accesses +system.cpu1.dtb.read_accesses 2098815 # DTB read accesses +system.cpu1.dtb.write_accesses 1419688 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3519224 # DTB hits -system.cpu1.dtb.misses 2441 # DTB misses -system.cpu1.dtb.accesses 3521665 # DTB accesses -system.cpu1.itb.inst_hits 8185092 # ITB inst hits -system.cpu1.itb.inst_misses 1172 # ITB inst misses +system.cpu1.dtb.hits 3516055 # DTB hits +system.cpu1.dtb.misses 2448 # DTB misses +system.cpu1.dtb.accesses 3518503 # DTB accesses +system.cpu1.itb.inst_hits 8182654 # ITB inst hits +system.cpu1.itb.inst_misses 1200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 888 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8186264 # ITB inst accesses -system.cpu1.itb.hits 8185092 # DTB hits -system.cpu1.itb.misses 1172 # DTB misses -system.cpu1.itb.accesses 8186264 # DTB accesses -system.cpu1.numCycles 580203625 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8183854 # ITB inst accesses +system.cpu1.itb.hits 8182654 # DTB hits +system.cpu1.itb.misses 1200 # DTB misses +system.cpu1.itb.accesses 8183854 # DTB accesses +system.cpu1.numCycles 581318737 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7980801 # Number of instructions committed -system.cpu1.committedOps 10142634 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9072894 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses -system.cpu1.num_func_calls 304668 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1116676 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9072894 # number of integer instructions -system.cpu1.num_fp_insts 2143 # number of float instructions -system.cpu1.num_int_register_reads 52281658 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9864872 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3686646 # number of memory refs -system.cpu1.num_load_insts 2191239 # Number of load instructions -system.cpu1.num_store_insts 1495407 # Number of store instructions -system.cpu1.num_idle_cycles 544226668.771142 # Number of idle cycles -system.cpu1.num_busy_cycles 35976956.228858 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062007 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937993 # Percentage of idle cycles +system.cpu1.committedInsts 7974693 # Number of instructions committed +system.cpu1.committedOps 10126531 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9058549 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1938 # Number of float alu accesses +system.cpu1.num_func_calls 304877 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114107 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9058549 # number of integer instructions +system.cpu1.num_fp_insts 1938 # number of float instructions +system.cpu1.num_int_register_reads 52214198 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9844324 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1424 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_mem_refs 3684398 # number of memory refs +system.cpu1.num_load_insts 2190368 # Number of load instructions +system.cpu1.num_store_insts 1494030 # Number of store instructions +system.cpu1.num_idle_cycles 546218260.044225 # Number of idle cycles +system.cpu1.num_busy_cycles 35100476.955774 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060381 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939619 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4715473 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3836739 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223495 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3141743 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527502 # Number of BTB hits +system.cpu2.branchPred.lookups 4723221 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3843292 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222521 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3120017 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2528037 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.449037 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411571 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21589 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 81.026385 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412365 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21211 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10976033 # DTB read hits -system.cpu2.dtb.read_misses 22752 # DTB read misses -system.cpu2.dtb.write_hits 3346841 # DTB write hits -system.cpu2.dtb.write_misses 6453 # DTB write misses +system.cpu2.dtb.read_hits 10969613 # DTB read hits +system.cpu2.dtb.read_misses 23045 # DTB read misses +system.cpu2.dtb.write_hits 3352330 # DTB write hits +system.cpu2.dtb.write_misses 6440 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2303 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 173 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2328 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 460 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10998785 # DTB read accesses -system.cpu2.dtb.write_accesses 3353294 # DTB write accesses +system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10992658 # DTB read accesses +system.cpu2.dtb.write_accesses 3358770 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14322874 # DTB hits -system.cpu2.dtb.misses 29205 # DTB misses -system.cpu2.dtb.accesses 14352079 # DTB accesses -system.cpu2.itb.inst_hits 4041881 # ITB inst hits -system.cpu2.itb.inst_misses 4586 # ITB inst misses +system.cpu2.dtb.hits 14321943 # DTB hits +system.cpu2.dtb.misses 29485 # DTB misses +system.cpu2.dtb.accesses 14351428 # DTB accesses +system.cpu2.itb.inst_hits 4048520 # ITB inst hits +system.cpu2.itb.inst_misses 4581 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1634 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1671 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1002 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1028 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4046467 # ITB inst accesses -system.cpu2.itb.hits 4041881 # DTB hits -system.cpu2.itb.misses 4586 # DTB misses -system.cpu2.itb.accesses 4046467 # DTB accesses -system.cpu2.numCycles 88343562 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4053101 # ITB inst accesses +system.cpu2.itb.hits 4048520 # DTB hits +system.cpu2.itb.misses 4581 # DTB misses +system.cpu2.itb.accesses 4053101 # DTB accesses +system.cpu2.numCycles 88363580 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9345666 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32463757 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4715473 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2939073 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6849430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1758819 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50954 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18707448 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 820 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32452 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 720275 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 489 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4040467 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 290046 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2014 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36916106 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.056921 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.443441 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9342746 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32497136 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4723221 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2940402 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6855397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1756636 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50446 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18848050 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 925 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 34178 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721824 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4047074 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289511 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37061318 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.053700 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.440521 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30071749 81.46% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 384570 1.04% 82.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 513519 1.39% 83.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 818109 2.22% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 634612 1.72% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341178 0.92% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1041484 2.82% 91.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 228835 0.62% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2882050 7.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30210914 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385385 1.04% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 515477 1.39% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 820134 2.21% 86.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 628486 1.70% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 342820 0.93% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1044433 2.82% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229207 0.62% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2884462 7.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36916106 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053377 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367472 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9928442 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19318553 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6233841 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 278394 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1155918 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 607967 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53425 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36920328 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 180410 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1155918 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10478416 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6754031 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11105712 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5942637 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1478447 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34829842 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2448 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 324847 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 890462 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148242103 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3218 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208068 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3242623 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6608021 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3899448 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530191 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 761841 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32138723 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 510591 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34782251 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 56051 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7186073 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19057300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 153940 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36916106 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.942197 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.600639 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37061318 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053452 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367766 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9926500 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19460558 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6238388 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 279816 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1155131 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608208 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53066 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36958585 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178391 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1155131 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10476553 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6920166 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11076723 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5947862 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1483966 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34870863 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2458 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 328650 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 889849 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 96 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37358262 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159586833 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148423376 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3369 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26507725 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10850536 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232822 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 209087 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3256835 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6623705 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3904787 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530493 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 775113 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32195808 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505146 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34809127 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54913 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7172484 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19086467 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 147942 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37061318 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.939231 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.598560 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24329752 65.91% 65.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3820331 10.35% 76.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2317804 6.28% 82.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2003808 5.43% 87.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2797781 7.58% 95.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 970796 2.63% 98.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496090 1.34% 99.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144708 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35036 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24455957 65.99% 65.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3833682 10.34% 76.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2322342 6.27% 82.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2005181 5.41% 88.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2795966 7.54% 95.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 971107 2.62% 98.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 498292 1.34% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144261 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34530 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36916106 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37061318 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19314 1.26% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407095 91.52% 92.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 111138 7.23% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19660 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1402550 91.51% 92.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110445 7.21% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61377 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19718575 56.69% 56.87% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 27760 0.08% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 9 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 371 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11459171 32.95% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3514969 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61175 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19747110 56.73% 56.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 27980 0.08% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11452276 32.90% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3520179 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34782251 # Type of FU issued -system.cpu2.iq.rate 0.393716 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537548 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044205 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108096303 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39840742 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28020326 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6981 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3693 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36254698 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3724 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 204617 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34809127 # Type of FU issued +system.cpu2.iq.rate 0.393931 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1532656 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044030 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108288948 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39878610 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28070823 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7546 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3965 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3367 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36276582 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4026 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205280 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1527306 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1908 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9375 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562929 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1528845 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1875 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9489 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562920 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5348773 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344308 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5328051 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344229 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1155918 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5077664 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88593 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32732277 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60627 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6608021 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3899448 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368370 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29616 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2740 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9375 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107393 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89251 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196644 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33865771 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11188559 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 916480 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1155131 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5244365 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 89322 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32783919 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60352 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6623705 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3904787 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362611 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 30261 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2481 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9489 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 106879 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89021 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195900 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33894861 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11182187 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 914266 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82963 # number of nop insts executed -system.cpu2.iew.exec_refs 14669578 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3700003 # Number of branches executed -system.cpu2.iew.exec_stores 3481019 # Number of stores executed -system.cpu2.iew.exec_rate 0.383342 # Inst execution rate -system.cpu2.iew.wb_sent 33465265 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28023453 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16087448 # num instructions producing a value -system.cpu2.iew.wb_consumers 29114707 # num instructions consuming a value +system.cpu2.iew.exec_nop 82965 # number of nop insts executed +system.cpu2.iew.exec_refs 14668868 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3706634 # Number of branches executed +system.cpu2.iew.exec_stores 3486681 # Number of stores executed +system.cpu2.iew.exec_rate 0.383584 # Inst execution rate +system.cpu2.iew.wb_sent 33494578 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28074190 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16115456 # num instructions producing a value +system.cpu2.iew.wb_consumers 29164308 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317210 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552554 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317712 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552575 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7129352 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356651 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170839 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35759991 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.708498 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.752281 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7126752 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357204 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170224 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35906001 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.707499 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.751012 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27025739 75.58% 75.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4219923 11.80% 87.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1248297 3.49% 90.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 635334 1.78% 92.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 557295 1.56% 94.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 319233 0.89% 95.09% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 417712 1.17% 96.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 309905 0.87% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1026553 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27147368 75.61% 75.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4230684 11.78% 87.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1251387 3.49% 90.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 639812 1.78% 92.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 559957 1.56% 94.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318640 0.89% 95.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 417979 1.16% 96.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311730 0.87% 97.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1028444 2.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35759991 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20506693 # Number of instructions committed -system.cpu2.commit.committedOps 25335895 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35906001 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20561870 # Number of instructions committed +system.cpu2.commit.committedOps 25403458 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8417234 # Number of memory references committed -system.cpu2.commit.loads 5080715 # Number of loads committed -system.cpu2.commit.membars 94304 # Number of memory barriers committed -system.cpu2.commit.branches 3173719 # Number of branches committed -system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22548127 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294799 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1026553 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8436727 # Number of memory references committed +system.cpu2.commit.loads 5094860 # Number of loads committed +system.cpu2.commit.membars 94449 # Number of memory barriers committed +system.cpu2.commit.branches 3185060 # Number of branches committed +system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22606405 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295605 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1028444 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66675347 # The number of ROB reads -system.cpu2.rob.rob_writes 66130617 # The number of ROB writes -system.cpu2.timesIdled 360964 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51427456 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3556668435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20451214 # Number of Instructions Simulated -system.cpu2.committedOps 25280416 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20451214 # Number of Instructions Simulated -system.cpu2.cpi 4.319722 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.319722 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231496 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231496 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 156902302 # number of integer regfile reads -system.cpu2.int_regfile_writes 29839836 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22382 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20836 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9252861 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241910 # number of misc regfile writes +system.cpu2.rob.rob_reads 66885510 # The number of ROB reads +system.cpu2.rob.rob_writes 66259648 # The number of ROB writes +system.cpu2.timesIdled 359925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51302262 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553994827 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20506347 # Number of Instructions Simulated +system.cpu2.committedOps 25347935 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20506347 # Number of Instructions Simulated +system.cpu2.cpi 4.309084 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.309084 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232068 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232068 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157055367 # number of integer regfile reads +system.cpu2.int_regfile_writes 29889640 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22622 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9269321 # number of misc regfile reads +system.cpu2.misc_regfile_writes 242794 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1838,10 +1972,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1279629373750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1279629373750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1346583006000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1346583006000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index b715fd89b..cc97b6f9f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,150 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.548576 # Number of seconds simulated -sim_ticks 2548576209000 # Number of ticks simulated -final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.549325 # Number of seconds simulated +sim_ticks 2549325180000 # Number of ticks simulated +final_tick 2549325180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64501 # Simulator instruction rate (inst/s) -host_op_rate 82996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2725389479 # Simulator tick rate (ticks/s) -host_mem_usage 403492 # Number of bytes of host memory used -host_seconds 935.12 # Real time elapsed on the host -sim_insts 60316464 # Number of instructions simulated -sim_ops 77611603 # Number of ops (including micro ops) simulated +host_inst_rate 61075 # Simulator instruction rate (inst/s) +host_op_rate 78588 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581455626 # Simulator tick rate (ticks/s) +host_mem_usage 428832 # Number of bytes of host memory used +host_seconds 987.55 # Real time elapsed on the host +sim_insts 60314884 # Number of instructions simulated +sim_ops 77609482 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 483776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5166800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 315264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3924504 # Number of bytes read from this memory -system.physmem.bytes_read::total 131003560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 483776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 315264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783488 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1522020 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494080 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799588 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 507840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4720464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 291712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4372184 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 507840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 291712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521520 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494580 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801764 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 80765 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 61326 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293434 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59117 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380505 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373520 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813142 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47520858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68321 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293464 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59151 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380380 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373645 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813176 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47506897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 678 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 189822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2027328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1539881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51402646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484550 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 597204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586241 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47520858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1851652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1715036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51388297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114427 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313633 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586265 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47506897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 678 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2624532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2126122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54070641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293434 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 813142 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15293434 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 813142 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 978779776 # Total number of bytes read from memory -system.physmem.bytesWritten 52041088 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131003560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799588 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 13 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955684 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955947 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955111 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955972 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956075 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955979 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6690 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6630 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6589 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6842 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6779 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7114 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6563 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7070 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6922 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2548575024500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 42 # Categorize read packet sizes -system.physmem.readPktSize::3 15138816 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154576 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754025 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59117 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1061686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 987876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 978214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2813374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2769477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 43265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu0.inst 199206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2448485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54056362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293464 # Number of read requests accepted +system.physmem.writeReqs 813176 # Number of write requests accepted +system.physmem.readBursts 15293464 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813176 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978217536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 564160 # Total number of bytes read from write queue +system.physmem.bytesWritten 6910272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131005480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801764 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8815 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705189 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4711 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955865 # Per bank write bursts +system.physmem.perBankRdBursts::1 955523 # Per bank write bursts +system.physmem.perBankRdBursts::2 954611 # Per bank write bursts +system.physmem.perBankRdBursts::3 954852 # Per bank write bursts +system.physmem.perBankRdBursts::4 955764 # Per bank write bursts +system.physmem.perBankRdBursts::5 955945 # Per bank write bursts +system.physmem.perBankRdBursts::6 954843 # Per bank write bursts +system.physmem.perBankRdBursts::7 954680 # Per bank write bursts +system.physmem.perBankRdBursts::8 956251 # Per bank write bursts +system.physmem.perBankRdBursts::9 955822 # Per bank write bursts +system.physmem.perBankRdBursts::10 954302 # Per bank write bursts +system.physmem.perBankRdBursts::11 954022 # Per bank write bursts +system.physmem.perBankRdBursts::12 956218 # Per bank write bursts +system.physmem.perBankRdBursts::13 955977 # Per bank write bursts +system.physmem.perBankRdBursts::14 955052 # Per bank write bursts +system.physmem.perBankRdBursts::15 954922 # Per bank write bursts +system.physmem.perBankWrBursts::0 6685 # Per bank write bursts +system.physmem.perBankWrBursts::1 6462 # Per bank write bursts +system.physmem.perBankWrBursts::2 6616 # Per bank write bursts +system.physmem.perBankWrBursts::3 6625 # Per bank write bursts +system.physmem.perBankWrBursts::4 6578 # Per bank write bursts +system.physmem.perBankWrBursts::5 6834 # Per bank write bursts +system.physmem.perBankWrBursts::6 6825 # Per bank write bursts +system.physmem.perBankWrBursts::7 6778 # Per bank write bursts +system.physmem.perBankWrBursts::8 7112 # Per bank write bursts +system.physmem.perBankWrBursts::9 6876 # Per bank write bursts +system.physmem.perBankWrBursts::10 6540 # Per bank write bursts +system.physmem.perBankWrBursts::11 6189 # Per bank write bursts +system.physmem.perBankWrBursts::12 7142 # Per bank write bursts +system.physmem.perBankWrBursts::13 6759 # Per bank write bursts +system.physmem.perBankWrBursts::14 7042 # Per bank write bursts +system.physmem.perBankWrBursts::15 6910 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2549324058500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 42 # Read request sizes (log2) +system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 154606 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754025 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59151 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1187642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1126920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1081304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3687011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2647213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2642028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2655762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 54010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -157,31 +171,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -189,456 +203,675 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39284 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 25091.701456 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2070.748672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31471.829892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 6644 16.91% 16.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 3436 8.75% 25.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 2300 5.85% 31.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 1832 4.66% 36.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 1227 3.12% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 1105 2.81% 42.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 800 2.04% 44.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 812 2.07% 46.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 554 1.41% 47.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 516 1.31% 48.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 427 1.09% 50.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 432 1.10% 51.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 277 0.71% 51.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 299 0.76% 52.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 172 0.44% 53.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 211 0.54% 53.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 136 0.35% 53.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 132 0.34% 54.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 101 0.26% 54.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 106 0.27% 54.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 70 0.18% 54.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 391 1.00% 55.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 264 0.67% 56.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 450 1.15% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 85 0.22% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 167 0.43% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 56 0.14% 58.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 95 0.24% 58.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 44 0.11% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 79 0.20% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 30 0.08% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 69 0.18% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 18 0.05% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 44 0.11% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 15 0.04% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 32 0.08% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 19 0.05% 59.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 8 0.02% 59.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 26 0.07% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 6 0.02% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 18 0.05% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 15 0.04% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 16 0.04% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 7 0.02% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 13 0.03% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 4 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 18 0.05% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 6 0.02% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 6 0.02% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 11 0.03% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 6 0.02% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 10 0.03% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 5 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 3 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3919 1 0.00% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3983 13 0.03% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 4 0.01% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 32 0.08% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4175 5 0.01% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4239 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4303 3 0.01% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 6 0.02% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4495 5 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4559 4 0.01% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4623 6 0.02% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 3 0.01% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4879 4 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 7 0.02% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 8 0.02% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5199 2 0.01% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5263 2 0.01% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 3 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 3 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5519 4 0.01% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5583 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5775 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5903 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6095 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6223 3 0.01% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 2 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6351 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 2 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6607 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6735 1 0.00% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 20 0.05% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 3 0.01% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7119 2 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7311 3 0.01% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 2 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 4 0.01% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7567 9 0.02% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7631 1 0.00% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 7 0.02% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7823 3 0.01% 60.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7887 4 0.01% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 2 0.01% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 11 0.03% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8143 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 311 0.79% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 63 0.16% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 194 0.49% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 13 0.03% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8783 3 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20495 1 0.00% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25615 2 0.01% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28367 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32207 1 0.00% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33359 1 0.00% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33679 2 0.01% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 2 0.01% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34575 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37199 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39503 1 0.00% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45071 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58127 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64768-64783 1 0.00% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 14685 37.38% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::68736-68751 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73935 9 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-73999 43 0.11% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74063 33 0.08% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39284 # Bytes accessed per row activation -system.physmem.totQLat 294283871250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 386089225000 # Sum of mem lat for all requests -system.physmem.totBusLat 76467105000 # Total cycles spent in databus access -system.physmem.totBankLat 15338248750 # Total cycles spent in bank access -system.physmem.avgQLat 19242.51 # Average queueing delay per request -system.physmem.avgBankLat 1002.93 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25245.45 # Average memory access latency -system.physmem.avgRdBW 384.05 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.08 # Average write queue length over time -system.physmem.readRowHits 15268174 # Number of row buffer hits during reads -system.physmem.writeRowHits 94166 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.58 # Row buffer hit rate for writes -system.physmem.avgGap 158231.96 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55011549 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346066 # Transaction distribution -system.membus.trans_dist::ReadResp 16346069 # Transaction distribution +system.physmem.bytesPerActivate::samples 86834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11344.953359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1015.074534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16830.192081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23626 27.21% 27.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14089 16.23% 43.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2724 3.14% 46.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2126 2.45% 49.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1310 1.51% 50.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1204 1.39% 51.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 811 0.93% 52.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1018 1.17% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 572 0.66% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 583 0.67% 55.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 533 0.61% 55.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 603 0.69% 56.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 265 0.31% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 147 0.17% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 578 0.67% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 113 0.13% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 129 0.15% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 237 0.27% 58.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 56 0.06% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 502 0.58% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 39 0.04% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 171 0.20% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 11 0.01% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 115 0.13% 59.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 15 0.02% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 109 0.13% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 18 0.02% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 54 0.06% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 24 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 490 0.56% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 17 0.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 7 0.01% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 154 0.18% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 14 0.02% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 32 0.04% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 7 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 95 0.11% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 14 0.02% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 9 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 155 0.18% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 16 0.02% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 408 0.47% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 96 0.11% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 10 0.01% 61.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 20 0.02% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.01% 61.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 86 0.10% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 6 0.01% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 21 0.02% 62.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 12 0.01% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 58 0.07% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 407 0.47% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 10 0.01% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 18 0.02% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 3 0.00% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 75 0.09% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 12 0.01% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 7 0.01% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 139 0.16% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 8 0.01% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 72 0.08% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 17 0.02% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 76 0.09% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 9 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 13 0.01% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 144 0.17% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 9 0.01% 63.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 13 0.01% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 12 0.01% 64.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 6 0.01% 64.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 262 0.30% 64.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 5 0.01% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 136 0.16% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 8 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 21 0.02% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 74 0.09% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 8 0.01% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 452 0.52% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 4 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 13 0.01% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 23 0.03% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 4 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 73 0.08% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 3 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 132 0.15% 65.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 243 0.28% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 128 0.15% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 66 0.08% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 67 0.08% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 450 0.52% 66.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 67 0.08% 66.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 2 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 1 0.00% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 251 0.29% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 128 0.15% 67.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 66 0.08% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 387 0.45% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 67 0.08% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 1 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 121 0.14% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 66 0.08% 68.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 380 0.44% 68.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 37 0.04% 68.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 69 0.08% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 65 0.07% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 389 0.45% 69.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 129 0.15% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 66 0.08% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 120 0.14% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 443 0.51% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 57 0.07% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 13 0.01% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 119 0.14% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 388 0.45% 71.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 123 0.14% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15751 1 0.00% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 64 0.07% 71.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 66 0.08% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 526 0.61% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 68 0.08% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 64 0.07% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 122 0.14% 72.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 391 0.45% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 120 0.14% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 15 0.02% 72.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 57 0.07% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 444 0.51% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 119 0.14% 73.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 66 0.08% 73.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 129 0.15% 73.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 64 0.07% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 70 0.08% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 37 0.04% 74.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 1 0.00% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 382 0.44% 74.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 65 0.07% 74.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 119 0.14% 75.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 66 0.08% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 385 0.44% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 68 0.08% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 128 0.15% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 69 0.08% 75.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 75.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 253 0.29% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 132 0.15% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 1 0.00% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 67 0.08% 76.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 450 0.52% 76.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 67 0.08% 77.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 129 0.15% 77.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 137 0.16% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 1 0.00% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 129 0.15% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 67 0.08% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 67 0.08% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 448 0.52% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25671 1 0.00% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 66 0.08% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 134 0.15% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 253 0.29% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 68 0.08% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 129 0.15% 78.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 78.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 68 0.08% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 384 0.44% 79.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 66 0.08% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 119 0.14% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 64 0.07% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 380 0.44% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 37 0.04% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 72 0.08% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 65 0.07% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 385 0.44% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 129 0.15% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 64 0.07% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 119 0.14% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 443 0.51% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 56 0.06% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 13 0.01% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 119 0.14% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 389 0.45% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31815 1 0.00% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 124 0.14% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 66 0.08% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 66 0.08% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 65 0.07% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 125 0.14% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 390 0.45% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 119 0.14% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 13 0.01% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 56 0.06% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 441 0.51% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 119 0.14% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.07% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 129 0.15% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 385 0.44% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 72 0.08% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 37 0.04% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 380 0.44% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 119 0.14% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 66 0.08% 86.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 384 0.44% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 67 0.08% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 128 0.15% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 68 0.08% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 253 0.29% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 134 0.15% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 66 0.08% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 448 0.52% 88.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 68 0.08% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 66 0.08% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 129 0.15% 88.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 137 0.16% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 129 0.15% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 67 0.08% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 449 0.52% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 67 0.08% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 132 0.15% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 251 0.29% 90.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 67 0.08% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43392-43399 2 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 128 0.15% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 67 0.08% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 384 0.44% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 68 0.08% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44480-44487 1 0.00% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 119 0.14% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 66 0.08% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 383 0.44% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 41 0.05% 91.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 65 0.07% 91.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 385 0.44% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 129 0.15% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 64 0.07% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 119 0.14% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 440 0.51% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 58 0.07% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 14 0.02% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 120 0.14% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 388 0.45% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 122 0.14% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 64 0.07% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 65 0.07% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5147 5.93% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86834 # Bytes accessed per row activation +system.physmem.totQLat 369633946000 # Total ticks spent queuing +system.physmem.totMemAccLat 463601929750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76423245000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17544738750 # Total ticks spent accessing banks +system.physmem.avgQLat 24183.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1147.87 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30331.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing +system.physmem.readRowHits 15212610 # Number of row buffer hits during reads +system.physmem.writeRowHits 93178 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes +system.physmem.avgGap 158277.83 # Average gap between requests +system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54996997 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346113 # Transaction distribution +system.membus.trans_dist::ReadResp 16346116 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4675 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4677 # Transaction distribution -system.membus.trans_dist::ReadExReq 131414 # Transaction distribution -system.membus.trans_dist::ReadExResp 131414 # Transaction distribution +system.membus.trans_dist::Writeback 59151 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4708 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4711 # Transaction distribution +system.membus.trans_dist::ReadExReq 131399 # Transaction distribution +system.membus.trans_dist::ReadExResp 131399 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885757 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272507 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272673 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550139 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390329 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550305 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692620 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19090597 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696716 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094701 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140201125 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140201125 # Total data (bytes) +system.membus.tot_pkt_size::total 140205229 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140205229 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475672000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487741000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3601000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17572541000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17567405000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4757385335 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4737923280 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34173123993 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34188515482 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64349 # number of replacements -system.l2c.tags.tagsinuse 51432.213982 # Cycle average of tags in use -system.l2c.tags.total_refs 1904557 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129741 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.679685 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2511462555500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36971.376669 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.336615 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4863.234399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3340.353025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.819885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3340.869034 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2888.223986 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564138 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000295 # Average percentage of cache occupancy +system.l2c.tags.replacements 64379 # number of replacements +system.l2c.tags.tagsinuse 51427.622498 # Cycle average of tags in use +system.l2c.tags.total_refs 1904241 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.674195 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2512188924000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36951.825179 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.926736 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4986.850446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3336.949611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.947160 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3226.583152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2894.539843 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563840 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000289 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.050978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044071 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784793 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 31056 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 489944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 180708 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 32283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 480968 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 206794 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435577 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608201 # number of Writeback hits -system.l2c.Writeback_hits::total 608201 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 22 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.076093 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050918 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.049234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044167 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784723 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 505956 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 182118 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30730 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464492 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 205502 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435201 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits +system.l2c.Writeback_hits::total 608382 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56719 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56246 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112965 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 31056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 489944 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 237427 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 32283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 480968 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 263040 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548542 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 31056 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6811 # number of overall hits -system.l2c.overall_hits::cpu0.inst 489944 # number of overall hits -system.l2c.overall_hits::cpu0.data 237427 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 32283 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7013 # number of overall hits -system.l2c.overall_hits::cpu1.inst 480968 # number of overall hits -system.l2c.overall_hits::cpu1.data 263040 # number of overall hits -system.l2c.overall_hits::total 1548542 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 15 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58173 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54780 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112953 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32603 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 505956 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240291 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30730 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260282 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548154 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32603 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7139 # number of overall hits +system.l2c.overall_hits::cpu0.inst 505956 # number of overall hits +system.l2c.overall_hits::cpu0.data 240291 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30730 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6661 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464492 # number of overall hits +system.l2c.overall_hits::cpu1.data 260282 # number of overall hits +system.l2c.overall_hits::total 1548154 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7450 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6327 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4932 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4374 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1313 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1598 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu0.inst 7825 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6187 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4565 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4551 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23171 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1631 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2916 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 75216 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 57962 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133178 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 68474 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 64717 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133191 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7450 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 81543 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4932 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 62336 # number of demand (read+write) misses -system.l2c.demand_misses::total 156303 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7825 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74661 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4565 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 69268 # number of demand (read+write) misses +system.l2c.demand_misses::total 156362 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7450 # number of overall misses -system.l2c.overall_misses::cpu0.data 81543 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4932 # number of overall misses -system.l2c.overall_misses::cpu1.data 62336 # number of overall misses -system.l2c.overall_misses::total 156303 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2773750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 535863000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 458241999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 375877250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 330560248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1704596747 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 185492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 279988 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5248575225 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3913924011 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9162499236 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2773750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 130250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 535863000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5706817224 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1150250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 375877250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4244484259 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10867095983 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2773750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 130250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 535863000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5706817224 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1150250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 375877250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4244484259 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10867095983 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 31085 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6813 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 497394 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 187035 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 32294 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7013 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 485900 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 211168 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1458702 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608201 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608201 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1331 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1620 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 131935 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 114208 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246143 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 31085 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6813 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 497394 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 318970 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 32294 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7013 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 485900 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 325376 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1704845 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 31085 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6813 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 497394 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 318970 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 32294 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7013 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 485900 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 325376 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1704845 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000294 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.033828 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010150 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020713 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015853 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.986476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986420 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.986445 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.570099 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.507513 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541059 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000294 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014978 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.255645 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010150 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.191581 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091682 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000294 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.255645 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010150 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.191581 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091682 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65125 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71927.919463 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 72426.426268 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76211.932279 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75573.902149 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73712.291762 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 141.273420 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 175.211514 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 159.903813 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69780.036495 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67525.689434 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 68798.894983 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71927.919463 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69985.372429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76211.932279 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 68090.417399 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69525.831129 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71927.919463 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69985.372429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76211.932279 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 68090.417399 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69525.831129 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 7825 # number of overall misses +system.l2c.overall_misses::cpu0.data 74661 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4565 # number of overall misses +system.l2c.overall_misses::cpu1.data 69268 # number of overall misses +system.l2c.overall_misses::total 156362 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2234250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 566532750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 458261500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1111500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 342566000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 354437999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1725301999 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 254989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 187492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 442481 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5097311886 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4928859322 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10026171208 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2234250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 566532750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5555573386 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1111500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 342566000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5283297321 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11751473207 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2234250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 566532750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5555573386 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1111500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 342566000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5283297321 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11751473207 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32630 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7141 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 513781 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 188305 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30744 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6661 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 469057 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 210053 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458372 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 608382 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 608382 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1307 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1649 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 12 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 126647 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 119497 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246144 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7141 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 513781 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314952 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30744 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6661 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 469057 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 329550 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704516 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7141 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 513781 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 314952 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30744 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6661 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 469057 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 329550 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704516 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000280 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015230 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.032856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009732 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021666 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015888 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.983168 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989084 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986468 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.166667 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.166667 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.540668 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.541578 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541110 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000280 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015230 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.237055 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009732 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.210190 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091734 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000280 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015230 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.237055 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009732 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.210190 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091734 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72400.351438 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74068.449976 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75041.840088 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77881.344540 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 74459.539899 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 198.435019 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 114.955242 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 151.742455 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74441.567398 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76160.194725 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 75276.641875 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 72400.351438 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 74410.647942 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75041.840088 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76273.276563 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 75155.557022 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 72400.351438 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 74410.647942 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75041.840088 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76273.276563 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 75155.557022 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,166 +880,170 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59117 # number of writebacks -system.l2c.writebacks::total 59117 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 78 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 59151 # number of writebacks +system.l2c.writebacks::total 59151 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7444 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6288 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4926 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4347 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23047 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1313 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1598 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2911 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7820 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6145 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4558 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4526 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23092 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1285 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1631 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 75216 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 57962 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133178 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 68474 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 64717 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7444 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 81504 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4926 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 62309 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156225 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7820 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 74619 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4558 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 69243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156283 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7444 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 81504 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4926 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 62309 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156225 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 440932000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 376527749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 313110000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 273532998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1407620997 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13131313 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15986098 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29117411 # number of UpgradeReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7820 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 74619 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4558 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 69243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156283 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 133500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 467782250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 379156500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 939000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 284899750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 296279749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1431092999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12851285 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 16316631 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29167916 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4295181775 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3176975989 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7472157764 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 440932000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4671709524 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 313110000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3450508987 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8879778761 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 440932000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4671709524 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 313110000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3450508987 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8879778761 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6023999 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84465244500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82459599500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166930867999 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8917288738 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8449538500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17366827238 # number of WriteReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4242388114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4120773678 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8363161792 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 467782250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4621544614 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 939000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 284899750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4417053427 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9794254791 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 467782250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4621544614 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 939000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 284899750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4417053427 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9794254791 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6012999 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84576136750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82361165750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166943315499 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8951295259 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8415675500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17366970759 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6023999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93382533238 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90909138000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184297695237 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033619 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020586 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015800 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986476 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986420 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.986445 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570099 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.507513 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541059 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091636 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091636 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 59880.367207 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62924.545204 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61076.105220 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6012999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93527432009 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90776841250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184310286258 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015834 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983168 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989084 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986468 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540668 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.541578 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541110 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.236922 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.210114 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091688 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.236922 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.210114 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091688 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61701.627339 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65461.720946 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61973.540577 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.816020 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.545861 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.065604 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.714678 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57104.629002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 54811.358977 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56106.547358 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61956.189415 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63673.743808 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62790.742558 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -829,49 +1066,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58475740 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676749 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676751 # Transaction distribution +system.toL2Bus.throughput 58456334 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676393 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676395 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608201 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2951 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246143 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246143 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608382 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2974 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246144 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246144 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967991 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797697 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37845 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149237 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952770 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62938176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85577189 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148824185 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148824185 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 205696 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4963674463 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798220 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37803 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952295 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62908992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85598765 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148816461 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148816461 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 207744 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964319701 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4434137240 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4431802148 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4494378467 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4486267320 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24064152 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24046904 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86310594 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86228845 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48458766 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322134 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322134 # Transaction distribution +system.iobus.throughput 48444532 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -893,12 +1130,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382960 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660588 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660592 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -920,14 +1157,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390329 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390337 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500857 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500857 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500865 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500865 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -973,684 +1210,684 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374796000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41501700007 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41492591518 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7055231 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5603867 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 360036 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4627391 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3766189 # Number of BTB hits +system.cpu0.branchPred.lookups 7178846 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5689563 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 376334 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4735029 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3823898 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.389038 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 696378 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 37374 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.757647 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 708733 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25604020 # DTB read hits -system.cpu0.dtb.read_misses 37101 # DTB read misses -system.cpu0.dtb.write_hits 6019786 # DTB write hits -system.cpu0.dtb.write_misses 10089 # DTB write misses +system.cpu0.dtb.read_hits 25686724 # DTB read hits +system.cpu0.dtb.read_misses 37672 # DTB read misses +system.cpu0.dtb.write_hits 5882199 # DTB write hits +system.cpu0.dtb.write_misses 9157 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5563 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1360 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5402 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1359 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 227 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 609 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25641121 # DTB read accesses -system.cpu0.dtb.write_accesses 6029875 # DTB write accesses +system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25724396 # DTB read accesses +system.cpu0.dtb.write_accesses 5891356 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31623806 # DTB hits -system.cpu0.dtb.misses 47190 # DTB misses -system.cpu0.dtb.accesses 31670996 # DTB accesses -system.cpu0.itb.inst_hits 5711817 # ITB inst hits -system.cpu0.itb.inst_misses 6786 # ITB inst misses +system.cpu0.dtb.hits 31568923 # DTB hits +system.cpu0.dtb.misses 46829 # DTB misses +system.cpu0.dtb.accesses 31615752 # DTB accesses +system.cpu0.itb.inst_hits 5794960 # ITB inst hits +system.cpu0.itb.inst_misses 6979 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2537 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1280 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5718603 # ITB inst accesses -system.cpu0.itb.hits 5711817 # DTB hits -system.cpu0.itb.misses 6786 # DTB misses -system.cpu0.itb.accesses 5718603 # DTB accesses -system.cpu0.numCycles 240384739 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5801939 # ITB inst accesses +system.cpu0.itb.hits 5794960 # DTB hits +system.cpu0.itb.misses 6979 # DTB misses +system.cpu0.itb.accesses 5801939 # DTB accesses +system.cpu0.numCycles 241329954 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15036708 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44324460 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7055231 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4462567 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9979880 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2348952 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 79920 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48371030 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 40136 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1395788 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5710035 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 358939 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3057 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 76524952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.728839 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.080650 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15402359 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44612176 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7178846 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4532631 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10046821 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2409329 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81802 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48777724 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1779 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1966 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 42894 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1416575 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 470 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5793020 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368373 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3163 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77432013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722773 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.070911 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66552751 86.97% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 648002 0.85% 87.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 843291 1.10% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1146450 1.50% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1051496 1.37% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 533927 0.70% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1248962 1.63% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 369566 0.48% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4130507 5.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67393349 87.04% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 663167 0.86% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 850708 1.10% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1161944 1.50% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1070979 1.38% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 538004 0.69% 92.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1258402 1.63% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 372673 0.48% 94.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4122787 5.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76524952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029350 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184390 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15988793 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49427885 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9067900 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 506950 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1531254 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 959604 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89006 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53104636 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 296594 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1531254 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16866391 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20063365 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26274348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8616750 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3170765 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50610961 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7411 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 529520 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2115247 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 214169305 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4937 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 362796 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6588533 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9723453 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6830710 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1010499 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1245426 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47056287 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 968125 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61041577 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 84130 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9522170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23883479 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 244384 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76524952 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.797669 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.517362 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77432013 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029747 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184860 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16324291 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49901037 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9152885 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 482910 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1568783 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 985989 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 93507 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53239353 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 312067 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1568783 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17193647 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20516369 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26371209 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8691714 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3088262 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50703360 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7236 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 484563 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2089605 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 237 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52223867 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231534090 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 214067803 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5431 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38086867 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14136999 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 416413 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 366902 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6391113 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9801074 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6698586 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1023553 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1394670 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47085778 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 981191 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 61028996 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9766291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24255892 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256976 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77432013 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.788162 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.509612 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54759555 71.56% 71.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6733047 8.80% 80.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3420180 4.47% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2920085 3.82% 88.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6164290 8.06% 96.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1467950 1.92% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 772657 1.01% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 222441 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 64747 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55649099 71.87% 71.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6737778 8.70% 80.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3435441 4.44% 85.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2925983 3.78% 88.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6185685 7.99% 96.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1437832 1.86% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 773159 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224755 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 62281 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76524952 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77432013 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27542 0.62% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4220431 94.60% 95.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 213140 4.78% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29912 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221653 94.70% 95.37% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206360 4.63% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 171568 0.28% 0.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28242983 46.27% 46.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47431 0.08% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1218 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.63% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26256845 43.01% 89.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6321515 10.36% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 165947 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28282024 46.34% 46.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46844 0.08% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1271 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26348641 43.17% 89.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6184237 10.13% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61041577 # Type of FU issued -system.cpu0.iq.rate 0.253933 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4461113 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073083 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 203189112 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57554843 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42164489 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11244 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5997 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4944 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65325122 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6000 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306679 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 61028996 # Type of FU issued +system.cpu0.iq.rate 0.252886 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4457926 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073046 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 204069737 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57841875 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42095336 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12029 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6474 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5396 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65314591 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6384 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 305188 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2052481 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3874 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 14810 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 826086 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2103037 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3902 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15671 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 837358 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17207144 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348104 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17232684 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348213 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1531254 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15306015 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 241273 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48127004 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 101529 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9723453 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6830710 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 683062 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 53931 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 11240 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 14810 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 174193 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 137584 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 311777 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 60001377 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 25939220 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1040200 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1568783 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15829049 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 237688 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48167223 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105126 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9801074 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6698586 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 691561 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54422 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4242 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15671 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 182031 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 143561 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 325592 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 59970791 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26024613 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1058205 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 102592 # number of nop insts executed -system.cpu0.iew.exec_refs 32204815 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5606114 # Number of branches executed -system.cpu0.iew.exec_stores 6265595 # Number of stores executed -system.cpu0.iew.exec_rate 0.249606 # Inst execution rate -system.cpu0.iew.wb_sent 59520960 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42169433 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22855569 # num instructions producing a value -system.cpu0.iew.wb_consumers 42162980 # num instructions consuming a value +system.cpu0.iew.exec_nop 100254 # number of nop insts executed +system.cpu0.iew.exec_refs 32151728 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5674244 # Number of branches executed +system.cpu0.iew.exec_stores 6127115 # Number of stores executed +system.cpu0.iew.exec_rate 0.248501 # Inst execution rate +system.cpu0.iew.wb_sent 59482820 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42100732 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22797313 # num instructions producing a value +system.cpu0.iew.wb_consumers 41683102 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.175425 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.542077 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.174453 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546920 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9402485 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 723741 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 272429 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74993698 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.510414 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.487877 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9635326 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 724215 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 284304 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75863230 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.501725 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.477269 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61390308 81.86% 81.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6607868 8.81% 90.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1921399 2.56% 93.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1064491 1.42% 94.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 990154 1.32% 95.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 565334 0.75% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 721378 0.96% 97.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 343964 0.46% 98.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1388802 1.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 62300247 82.12% 82.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6632163 8.74% 90.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1905948 2.51% 93.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1063803 1.40% 94.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 963459 1.27% 96.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 539688 0.71% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 720050 0.95% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 348558 0.46% 98.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1389314 1.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74993698 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29384265 # Number of instructions committed -system.cpu0.commit.committedOps 38277857 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75863230 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29321704 # Number of instructions committed +system.cpu0.commit.committedOps 38062462 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13675596 # Number of memory references committed -system.cpu0.commit.loads 7670972 # Number of loads committed -system.cpu0.commit.membars 201047 # Number of memory barriers committed -system.cpu0.commit.branches 4859392 # Number of branches committed -system.cpu0.commit.fp_insts 4891 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33962414 # Number of committed integer instructions. -system.cpu0.commit.function_calls 491145 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1388802 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13559265 # Number of memory references committed +system.cpu0.commit.loads 7698037 # Number of loads committed +system.cpu0.commit.membars 204059 # Number of memory barriers committed +system.cpu0.commit.branches 4889328 # Number of branches committed +system.cpu0.commit.fp_insts 5354 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33742241 # Number of committed integer instructions. +system.cpu0.commit.function_calls 497179 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1389314 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 120378043 # The number of ROB reads -system.cpu0.rob.rob_writes 96934970 # The number of ROB writes -system.cpu0.timesIdled 903993 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163859787 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2252055071 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29315772 # Number of Instructions Simulated -system.cpu0.committedOps 38209364 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29315772 # Number of Instructions Simulated -system.cpu0.cpi 8.199843 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.199843 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.121954 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.121954 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271685631 # number of integer regfile reads -system.cpu0.int_regfile_writes 42795201 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22306 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19768 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15093810 # number of misc regfile reads -system.cpu0.misc_regfile_writes 401151 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983925 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.538497 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10508756 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984437 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.674889 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6941856250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 321.486243 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 190.052254 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.627903 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.371196 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999099 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5171009 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5337747 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10508756 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5171009 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5337747 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10508756 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5171009 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5337747 # number of overall hits -system.cpu0.icache.overall_hits::total 10508756 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 538904 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 526390 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065294 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 538904 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 526390 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065294 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 538904 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 526390 # number of overall misses -system.cpu0.icache.overall_misses::total 1065294 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7446919215 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7105468986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14552388201 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7446919215 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7105468986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14552388201 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7446919215 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7105468986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14552388201 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5709913 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5864137 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11574050 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5709913 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5864137 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11574050 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5709913 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5864137 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11574050 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094380 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089764 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092042 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094380 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089764 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092042 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094380 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089764 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092042 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13818.637856 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.487787 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.443221 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13660.443221 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13660.443221 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6869 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1025 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 398 # number of cycles access was blocked +system.cpu0.rob.rob_reads 121250209 # The number of ROB reads +system.cpu0.rob.rob_writes 97007351 # The number of ROB writes +system.cpu0.timesIdled 906901 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 163897941 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2251401803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29254206 # Number of Instructions Simulated +system.cpu0.committedOps 37994964 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29254206 # Number of Instructions Simulated +system.cpu0.cpi 8.249410 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.249410 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.121221 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.121221 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 271506841 # number of integer regfile reads +system.cpu0.int_regfile_writes 42814380 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22646 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19918 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15055897 # number of misc regfile reads +system.cpu0.misc_regfile_writes 404161 # number of misc regfile writes +system.cpu0.icache.tags.replacements 983492 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.574238 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10516196 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984004 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.687148 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6986136250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 318.901478 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 192.672760 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.622854 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.376314 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5235281 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5280915 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10516196 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5235281 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5280915 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10516196 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5235281 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5280915 # number of overall hits +system.cpu0.icache.overall_hits::total 10516196 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 557620 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 507749 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065369 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 557620 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 507749 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065369 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 557620 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 507749 # number of overall misses +system.cpu0.icache.overall_misses::total 1065369 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7715888650 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6834076460 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14549965110 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7715888650 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6834076460 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14549965110 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7715888650 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6834076460 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14549965110 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5792901 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5788664 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11581565 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5792901 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5788664 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11581565 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5792901 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5788664 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11581565 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096259 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087714 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.091988 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096259 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087714 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.091988 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096259 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087714 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.091988 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13837.180607 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13459.556710 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.207137 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13657.207137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13657.207137 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6518 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 829 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 410 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.258794 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 1025 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.897561 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 829 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40970 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39858 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80828 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 40970 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39858 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80828 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 40970 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39858 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80828 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 497934 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 486532 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984466 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 497934 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 486532 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984466 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 497934 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 486532 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984466 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6047465345 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5786819388 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11834284733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6047465345 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5786819388 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11834284733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6047465345 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5786819388 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11834284733 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8439000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8439000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8439000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8439000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085058 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085058 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085058 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12021.019246 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12021.019246 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12021.019246 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38074 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 81323 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 38074 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 81323 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 38074 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 81323 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 514371 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469675 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984046 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 514371 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 469675 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984046 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 514371 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 469675 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984046 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6258994404 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5567069659 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11826064063 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258994404 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5567069659 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11826064063 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258994404 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5567069659 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11826064063 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8426500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8426500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8426500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8426500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084967 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084967 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084967 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.795980 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643834 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993352 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21533253 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644346 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.418773 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42568250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.929916 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.063436 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497910 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502077 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 643990 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21534082 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644502 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.411971 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43026250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.795317 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.198007 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499600 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500387 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6778619 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6998983 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13777602 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3655456 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3606248 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261704 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113306 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129840 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 115957 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131727 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247684 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10434075 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10605231 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21039306 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10434075 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10605231 # number of overall hits -system.cpu0.dcache.overall_hits::total 21039306 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 328027 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 420957 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 748984 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1610503 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1351638 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2962141 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7363 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6159 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13522 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 8 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1938530 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1772595 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3711125 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1938530 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1772595 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711125 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5252707334 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6136741422 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11389448756 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82511290457 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 60760612895 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 143271903352 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104363999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 83076247 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 187440246 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 129002 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 155002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 87763997791 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66897354317 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 154661352108 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 87763997791 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66897354317 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 154661352108 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7106646 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7419940 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14526586 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5265959 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4957886 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223845 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 120669 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135999 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256668 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 115959 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131735 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247694 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12372605 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12377826 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24750431 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12372605 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12377826 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24750431 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046158 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.056733 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051560 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.305833 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.272624 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289729 # miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6836118 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6942659 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13778777 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3601868 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3659456 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261324 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114429 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 128738 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243167 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116989 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 130670 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247659 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10437986 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10602115 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21040101 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10437986 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10602115 # number of overall hits +system.cpu0.dcache.overall_hits::total 21040101 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 327145 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 421730 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 748875 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1520256 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1442024 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2962280 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7436 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6109 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13545 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 12 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1847401 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1863754 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711155 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1847401 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1863754 # number of overall misses +system.cpu0.dcache.overall_misses::total 3711155 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5258794781 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6175311803 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11434106584 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76116558084 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 73496602051 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 149613160135 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106253499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82007996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 188261495 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90501 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 181002 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 271503 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 81375352865 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 79671913854 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 161047266719 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 81375352865 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 79671913854 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 161047266719 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7163263 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7364389 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14527652 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5122124 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5101480 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223604 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121865 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 134847 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256712 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116995 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 130682 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247677 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12285387 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12465869 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24751256 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12285387 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12465869 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24751256 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045670 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057266 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051548 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.296802 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.282668 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289749 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045287 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052683 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000061 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.156679 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.143207 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149942 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.156679 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.143207 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149942 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16013.033482 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14578.071922 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15206.531456 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51233.242321 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44953.318044 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48367.685182 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14174.113676 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13488.593440 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13861.872948 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16125.250000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15500.200000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45273.479281 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37739.785070 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41675.058670 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45273.479281 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37739.785070 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41675.058670 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36870 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 26211 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3510 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 295 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.504274 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 88.850847 # average number of cycles each access was blocked +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045303 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000051 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000092 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150374 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.149509 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149938 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.150374 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.149509 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149938 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16074.813251 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14642.808913 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15268.378012 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50068.250403 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50967.669089 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50506.083198 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14289.066568 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13424.127680 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13898.966039 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15083.500000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43395.456864 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43395.456864 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 38322 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25151 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3482 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 293 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.005744 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 85.839590 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608201 # number of writebacks -system.cpu0.dcache.writebacks::total 608201 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 147533 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 215292 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362825 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1477292 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1235866 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2713158 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 767 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 600 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1367 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1624825 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1451158 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3075983 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1624825 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1451158 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3075983 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180494 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205665 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386159 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 133211 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 115772 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6596 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5559 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12155 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 313705 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 321437 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 313705 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 321437 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2529137468 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2700943395 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5230080863 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6074560248 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4703819078 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10778379326 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82036251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64895003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146931254 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 112998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8603697716 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7404762473 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16008460189 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8603697716 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7404762473 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16008460189 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92246094501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90072157750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182318252251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13667158074 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13097409574 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26764567648 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608382 # number of writebacks +system.cpu0.dcache.writebacks::total 608382 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 145500 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 217105 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362605 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392355 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1320933 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713288 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 723 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 626 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1537855 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1538038 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3075893 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1537855 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1538038 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3075893 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181645 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 204625 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386270 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127901 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121091 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248992 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6713 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5483 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12196 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309546 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 325716 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635262 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309546 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 325716 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635262 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2539210775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2715181297 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5254392072 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5938244941 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5721716845 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11659961786 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84451251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63563504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148014755 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 156998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 235497 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8477455716 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8436898142 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16914353858 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8477455716 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8436898142 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16914353858 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92366768250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89963955251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330723501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13704367995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13062365000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26766732995 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105913252575 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103169567324 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209082819899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025398 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027718 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025297 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023351 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054662 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040875 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047357 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025662 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025662 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14012.307711 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13132.732332 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13543.853343 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45601.040815 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40630.023477 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43289.619476 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12437.272741 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11673.862745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12088.132785 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13499.800000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106071136245 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103026320251 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209097456496 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025358 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027786 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024970 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023736 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055086 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040661 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047508 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000051 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000092 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13978.974235 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13269.059484 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.899713 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46428.448104 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47251.379913 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46828.660302 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12580.254879 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11592.833121 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12136.336094 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1665,324 +1902,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7417918 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5931932 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 364646 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4881678 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3917644 # Number of BTB hits +system.cpu1.branchPred.lookups 7299586 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5849815 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347289 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4589899 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3862662 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.251995 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 703527 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35801 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.155708 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 691728 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34987 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25617777 # DTB read hits -system.cpu1.dtb.read_misses 38543 # DTB read misses -system.cpu1.dtb.write_hits 5691491 # DTB write hits -system.cpu1.dtb.write_misses 8859 # DTB write misses +system.cpu1.dtb.read_hits 25535708 # DTB read hits +system.cpu1.dtb.read_misses 37819 # DTB read misses +system.cpu1.dtb.write_hits 5832824 # DTB write hits +system.cpu1.dtb.write_misses 9748 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5585 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2011 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2100 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 659 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25656320 # DTB read accesses -system.cpu1.dtb.write_accesses 5700350 # DTB write accesses +system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25573527 # DTB read accesses +system.cpu1.dtb.write_accesses 5842572 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31309268 # DTB hits -system.cpu1.dtb.misses 47402 # DTB misses -system.cpu1.dtb.accesses 31356670 # DTB accesses -system.cpu1.itb.inst_hits 5866342 # ITB inst hits -system.cpu1.itb.inst_misses 7403 # ITB inst misses +system.cpu1.dtb.hits 31368532 # DTB hits +system.cpu1.dtb.misses 47567 # DTB misses +system.cpu1.dtb.accesses 31416099 # DTB accesses +system.cpu1.itb.inst_hits 5790816 # ITB inst hits +system.cpu1.itb.inst_misses 7158 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2684 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1687 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1580 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5873745 # ITB inst accesses -system.cpu1.itb.hits 5866342 # DTB hits -system.cpu1.itb.misses 7403 # DTB misses -system.cpu1.itb.accesses 5873745 # DTB accesses -system.cpu1.numCycles 234836749 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5797974 # ITB inst accesses +system.cpu1.itb.hits 5790816 # DTB hits +system.cpu1.itb.misses 7158 # DTB misses +system.cpu1.itb.accesses 5797974 # DTB accesses +system.cpu1.numCycles 235384601 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14958684 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46343438 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7417918 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4621171 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10240931 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2382000 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84846 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47705916 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1885 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 51796 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1300956 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.icacheStallCycles 14589178 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46084175 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7299586 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4554390 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10179964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2322435 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82610 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48394674 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1151 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1760 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 51069 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1300436 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5864138 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 361139 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3128 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 75991069 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.753206 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 5788667 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 351586 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2955 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76205210 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.749083 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.107109 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65758157 86.53% 86.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 661623 0.87% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 874095 1.15% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1155735 1.52% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1058337 1.39% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 579833 0.76% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1309635 1.72% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 379645 0.50% 94.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4214009 5.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66032287 86.65% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 647062 0.85% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 866139 1.14% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1142625 1.50% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1039142 1.36% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 573208 0.75% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1303078 1.71% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 377648 0.50% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4224021 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 75991069 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031588 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.197343 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15934805 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 48666188 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9324612 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 504366 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1558997 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1010894 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 88249 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54549781 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 295589 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1558997 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16808618 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19027959 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26571393 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8885070 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3136997 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 52018175 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13230 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 586421 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2033878 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219276243 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5446 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 374760 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6443032 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10070258 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6501681 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 951169 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1220754 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48367033 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1016747 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62006899 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 95474 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9693963 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24244292 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 257471 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 75991069 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.815976 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521890 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76205210 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.031011 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.195782 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15588837 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49317422 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9252055 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 521656 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1523167 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 986244 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 83403 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54452083 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 278013 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1523167 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16469267 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19674049 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26510190 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8818021 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3208448 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51956781 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13421 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 604219 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2079670 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 451 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54191440 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237039699 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 219510796 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4998 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40313487 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13877953 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 415796 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 370913 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6599828 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9995387 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6641278 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 924791 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1180275 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48354458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1004264 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62036555 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93414 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9463744 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23885542 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245582 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76205210 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814072 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.522064 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53638566 70.59% 70.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7003056 9.22% 79.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3617950 4.76% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3068918 4.04% 88.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6184871 8.14% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1401826 1.84% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 782382 1.03% 99.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 229717 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 63783 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53886192 70.71% 70.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6968313 9.14% 79.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3603419 4.73% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3067011 4.02% 88.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6180907 8.11% 96.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1416351 1.86% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 790440 1.04% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 228268 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64309 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 75991069 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76205210 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 31911 0.73% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4158175 94.76% 95.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 198234 4.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29954 0.68% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4154847 94.70% 95.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 202692 4.62% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 192098 0.31% 0.31% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29460264 47.51% 47.82% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45939 0.07% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26296905 42.41% 90.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6010767 9.69% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 197719 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29431617 47.44% 47.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46723 0.08% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 843 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26206761 42.24% 90.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6152865 9.92% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62006899 # Type of FU issued -system.cpu1.iq.rate 0.264043 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4388325 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070772 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204523942 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59086561 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43409940 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11938 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6483 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5383 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66196788 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6338 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 319760 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62036555 # Type of FU issued +system.cpu1.iq.rate 0.263554 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4387499 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070724 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204795562 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58831312 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43493604 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11047 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6062 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4926 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66220464 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5871 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 319800 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2083716 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3064 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15874 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 772589 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2036379 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2915 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15518 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 769053 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16902604 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332952 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16877667 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 333288 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1558997 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14375191 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 227377 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49504406 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10070258 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6501681 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 727587 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 51733 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9370 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15874 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 179251 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 141654 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 320905 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60955471 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25970384 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1051428 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1523167 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14985510 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 225691 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49480647 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96107 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9995387 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6641278 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 719443 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50947 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6143 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15518 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 171517 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135143 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 306660 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 61000330 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25886068 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1036225 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 120626 # number of nop insts executed -system.cpu1.iew.exec_refs 31928214 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5888736 # Number of branches executed -system.cpu1.iew.exec_stores 5957830 # Number of stores executed -system.cpu1.iew.exec_rate 0.259565 # Inst execution rate -system.cpu1.iew.wb_sent 60476945 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43415323 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24094324 # num instructions producing a value -system.cpu1.iew.wb_consumers 44023151 # num instructions consuming a value +system.cpu1.iew.exec_nop 121925 # number of nop insts executed +system.cpu1.iew.exec_refs 31986182 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5823905 # Number of branches executed +system.cpu1.iew.exec_stores 6100114 # Number of stores executed +system.cpu1.iew.exec_rate 0.259152 # Inst execution rate +system.cpu1.iew.wb_sent 60530443 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43498530 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24164344 # num instructions producing a value +system.cpu1.iew.wb_consumers 44485345 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.184874 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.547310 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.184798 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.543198 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9567264 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 759276 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 277731 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74432072 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.530472 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.515537 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9351616 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 758682 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 265186 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74682043 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.531552 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.520144 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60336914 81.06% 81.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6930423 9.31% 90.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1972494 2.65% 93.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1094851 1.47% 94.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1021489 1.37% 95.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524731 0.70% 96.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 707921 0.95% 97.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378966 0.51% 98.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1464283 1.97% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60574973 81.11% 81.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6925092 9.27% 90.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1956264 2.62% 93.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1088628 1.46% 94.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1022152 1.37% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 532797 0.71% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 718663 0.96% 97.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378466 0.51% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1485008 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74432072 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31082580 # Number of instructions committed -system.cpu1.commit.committedOps 39484127 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74682043 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31143561 # Number of instructions committed +system.cpu1.commit.committedOps 39697401 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13715634 # Number of memory references committed -system.cpu1.commit.loads 7986542 # Number of loads committed -system.cpu1.commit.membars 202747 # Number of memory barriers committed -system.cpu1.commit.branches 5103464 # Number of branches committed -system.cpu1.commit.fp_insts 5321 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34903456 # Number of committed integer instructions. -system.cpu1.commit.function_calls 500366 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1464283 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13831233 # Number of memory references committed +system.cpu1.commit.loads 7959008 # Number of loads committed +system.cpu1.commit.membars 199700 # Number of memory barriers committed +system.cpu1.commit.branches 5073252 # Number of branches committed +system.cpu1.commit.fp_insts 4858 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 35121772 # Number of committed integer instructions. +system.cpu1.commit.function_calls 494294 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1485008 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121076761 # The number of ROB reads -system.cpu1.rob.rob_writes 99705340 # The number of ROB writes -system.cpu1.timesIdled 873554 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 158845680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2319747272 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31000692 # Number of Instructions Simulated -system.cpu1.committedOps 39402239 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31000692 # Number of Instructions Simulated -system.cpu1.cpi 7.575210 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.575210 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132010 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132010 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276194442 # number of integer regfile reads -system.cpu1.int_regfile_writes 44861664 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22699 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19852 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15196533 # number of misc regfile reads -system.cpu1.misc_regfile_writes 431717 # number of misc regfile writes +system.cpu1.rob.rob_reads 121317994 # The number of ROB reads +system.cpu1.rob.rob_writes 99664484 # The number of ROB writes +system.cpu1.timesIdled 865516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159179391 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2318646728 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31060678 # Number of Instructions Simulated +system.cpu1.committedOps 39614518 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31060678 # Number of Instructions Simulated +system.cpu1.cpi 7.578218 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.578218 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.131957 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.131957 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276434717 # number of integer regfile reads +system.cpu1.int_regfile_writes 44854574 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22375 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19728 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15285924 # number of misc regfile reads +system.cpu1.misc_regfile_writes 428613 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1997,17 +2234,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1441896554007 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1441896554007 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518441783518 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518441783518 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83067 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 820046126..87a0dc109 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,143 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.630640 # Number of seconds simulated -sim_ticks 2630640106500 # Number of ticks simulated -final_tick 2630640106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.631415 # Number of seconds simulated +sim_ticks 2631415171500 # Number of ticks simulated +final_tick 2631415171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 544255 # Simulator instruction rate (inst/s) -host_op_rate 692557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23778611565 # Simulator tick rate (ticks/s) -host_mem_usage 394548 # Number of bytes of host memory used -host_seconds 110.63 # Real time elapsed on the host -sim_insts 60211209 # Number of instructions simulated -sim_ops 76617916 # Number of ops (including micro ops) simulated +host_inst_rate 471038 # Simulator instruction rate (inst/s) +host_op_rate 599389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20585916294 # Simulator tick rate (ticks/s) +host_mem_usage 424736 # Number of bytes of host memory used +host_seconds 127.83 # Real time elapsed on the host +sim_insts 60210883 # Number of instructions simulated +sim_ops 76617506 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 310496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4767440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 278752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4724944 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 393856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4293936 # Number of bytes read from this memory -system.physmem.bytes_read::total 134022176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 310496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 393856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1534960 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1481192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706776 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 425732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4336188 # Number of bytes read from this memory +system.physmem.bytes_read::total 134022064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 278752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704484 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1530592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1485560 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706648 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73861 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 383740 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 370298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811704 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47234229 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 67782 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690904 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 382648 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 371390 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811702 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47220316 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 118031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1812274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 105932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1795590 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 149719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1632278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50946603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 118031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 149719 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 583493 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563054 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2549484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47234229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 161788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1647854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50931554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 105932 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 161788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402476 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 581661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 564548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2548685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47220316 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 118031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2395767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 105932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2377252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 149719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2195332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53496087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690887 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 811704 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15690887 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 811704 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 1004216768 # Total number of bytes read from memory -system.physmem.bytesWritten 51949056 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 134022176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6706776 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 980224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 980420 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 979555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 980165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6627 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6678 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7054 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7014 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6836 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6624 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2630635687000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6680 # Categorize read packet sizes -system.physmem.readPktSize::3 15532032 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152175 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754038 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57666 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1132703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1005041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3836885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2878586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2878042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2847020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 44009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 10 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 161788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2212402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53480239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690904 # Number of read requests accepted +system.physmem.writeReqs 811702 # Number of write requests accepted +system.physmem.readBursts 15690904 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811702 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004216000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6838848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134022064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 704845 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 980392 # Per bank write bursts +system.physmem.perBankRdBursts::1 980205 # Per bank write bursts +system.physmem.perBankRdBursts::2 980222 # Per bank write bursts +system.physmem.perBankRdBursts::3 980428 # Per bank write bursts +system.physmem.perBankRdBursts::4 986950 # Per bank write bursts +system.physmem.perBankRdBursts::5 980709 # Per bank write bursts +system.physmem.perBankRdBursts::6 980611 # Per bank write bursts +system.physmem.perBankRdBursts::7 980420 # Per bank write bursts +system.physmem.perBankRdBursts::8 980615 # Per bank write bursts +system.physmem.perBankRdBursts::9 980431 # Per bank write bursts +system.physmem.perBankRdBursts::10 979815 # Per bank write bursts +system.physmem.perBankRdBursts::11 979555 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts +system.physmem.perBankRdBursts::13 980095 # Per bank write bursts +system.physmem.perBankRdBursts::14 980165 # Per bank write bursts +system.physmem.perBankRdBursts::15 980109 # Per bank write bursts +system.physmem.perBankWrBursts::0 6734 # Per bank write bursts +system.physmem.perBankWrBursts::1 6600 # Per bank write bursts +system.physmem.perBankWrBursts::2 6608 # Per bank write bursts +system.physmem.perBankWrBursts::3 6671 # Per bank write bursts +system.physmem.perBankWrBursts::4 6747 # Per bank write bursts +system.physmem.perBankWrBursts::5 7057 # Per bank write bursts +system.physmem.perBankWrBursts::6 7034 # Per bank write bursts +system.physmem.perBankWrBursts::7 6884 # Per bank write bursts +system.physmem.perBankWrBursts::8 7000 # Per bank write bursts +system.physmem.perBankWrBursts::9 6825 # Per bank write bursts +system.physmem.perBankWrBursts::10 6323 # Per bank write bursts +system.physmem.perBankWrBursts::11 6129 # Per bank write bursts +system.physmem.perBankWrBursts::12 6612 # Per bank write bursts +system.physmem.perBankWrBursts::13 6395 # Per bank write bursts +system.physmem.perBankWrBursts::14 6622 # Per bank write bursts +system.physmem.perBankWrBursts::15 6616 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2631410752000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6700 # Read request sizes (log2) +system.physmem.readPktSize::3 15532032 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754038 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 57664 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1280991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1124435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1124568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3790382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2700913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2699740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2717442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,29 +155,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -185,193 +187,315 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 26627.977877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2487.931344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31806.056461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5445 14.34% 14.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3318 8.74% 23.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2184 5.75% 28.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1677 4.42% 33.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1130 2.98% 36.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1067 2.81% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 805 2.12% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 712 1.88% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 588 1.55% 44.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 469 1.24% 45.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 450 1.19% 47.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 409 1.08% 48.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 266 0.70% 48.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 255 0.67% 49.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 222 0.58% 50.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 208 0.55% 50.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 140 0.37% 50.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 130 0.34% 51.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 95 0.25% 51.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 109 0.29% 51.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 83 0.22% 52.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 158 0.42% 52.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 757 1.99% 54.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 208 0.55% 55.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 141 0.37% 55.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 116 0.31% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 79 0.21% 55.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 86 0.23% 56.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 52 0.14% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 50 0.13% 56.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 43 0.11% 56.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 55 0.14% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 50 0.13% 56.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 19 0.05% 56.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 17 0.04% 56.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 20 0.05% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 17 0.04% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 12 0.03% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 10 0.03% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 4 0.01% 57.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 9 0.02% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 14 0.04% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 6 0.02% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 11 0.03% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 5 0.01% 57.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 7 0.02% 57.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 8 0.02% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 10 0.03% 57.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 14 0.04% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 5 0.01% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 7 0.02% 57.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 2 0.01% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 8 0.02% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 5 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 2 0.01% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 2 0.01% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 7 0.02% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 2 0.01% 57.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 8 0.02% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 1 0.00% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 5 0.01% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 1 0.00% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 4 0.01% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 3 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 8 0.02% 57.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 3 0.01% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 2 0.01% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 2 0.01% 57.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 3 0.01% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 5 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 6 0.02% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 5 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 5 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 309 0.81% 59.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 22 0.06% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 151 0.40% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 180 0.47% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8703 3 0.01% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8831 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 2 0.01% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 2 0.01% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 2 0.01% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 1 0.00% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 7 0.02% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 12 0.03% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55872-55935 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 15142 39.88% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67392-67455 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37970 # Bytes accessed per row activation -system.physmem.totQLat 300039544000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 394721941500 # Sum of mem lat for all requests -system.physmem.totBusLat 78454290000 # Total cycles spent in databus access -system.physmem.totBankLat 16228107500 # Total cycles spent in bank access -system.physmem.avgQLat 19121.93 # Average queueing delay per request -system.physmem.avgBankLat 1034.24 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25156.17 # Average memory access latency -system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.25 # Average write queue length over time -system.physmem.readRowHits 15666199 # Number of row buffer hits during reads -system.physmem.writeRowHits 93719 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.55 # Row buffer hit rate for writes -system.physmem.avgGap 159407.43 # Average gap between requests +system.physmem.bytesPerActivate::samples 90271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11200.204894 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1031.239605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16762.903946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23441 25.97% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14726 16.31% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2829 3.13% 45.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2153 2.39% 47.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1359 1.51% 49.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1176 1.30% 50.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 955 1.06% 51.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1145 1.27% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 612 0.68% 53.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 559 0.62% 54.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 621 0.69% 54.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 534 0.59% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 322 0.36% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 268 0.30% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 218 0.24% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 586 0.65% 57.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 164 0.18% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 127 0.14% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 130 0.14% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 257 0.28% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 89 0.10% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 142 0.16% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 48 0.05% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 45 0.05% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 41 0.05% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 166 0.18% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 19 0.02% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 18 0.02% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 150 0.17% 61.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 341 0.38% 61.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 19 0.02% 61.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 17 0.02% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 76 0.08% 61.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 15 0.02% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 8 0.01% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 16 0.02% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 76 0.08% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 11 0.01% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 6 0.01% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 22 0.02% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 3 0.00% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 382 0.42% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 6 0.01% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 146 0.16% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 2 0.00% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 137 0.15% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 197 0.22% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 7 0.01% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 7 0.01% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 32 0.04% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 137 0.15% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 6 0.01% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 2 0.00% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 6 0.01% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 337 0.37% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 1 0.00% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 1 0.00% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 130 0.14% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 1 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 71 0.08% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 129 0.14% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 75 0.08% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 261 0.29% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 1 0.00% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 62 0.07% 64.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 15 0.02% 64.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 204 0.23% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 122 0.14% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 133 0.15% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 389 0.43% 65.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 64 0.07% 65.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 120 0.13% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 252 0.28% 65.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 133 0.15% 65.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 13 0.01% 66.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 68 0.08% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 520 0.58% 66.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 68 0.08% 66.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 11 0.01% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 136 0.15% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 250 0.28% 67.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 121 0.13% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 68 0.08% 67.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 388 0.43% 67.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 132 0.15% 68.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 121 0.13% 68.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10823 2 0.00% 68.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 55 0.06% 68.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 259 0.29% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 71 0.08% 68.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 69 0.08% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.14% 68.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 328 0.36% 69.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 133 0.15% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 193 0.21% 69.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 136 0.15% 69.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 377 0.42% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 11 0.01% 70.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 64 0.07% 70.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 322 0.36% 70.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 132 0.15% 70.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 68 0.08% 70.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 129 0.14% 70.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 391 0.43% 71.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 67 0.07% 71.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 129 0.14% 71.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 641 0.71% 72.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 136 0.15% 72.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 66 0.07% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 391 0.43% 73.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 128 0.14% 73.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 67 0.07% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 131 0.15% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 320 0.35% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 67 0.07% 73.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 67 0.07% 73.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 13 0.01% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 1 0.00% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 376 0.42% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 137 0.15% 74.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 192 0.21% 74.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 131 0.15% 74.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 326 0.36% 75.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 124 0.14% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 68 0.08% 75.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21056-21063 1 0.00% 75.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 71 0.08% 75.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 259 0.29% 75.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 56 0.06% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 120 0.13% 75.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 134 0.15% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 388 0.43% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 64 0.07% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 67 0.07% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 121 0.13% 76.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 253 0.28% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 133 0.15% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 10 0.01% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 70 0.08% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 519 0.57% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 69 0.08% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 10 0.01% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 133 0.15% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 251 0.28% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 120 0.13% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 70 0.08% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 64 0.07% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 387 0.43% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 134 0.15% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 119 0.13% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 56 0.06% 79.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 259 0.29% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 71 0.08% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 68 0.08% 79.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 125 0.14% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 325 0.36% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 133 0.15% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 192 0.21% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 377 0.42% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 11 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 65 0.07% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 69 0.08% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 321 0.36% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 130 0.14% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 67 0.07% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 128 0.14% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 390 0.43% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 1 0.00% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 67 0.07% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 130 0.14% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 640 0.71% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 132 0.15% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 70 0.08% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 1 0.00% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 389 0.43% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 128 0.14% 84.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 67 0.07% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 130 0.14% 84.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 318 0.35% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.07% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 10 0.01% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 377 0.42% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 136 0.15% 85.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 192 0.21% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 132 0.15% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 324 0.36% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 125 0.14% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 68 0.08% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 71 0.08% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 259 0.29% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 56 0.06% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 119 0.13% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 134 0.15% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 387 0.43% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 64 0.07% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 69 0.08% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 119 0.13% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 251 0.28% 88.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 133 0.15% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 9 0.01% 88.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 68 0.08% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 518 0.57% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 10 0.01% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 133 0.15% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 252 0.28% 89.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 120 0.13% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 67 0.07% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 64 0.07% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 388 0.43% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 134 0.15% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 119 0.13% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 56 0.06% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 260 0.29% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 71 0.08% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 69 0.08% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 124 0.14% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 325 0.36% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 191 0.21% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 137 0.15% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 375 0.42% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 11 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 66 0.07% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 66 0.07% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 319 0.35% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 133 0.15% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 129 0.14% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 390 0.43% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 67 0.07% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 131 0.15% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5359 5.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90271 # Bytes accessed per row activation +system.physmem.totQLat 377292466250 # Total ticks spent queuing +system.physmem.totMemAccLat 474547986250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454375000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18801145000 # Total ticks spent accessing banks +system.physmem.avgQLat 24045.34 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1198.22 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30243.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing +system.physmem.readRowHits 15616441 # Number of row buffer hits during reads +system.physmem.writeRowHits 91020 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.18 # Row buffer hit rate for writes +system.physmem.avgGap 159454.26 # Average gap between requests +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -384,249 +508,249 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54407704 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743613 # Transaction distribution -system.membus.trans_dist::ReadResp 16743613 # Transaction distribution +system.membus.throughput 54391586 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743633 # Transaction distribution +system.membus.trans_dist::ReadResp 16743633 # Transaction distribution system.membus.trans_dist::WriteReq 763392 # Transaction distribution system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57666 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution -system.membus.trans_dist::ReadExReq 131350 # Transaction distribution -system.membus.trans_dist::ReadExResp 131350 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57664 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution +system.membus.trans_dist::ReadExReq 131346 # Transaction distribution +system.membus.trans_dist::ReadExResp 131346 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892496 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279356 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279376 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343420 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343440 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870833 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870589 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143127089 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143127089 # Total data (bytes) +system.membus.tot_pkt_size::total 143126845 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126845 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1209125000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1220589500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3743000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3747000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18109707000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18118484000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4946568726 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4951896724 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35058992750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35075499000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62061 # number of replacements -system.l2c.tags.tagsinuse 51615.718916 # Cycle average of tags in use -system.l2c.tags.total_refs 1699022 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127446 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.331309 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2575798778500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38215.031353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2892.274749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3021.606158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4129.656737 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3357.149045 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583115 # Average percentage of cache occupancy +system.l2c.tags.replacements 62057 # number of replacements +system.l2c.tags.tagsinuse 51615.015118 # Cycle average of tags in use +system.l2c.tags.total_refs 1699237 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127445 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.333101 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2576505750500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38217.986822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2603.292629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3037.110347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4418.327235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3338.297198 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583160 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.044133 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046106 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.039723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046343 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.051226 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787593 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9999 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 436599 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 185177 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9919 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3623 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 407829 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 185133 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241869 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596358 # number of Writeback hits -system.l2c.Writeback_hits::total 596358 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.067418 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050938 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787583 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9914 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3649 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 415311 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183212 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3517 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 429187 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187142 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241940 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596380 # number of Writeback hits +system.l2c.Writeback_hits::total 596380 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 59730 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54783 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114513 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9999 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 436599 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 244907 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9919 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3623 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 407829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239916 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356382 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9999 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3590 # number of overall hits -system.l2c.overall_hits::cpu0.inst 436599 # number of overall hits -system.l2c.overall_hits::cpu0.data 244907 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9919 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3623 # number of overall hits -system.l2c.overall_hits::cpu1.inst 407829 # number of overall hits -system.l2c.overall_hits::cpu1.data 239916 # number of overall hits -system.l2c.overall_hits::total 1356382 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 56696 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57849 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114545 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3649 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 415311 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 239908 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10008 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3517 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 429187 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 244991 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356485 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9914 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3649 # number of overall hits +system.l2c.overall_hits::cpu0.inst 415311 # number of overall hits +system.l2c.overall_hits::cpu0.data 239908 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10008 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3517 # number of overall hits +system.l2c.overall_hits::cpu1.inst 429187 # number of overall hits +system.l2c.overall_hits::cpu1.data 244991 # number of overall hits +system.l2c.overall_hits::total 1356485 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4438 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5378 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3942 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5224 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6154 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4852 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20825 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1446 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1435 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 63028 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132991 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6651 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5006 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20826 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1375 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1512 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2887 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 69398 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 63578 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4438 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75341 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 3942 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74622 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6154 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 67880 # number of demand (read+write) misses -system.l2c.demand_misses::total 153816 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6651 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 68584 # number of demand (read+write) misses +system.l2c.demand_misses::total 153802 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 4438 # number of overall misses -system.l2c.overall_misses::cpu0.data 75341 # number of overall misses +system.l2c.overall_misses::cpu0.inst 3942 # number of overall misses +system.l2c.overall_misses::cpu0.data 74622 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6154 # number of overall misses -system.l2c.overall_misses::cpu1.data 67880 # number of overall misses -system.l2c.overall_misses::total 153816 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 307218750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 368704500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 6651 # number of overall misses +system.l2c.overall_misses::cpu1.data 68584 # number of overall misses +system.l2c.overall_misses::total 153802 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 279121500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 387849000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 431930250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 347894250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1455959500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 232990 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4479114898 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4038724211 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8517839109 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 307218750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4847819398 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 474818500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 382257500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1524285750 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 256989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 208991 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4923800203 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4505788417 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9429588620 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 279121500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5311649203 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 431930250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4386618461 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9973798609 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 307218750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4847819398 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 474818500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4888045917 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10953874370 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 279121500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5311649203 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 431930250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4386618461 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9973798609 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9999 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3592 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 441037 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 190555 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9920 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 413983 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 189985 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262694 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596358 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596358 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1464 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1443 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2907 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 129693 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 117811 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247504 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9999 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3592 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 441037 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 320248 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9920 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3623 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 413983 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 307796 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1510198 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9999 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3592 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 441037 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 320248 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9920 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3623 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 413983 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 307796 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1510198 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000557 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.010063 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028223 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014865 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025539 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016493 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987705 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.994456 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991056 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.539451 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.534992 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537329 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000557 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010063 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.235258 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014865 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.220536 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101852 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000557 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010063 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.235258 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014865 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.220536 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101852 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69224.594412 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 68557.921160 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu1.inst 474818500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4888045917 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10953874370 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9914 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 419253 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 188436 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10009 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3517 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 435838 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 192148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1262766 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596380 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596380 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1389 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1524 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2913 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 126094 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 121427 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247521 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9914 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3651 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 419253 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314530 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10009 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3517 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 435838 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 313575 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1510287 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9914 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3651 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 419253 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 314530 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10009 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3517 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 435838 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 313575 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1510287 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000548 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.009402 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027723 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.015260 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.026053 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016492 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989921 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992126 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991074 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.550367 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.523590 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537231 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000548 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009402 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.237249 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.015260 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.218716 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101836 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000548 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009402 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.237249 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.015260 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.218716 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101836 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70807.077626 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74243.683002 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70186.910952 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 71701.205688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 69914.021609 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 160.781466 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 162.362369 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 161.568900 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 64021.195460 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64078.254284 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 64048.237166 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 69224.594412 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 64345.036541 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71390.542776 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 76359.868158 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73191.479401 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 186.901091 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 138.221561 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 161.406304 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70950.174400 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70870.244692 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 70911.958699 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 70807.077626 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 71180.740304 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70186.910952 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 64623.135843 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64842.400069 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 69224.594412 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 64345.036541 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71390.542776 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71270.936618 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71220.623724 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 70807.077626 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 71180.740304 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70186.910952 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 64623.135843 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64842.400069 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71390.542776 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71270.936618 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71220.623724 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,129 +759,132 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57666 # number of writebacks -system.l2c.writebacks::total 57666 # number of writebacks +system.l2c.writebacks::writebacks 57664 # number of writebacks +system.l2c.writebacks::total 57664 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4438 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5378 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 3942 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5224 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6154 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4852 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20825 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1446 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1435 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2881 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 69963 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 63028 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 132991 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6651 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 5006 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20826 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1375 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1512 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2887 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 69398 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 63578 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 132976 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 4438 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75341 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 3942 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 74622 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6154 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 67880 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153816 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6651 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 68584 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153802 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 4438 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75341 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 3942 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 74622 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6154 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 67880 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153816 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 251180750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 300683500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 6651 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 68584 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153802 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229630000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 322854500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 354229750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 286200750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1192468500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14461446 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14352435 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28813881 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3602203602 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3248593789 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6850797391 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 251180750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3902887102 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 391301000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 319831000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1263817750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13751375 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15121512 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28872887 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4053929797 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3708851583 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7762781380 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 229630000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4376784297 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 354229750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3534794539 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8043265891 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 251180750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3902887102 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 391301000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4028682583 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9026599130 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 229630000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4376784297 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 354229750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3534794539 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8043265891 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 322980250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84062460250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82598359000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166983799500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8379652001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8320086501 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16699738502 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 322980250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92442112251 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90918445501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183683538002 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028223 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025539 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016493 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987705 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994456 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991056 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.539451 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534992 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537329 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.235258 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.220536 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101852 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.235258 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.220536 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101852 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 55909.910747 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu1.inst 391301000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4028682583 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9026599130 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343871250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83402251750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 842500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83269942750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167016908250 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8431436509 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8268193000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16699629509 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343871250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91833688259 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 842500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91538135750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183716537759 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027723 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026053 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016492 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989921 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992126 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991074 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.550367 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.523590 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537231 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.237249 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.218716 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101836 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.237249 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.218716 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101836 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61802.163093 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58986.139736 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57261.392557 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63889.532561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60684.612984 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.696864 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.347102 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51487.266155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51542.073190 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51513.240678 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58415.657469 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58335.455393 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58377.311545 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -765,6 +892,7 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate @@ -774,45 +902,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52764048 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471787 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471787 # Transaction distribution +system.toL2Bus.throughput 52751818 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471631 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471631 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596358 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247504 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247504 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1724904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753314 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549201 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54747764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83776253 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79676 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138632553 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138632553 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170668 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808102000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596380 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2913 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2913 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247521 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247521 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725079 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753474 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549204 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54752376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83781573 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138642313 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138642313 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169620 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808134500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865742750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865505750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4428115774 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420696776 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13092500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12940000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30757250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30620250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48142902 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution +system.iobus.throughput 48128720 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715358 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715358 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -834,12 +962,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447050 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -861,14 +989,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646649 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646645 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646645 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -914,141 +1042,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374819000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42581193250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42584048000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7542817 # DTB read hits -system.cpu0.dtb.read_misses 7082 # DTB read misses -system.cpu0.dtb.write_hits 5717425 # DTB write hits -system.cpu0.dtb.write_misses 1778 # DTB write misses +system.cpu0.dtb.read_hits 7352406 # DTB read hits +system.cpu0.dtb.read_misses 6766 # DTB read misses +system.cpu0.dtb.write_hits 5599485 # DTB write hits +system.cpu0.dtb.write_misses 1847 # DTB write misses system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6542 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6337 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 149 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 131 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7549899 # DTB read accesses -system.cpu0.dtb.write_accesses 5719203 # DTB write accesses +system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7359172 # DTB read accesses +system.cpu0.dtb.write_accesses 5601332 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13260242 # DTB hits -system.cpu0.dtb.misses 8860 # DTB misses -system.cpu0.dtb.accesses 13269102 # DTB accesses -system.cpu0.itb.inst_hits 30610477 # ITB inst hits -system.cpu0.itb.inst_misses 3712 # ITB inst misses +system.cpu0.dtb.hits 12951891 # DTB hits +system.cpu0.dtb.misses 8613 # DTB misses +system.cpu0.dtb.accesses 12960504 # DTB accesses +system.cpu0.itb.inst_hits 30170189 # ITB inst hits +system.cpu0.itb.inst_misses 3579 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2775 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30614189 # ITB inst accesses -system.cpu0.itb.hits 30610477 # DTB hits -system.cpu0.itb.misses 3712 # DTB misses -system.cpu0.itb.accesses 30614189 # DTB accesses -system.cpu0.numCycles 2629428479 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30173768 # ITB inst accesses +system.cpu0.itb.hits 30170189 # DTB hits +system.cpu0.itb.misses 3579 # DTB misses +system.cpu0.itb.accesses 30173768 # DTB accesses +system.cpu0.numCycles 2629696361 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30009354 # Number of instructions committed -system.cpu0.committedOps 38372334 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34511671 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses -system.cpu0.num_func_calls 1080838 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3989390 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34511671 # number of integer instructions -system.cpu0.num_fp_insts 5157 # number of float instructions -system.cpu0.num_int_register_reads 198034256 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36980567 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written -system.cpu0.num_mem_refs 13842126 # number of memory refs -system.cpu0.num_load_insts 7871888 # Number of load instructions -system.cpu0.num_store_insts 5970238 # Number of store instructions -system.cpu0.num_idle_cycles 2283161569.446249 # Number of idle cycles -system.cpu0.num_busy_cycles 346266909.553751 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131689 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868311 # Percentage of idle cycles +system.cpu0.committedInsts 29597158 # Number of instructions committed +system.cpu0.committedOps 37762240 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33970200 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses +system.cpu0.num_func_calls 1050225 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3920547 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33970200 # number of integer instructions +system.cpu0.num_fp_insts 4584 # number of float instructions +system.cpu0.num_int_register_reads 194623734 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36521551 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3225 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1362 # number of times the floating registers were written +system.cpu0.num_mem_refs 13522491 # number of memory refs +system.cpu0.num_load_insts 7673972 # Number of load instructions +system.cpu0.num_store_insts 5848519 # Number of store instructions +system.cpu0.num_idle_cycles 2290697984.129271 # Number of idle cycles +system.cpu0.num_busy_cycles 338998376.870729 # Number of busy cycles +system.cpu0.not_idle_fraction 0.128912 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.871088 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856130 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.884273 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60648659 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856642 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.798139 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19947189250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.188035 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.696238 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410524 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.587297 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 30168630 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30480029 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60648659 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30168630 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30480029 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60648659 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30168630 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30480029 # number of overall hits -system.cpu0.icache.overall_hits::total 60648659 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 441847 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 414795 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856642 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 441847 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 414795 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856642 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 441847 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 414795 # number of overall misses -system.cpu0.icache.overall_misses::total 856642 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6019417250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5775014750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11794432000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6019417250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5775014750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11794432000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6019417250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5775014750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11794432000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30610477 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30894824 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61505301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30610477 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30894824 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61505301 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30610477 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30894824 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61505301 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014435 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013426 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014435 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013426 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014435 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013426 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13623.306823 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13922.575610 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13768.215894 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13623.306823 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13922.575610 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13768.215894 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13623.306823 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13922.575610 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13768.215894 # average overall miss latency +system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 856199 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.856725 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60648231 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856711 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.791937 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20135568250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 208.641443 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 302.215282 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.407503 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.590264 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997767 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29750188 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30898043 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60648231 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29750188 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30898043 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60648231 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29750188 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30898043 # number of overall hits +system.cpu0.icache.overall_hits::total 60648231 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 420001 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 436711 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856712 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 420001 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 436711 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856712 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 420001 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 436711 # number of overall misses +system.cpu0.icache.overall_misses::total 856712 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5711192500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6097938000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11809130500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5711192500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6097938000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11809130500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5711192500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6097938000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11809130500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30170189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 31334754 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61504943 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30170189 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 31334754 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61504943 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30170189 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 31334754 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61504943 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013921 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013937 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013921 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013937 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013921 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013937 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.045005 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13963.325861 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13784.247799 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13784.247799 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13784.247799 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1057,158 +1185,162 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 441847 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 414795 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856642 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 441847 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 414795 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856642 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 441847 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 414795 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856642 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5133544750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4942408250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10075953000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5133544750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4942408250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10075953000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5133544750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4942408250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10075953000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 414413750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11762.151517 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 420001 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 436711 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856712 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 420001 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 436711 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856712 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 420001 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 436711 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856712 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869726500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5221934000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10091660500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869726500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5221934000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10091660500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869726500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5221934000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10091660500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435321250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.525091 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627532 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.881676 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23660522 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628044 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.673351 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 640880250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.734555 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 329.147121 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.356903 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642865 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999769 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6634061 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6564802 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13198863 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5075609 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4899184 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974793 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 120623 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 115578 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236201 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126785 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120973 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247758 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11709670 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11463986 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23173656 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11709670 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11463986 # number of overall hits -system.cpu0.dcache.overall_hits::total 23173656 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 184394 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 184588 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 368982 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 131157 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 119254 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250411 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6161 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5397 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11558 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 315551 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 303842 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619393 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 315551 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 303842 # number of overall misses -system.cpu0.dcache.overall_misses::total 619393 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2725468500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2705402500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5430871000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5537493548 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5008087224 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10545580772 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82157000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77679750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 159836750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8262962048 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 7713489724 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15976451772 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8262962048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 7713489724 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15976451772 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6818455 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6749390 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13567845 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206766 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5018438 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225204 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126784 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 120975 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247759 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126785 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120973 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247758 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12025221 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11767828 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793049 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12025221 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11767828 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793049 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027043 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027349 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027195 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025190 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023763 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048594 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046650 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026241 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025820 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026241 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025820 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14780.678872 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14656.437580 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.525565 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.343161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41995.129924 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42113.089169 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13335.010550 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14393.135075 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13829.101056 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25793.723487 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25793.723487 # average overall miss latency +system.cpu0.dcache.tags.replacements 627593 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.877442 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23660330 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628105 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.669386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.884282 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 328.993161 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357196 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642565 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6452957 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6745780 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13198737 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4964348 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 5010385 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974733 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118524 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117664 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236188 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124634 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123125 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247759 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11417305 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11756165 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23173470 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11417305 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11756165 # number of overall hits +system.cpu0.dcache.overall_hits::total 23173470 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 182326 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 186686 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 369012 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 127483 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 122951 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250434 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6110 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5462 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11572 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 309809 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 309637 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 619446 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 309809 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 309637 # number of overall misses +system.cpu0.dcache.overall_misses::total 619446 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2717177250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2764634500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5481811750 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5932563172 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5512471095 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11445034267 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81881250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 78503500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 160384750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8649740422 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 8277105595 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16926846017 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8649740422 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 8277105595 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16926846017 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6635283 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6932466 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13567749 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5091831 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5133336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10225167 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124634 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123126 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247760 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124634 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123125 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247759 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11727114 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12065802 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23792916 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11727114 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12065802 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23792916 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027478 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026929 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027198 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025037 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023951 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024492 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049024 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044361 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046706 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026418 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025662 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025662 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14902.851212 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14809.008174 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14855.375299 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46536.112046 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44834.699148 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45700.800478 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13401.186579 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14372.665690 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13859.726063 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27325.781451 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27325.781451 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1217,77 +1349,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596358 # number of writebacks -system.cpu0.dcache.writebacks::total 596358 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184394 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184588 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 368982 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131157 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250411 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6161 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5397 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11558 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 315551 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 303842 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619393 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 315551 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 303842 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619393 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2354074500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333925500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4688000000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5241357452 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4739135776 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9980493228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69822000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66822250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136644250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7595431952 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7073061276 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14668493228 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7595431952 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7073061276 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14668493228 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91831657250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90223318750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182054976000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13223525999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13011841499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235367498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105055183249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103235160249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290343498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027043 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027349 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023763 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048594 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044613 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046650 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12766.546092 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12643.971981 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.226813 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39962.468278 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.847519 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39856.448910 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11332.900503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12381.369279 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.482263 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596380 # number of writebacks +system.cpu0.dcache.writebacks::total 596380 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182326 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186686 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369012 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127483 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 122951 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250434 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6110 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309809 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 309637 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619446 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309809 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 309637 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619446 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2351238750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2390198500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741437250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5650406828 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5242308905 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10892715733 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69656750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67531500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137188250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8001645578 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7632507405 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15634152983 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8001645578 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7632507405 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15634152983 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91105263250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90961118500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182066381750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13264461491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12970911500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235372991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104369724741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103932030000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208301754741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027478 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026929 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027198 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025037 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023951 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049024 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044361 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046706 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12895.795169 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.308764 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12849.005588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44322.826008 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42637.383226 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43495.354996 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11400.450082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12363.877700 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11855.189250 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1300,68 +1432,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7456887 # DTB read hits -system.cpu1.dtb.read_misses 7096 # DTB read misses -system.cpu1.dtb.write_hits 5515190 # DTB write hits -system.cpu1.dtb.write_misses 1853 # DTB write misses -system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7647205 # DTB read hits +system.cpu1.dtb.read_misses 7298 # DTB read misses +system.cpu1.dtb.write_hits 5633094 # DTB write hits +system.cpu1.dtb.write_misses 1843 # DTB write misses +system.cpu1.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6662 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6730 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7463983 # DTB read accesses -system.cpu1.dtb.write_accesses 5517043 # DTB write accesses +system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7654503 # DTB read accesses +system.cpu1.dtb.write_accesses 5634937 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12972077 # DTB hits -system.cpu1.dtb.misses 8949 # DTB misses -system.cpu1.dtb.accesses 12981026 # DTB accesses -system.cpu1.itb.inst_hits 30894824 # ITB inst hits -system.cpu1.itb.inst_misses 3669 # ITB inst misses +system.cpu1.dtb.hits 13280299 # DTB hits +system.cpu1.dtb.misses 9141 # DTB misses +system.cpu1.dtb.accesses 13289440 # DTB accesses +system.cpu1.itb.inst_hits 31334771 # ITB inst hits +system.cpu1.itb.inst_misses 3728 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2813 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2858 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30898493 # ITB inst accesses -system.cpu1.itb.hits 30894824 # DTB hits -system.cpu1.itb.misses 3669 # DTB misses -system.cpu1.itb.accesses 30898493 # DTB accesses -system.cpu1.numCycles 2631851734 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31338499 # ITB inst accesses +system.cpu1.itb.hits 31334771 # DTB hits +system.cpu1.itb.misses 3728 # DTB misses +system.cpu1.itb.accesses 31338499 # DTB accesses +system.cpu1.numCycles 2633133982 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30201855 # Number of instructions committed -system.cpu1.committedOps 38245582 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34372038 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses -system.cpu1.num_func_calls 1059508 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3959978 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34372038 # number of integer instructions -system.cpu1.num_fp_insts 5112 # number of float instructions -system.cpu1.num_int_register_reads 196814123 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37215593 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written -system.cpu1.num_mem_refs 13557754 # number of memory refs -system.cpu1.num_load_insts 7792008 # Number of load instructions -system.cpu1.num_store_insts 5765746 # Number of store instructions -system.cpu1.num_idle_cycles 2293589601.195636 # Number of idle cycles -system.cpu1.num_busy_cycles 338262132.804364 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128526 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871474 # Percentage of idle cycles +system.cpu1.committedInsts 30613725 # Number of instructions committed +system.cpu1.committedOps 38855266 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34913201 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses +system.cpu1.num_func_calls 1090107 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4028756 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34913201 # number of integer instructions +system.cpu1.num_fp_insts 5685 # number of float instructions +system.cpu1.num_int_register_reads 200222637 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37674133 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4268 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written +system.cpu1.num_mem_refs 13877284 # number of memory refs +system.cpu1.num_load_insts 7989860 # Number of load instructions +system.cpu1.num_store_insts 5887424 # Number of store instructions +system.cpu1.num_idle_cycles 2288817928.029144 # Number of idle cycles +system.cpu1.num_busy_cycles 344316053.970855 # Number of busy cycles +system.cpu1.not_idle_fraction 0.130763 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.869237 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1378,10 +1510,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1478384126250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1478384126250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557205456000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557205456000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index ded25c3bb..8fd17006a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,133 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.149802 # Number of seconds simulated -sim_ticks 5149801602000 # Number of ticks simulated -final_tick 5149801602000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133932 # Number of seconds simulated +sim_ticks 5133932129000 # Number of ticks simulated +final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149544 # Simulator instruction rate (inst/s) -host_op_rate 295611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1888705545 # Simulator tick rate (ticks/s) -host_mem_usage 733444 # Number of bytes of host memory used -host_seconds 2726.63 # Real time elapsed on the host -sim_insts 407752265 # Number of instructions simulated -sim_ops 806021401 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464448 # Number of bytes read from this memory +host_inst_rate 157497 # Simulator instruction rate (inst/s) +host_op_rate 311329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1982921852 # Simulator tick rate (ticks/s) +host_mem_usage 759792 # Number of bytes of host memory used +host_seconds 2589.07 # Real time elapsed on the host +sim_insts 407772261 # Number of instructions simulated +sim_ops 806052921 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1029696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10712000 # Number of bytes read from this memory -system.physmem.bytes_read::total 14210368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1029696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1029696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9492864 # Number of bytes written to this memory -system.physmem.bytes_written::total 9492864 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38507 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory +system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory +system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167375 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222037 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148326 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148326 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 478552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 758 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 199949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2080080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2759401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1843346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1843346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1843346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 478552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2080080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4602747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222037 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 148326 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 222037 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 148326 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 14210368 # Total number of bytes read from memory -system.physmem.bytesWritten 9492864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14210368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9492864 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 1678 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 14693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 13767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 13963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13415 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13462 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13512 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14150 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 13288 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 9534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 9830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 9200 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9484 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 9093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9396 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8748 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9077 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 10300 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8716 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry -system.physmem.totGap 5149801548000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 222037 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 148326 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 173642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222430 # Number of read requests accepted +system.physmem.writeReqs 148587 # Number of write requests accepted +system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue +system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14853 # Per bank write bursts +system.physmem.perBankRdBursts::1 13635 # Per bank write bursts +system.physmem.perBankRdBursts::2 14415 # Per bank write bursts +system.physmem.perBankRdBursts::3 13770 # Per bank write bursts +system.physmem.perBankRdBursts::4 14136 # Per bank write bursts +system.physmem.perBankRdBursts::5 13341 # Per bank write bursts +system.physmem.perBankRdBursts::6 13755 # Per bank write bursts +system.physmem.perBankRdBursts::7 13953 # Per bank write bursts +system.physmem.perBankRdBursts::8 13590 # Per bank write bursts +system.physmem.perBankRdBursts::9 13369 # Per bank write bursts +system.physmem.perBankRdBursts::10 13469 # Per bank write bursts +system.physmem.perBankRdBursts::11 13962 # Per bank write bursts +system.physmem.perBankRdBursts::12 14252 # Per bank write bursts +system.physmem.perBankRdBursts::13 14454 # Per bank write bursts +system.physmem.perBankRdBursts::14 13844 # Per bank write bursts +system.physmem.perBankRdBursts::15 13571 # Per bank write bursts +system.physmem.perBankWrBursts::0 10225 # Per bank write bursts +system.physmem.perBankWrBursts::1 9089 # Per bank write bursts +system.physmem.perBankWrBursts::2 9605 # Per bank write bursts +system.physmem.perBankWrBursts::3 9165 # Per bank write bursts +system.physmem.perBankWrBursts::4 9475 # Per bank write bursts +system.physmem.perBankWrBursts::5 8866 # Per bank write bursts +system.physmem.perBankWrBursts::6 9032 # Per bank write bursts +system.physmem.perBankWrBursts::7 9363 # Per bank write bursts +system.physmem.perBankWrBursts::8 8843 # Per bank write bursts +system.physmem.perBankWrBursts::9 8764 # Per bank write bursts +system.physmem.perBankWrBursts::10 9099 # Per bank write bursts +system.physmem.perBankWrBursts::11 9352 # Per bank write bursts +system.physmem.perBankWrBursts::12 9596 # Per bank write bursts +system.physmem.perBankWrBursts::13 9639 # Per bank write bursts +system.physmem.perBankWrBursts::14 9447 # Per bank write bursts +system.physmem.perBankWrBursts::15 9010 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 5133932076000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 222430 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 148587 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -137,343 +139,366 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.140187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.041653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1280.875932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 27817 44.52% 44.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 9622 15.40% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5951 9.52% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3940 6.31% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2520 4.03% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1986 3.18% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1542 2.47% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1215 1.94% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 1005 1.61% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 910 1.46% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 598 0.96% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 543 0.87% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 367 0.59% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 364 0.58% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 356 0.57% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 454 0.73% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 284 0.45% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 192 0.31% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 180 0.29% 95.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 146 0.23% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 174 0.28% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 177 0.28% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 484 0.77% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 176 0.28% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 118 0.19% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 94 0.15% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 80 0.13% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 58 0.09% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 28 0.04% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 25 0.04% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 31 0.05% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 34 0.05% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 13 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 15 0.02% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 19 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 8 0.01% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 10 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 8 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.00% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 9 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 9 0.01% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.00% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 7 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 5 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 14 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 6 0.01% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 3 0.00% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 21 0.03% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 7 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 6 0.01% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 3 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 5 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 3 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 4 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 4 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 2 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.00% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 7 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 339 0.54% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 8 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 3 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 4 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 28 0.04% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 15 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 10 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 3 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 3 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 6 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 7 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 6 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 8 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 12 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 11 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 62 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62488 # Bytes accessed per row activation -system.physmem.totQLat 4021160000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8281507500 # Sum of mem lat for all requests -system.physmem.totBusLat 1109590000 # Total cycles spent in databus access -system.physmem.totBankLat 3150757500 # Total cycles spent in bank access -system.physmem.avgQLat 18120.03 # Average queueing delay per request -system.physmem.avgBankLat 14197.85 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37317.87 # Average memory access latency -system.physmem.avgRdBW 2.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.84 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.76 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.84 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation +system.physmem.totQLat 5163279754 # Total ticks spent queuing +system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers +system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks +system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.63 # Average write queue length over time -system.physmem.readRowHits 198603 # Number of row buffer hits during reads -system.physmem.writeRowHits 109131 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes -system.physmem.avgGap 13904740.88 # Average gap between requests -system.membus.throughput 5073674 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662109 # Transaction distribution -system.membus.trans_dist::ReadResp 662107 # Transaction distribution -system.membus.trans_dist::WriteReq 13770 # Transaction distribution -system.membus.trans_dist::WriteResp 13770 # Transaction distribution -system.membus.trans_dist::Writeback 148326 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2172 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1696 # Transaction distribution -system.membus.trans_dist::ReadExReq 179020 # Transaction distribution -system.membus.trans_dist::ReadExResp 179014 # Transaction distribution -system.membus.trans_dist::MessageReq 1646 # Transaction distribution -system.membus.trans_dist::MessageResp 1646 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473242 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1855469 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550173 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18252032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20044007 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5451200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5451200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25501791 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25501791 # Total data (bytes) -system.membus.snoop_data_through_bus 626624 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250581000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing +system.physmem.readRowHits 193089 # Number of row buffer hits during reads +system.physmem.writeRowHits 108689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes +system.physmem.avgGap 13837457.79 # Average gap between requests +system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 5101771 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662370 # Transaction distribution +system.membus.trans_dist::ReadResp 662362 # Transaction distribution +system.membus.trans_dist::WriteReq 13778 # Transaction distribution +system.membus.trans_dist::WriteResp 13778 # Transaction distribution +system.membus.trans_dist::Writeback 148587 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution +system.membus.trans_dist::ReadExReq 179504 # Transaction distribution +system.membus.trans_dist::ReadExResp 179502 # Transaction distribution +system.membus.trans_dist::MessageReq 1643 # Transaction distribution +system.membus.trans_dist::MessageResp 1643 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25543633 # Total data (bytes) +system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583304500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3292000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1605050249 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1646000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3149132971 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429400997 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47576 # number of replacements -system.iocache.tags.tagsinuse 0.153339 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992838664000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.153339 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.009584 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.009584 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152977935 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152977935 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10361858110 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10361858110 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10514836045 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10514836045 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10514836045 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10514836045 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -482,40 +507,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 168107.620879 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 168107.620879 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221786.346533 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 221786.346533 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220760.781965 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220760.781965 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 148180 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13622 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.877991 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105623935 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 105623935 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7930990116 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7930990116 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8036614051 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8036614051 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -524,18 +549,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116070.258242 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 116070.258242 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169755.781592 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 169755.781592 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -545,16 +570,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 636182 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225558 # Transaction distribution -system.iobus.trans_dist::ReadResp 225558 # Transaction distribution -system.iobus.trans_dist::WriteReq 57591 # Transaction distribution -system.iobus.trans_dist::WriteResp 57591 # Transaction distribution -system.iobus.trans_dist::MessageReq 1646 # Transaction distribution -system.iobus.trans_dist::MessageResp 1646 # Transaction distribution +system.iobus.throughput 638153 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225567 # Transaction distribution +system.iobus.trans_dist::ReadResp 225567 # Transaction distribution +system.iobus.trans_dist::WriteReq 57606 # Transaction distribution +system.iobus.trans_dist::WriteResp 57606 # Transaction distribution +system.iobus.trans_dist::MessageReq 1643 # Transaction distribution +system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -570,15 +595,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3292 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3292 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -594,20 +619,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6584 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6584 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276210 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276210 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3927144 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276232 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -637,456 +662,456 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424444048 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53407003 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1646000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85588006 # Number of BP lookups -system.cpu.branchPred.condPredicted 85588006 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 877454 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79215990 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77530840 # Number of BTB hits +system.cpu.branchPred.lookups 85592238 # Number of BP lookups +system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.872715 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1437704 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180381 # Number of incorrect RAS predictions. -system.cpu.numCycles 453669464 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions. +system.cpu.numCycles 453841851 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25482716 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422686689 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85588006 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78968544 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162633276 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3972302 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 106554 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71193509 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89294 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8469801 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382535 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2385 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262601517 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.178991 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100383881 38.23% 38.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1533037 0.58% 38.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71821115 27.35% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 895642 0.34% 66.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1564995 0.60% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2390879 0.91% 68.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1017520 0.39% 68.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1329446 0.51% 68.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81665002 31.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262601517 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188657 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29392698 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68340203 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158479192 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3338868 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3050556 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832478930 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 959 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3050556 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32088006 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43079490 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12529275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158770454 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13083736 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829577701 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21771 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6064622 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5141489 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991205554 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800191267 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1106790785 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 123 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963930499 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27275048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 452761 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 458610 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29575764 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16714812 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9817459 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1139197 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 962008 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824812969 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184552 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820895267 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 151456 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19155682 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29185416 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 129934 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262601517 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.126011 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400353 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76255592 29.04% 29.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15761044 6.00% 35.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10531368 4.01% 39.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7369443 2.81% 41.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75730840 28.84% 70.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3739599 1.42% 72.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72299562 27.53% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 768121 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145948 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262601517 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 345012 32.94% 32.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 32.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 974 0.09% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547730 52.30% 85.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153356 14.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307746 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793434579 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149572 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124688 0.02% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17663300 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9215382 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820895267 # Type of FU issued -system.cpu.iq.rate 1.809457 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1047313 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001276 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905699959 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845163637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 816985295 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 199 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821634741 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1691465 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued +system.cpu.iq.rate 1.808871 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2728859 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17017 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11975 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1400009 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931860 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12243 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3050556 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31208951 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2150350 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 825997521 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 243405 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16714812 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9817459 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 689575 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1619766 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11975 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 493977 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506066 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1000043 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819488058 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17361171 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1407208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26390625 # number of memory reference insts executed -system.cpu.iew.exec_branches 83079645 # Number of branches executed -system.cpu.iew.exec_stores 9029454 # Number of stores executed -system.cpu.iew.exec_rate 1.806355 # Inst execution rate -system.cpu.iew.wb_sent 819086222 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 816985349 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638544896 # num instructions producing a value -system.cpu.iew.wb_consumers 1043866074 # num instructions consuming a value +system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed +system.cpu.iew.exec_branches 83090404 # Number of branches executed +system.cpu.iew.exec_stores 9036920 # Number of stores executed +system.cpu.iew.exec_rate 1.805776 # Inst execution rate +system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638560375 # num instructions producing a value +system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800838 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611712 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19867682 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054616 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 887449 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259550960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.105446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863698 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88027122 33.92% 33.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11847553 4.56% 38.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3827434 1.47% 39.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74752127 28.80% 68.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2379438 0.92% 69.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1475953 0.57% 70.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 857436 0.33% 70.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70850710 27.30% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533187 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259550960 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407752265 # Number of instructions committed -system.cpu.commit.committedOps 806021401 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407772261 # Number of instructions committed +system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22403400 # Number of memory references committed -system.cpu.commit.loads 13985950 # Number of loads committed -system.cpu.commit.membars 474657 # Number of memory barriers committed -system.cpu.commit.branches 82156128 # Number of branches committed +system.cpu.commit.refs 22412414 # Number of memory references committed +system.cpu.commit.loads 13990896 # Number of loads committed +system.cpu.commit.membars 474709 # Number of memory barriers committed +system.cpu.commit.branches 82160310 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734862948 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155170 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533187 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734896243 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155289 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079828496 # The number of ROB reads -system.cpu.rob.rob_writes 1654843441 # The number of ROB writes -system.cpu.timesIdled 1258915 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191067947 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9845938983 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407752265 # Number of Instructions Simulated -system.cpu.committedOps 806021401 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407752265 # Number of Instructions Simulated -system.cpu.cpi 1.112611 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112611 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088694796 # number of integer regfile reads -system.cpu.int_regfile_writes 653771353 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.cc_regfile_reads 415601025 # number of cc regfile reads -system.cpu.cc_regfile_writes 321483560 # number of cc regfile writes -system.cpu.misc_regfile_reads 264032145 # number of misc regfile reads -system.cpu.misc_regfile_writes 402444 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53392020 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3013693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3013151 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1577044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121437 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 151603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8199918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61058944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207524391 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 566848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5217216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 274367399 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274343271 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 615040 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4030545417 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080212949 # The number of ROB reads +system.cpu.rob.rob_writes 1654925831 # The number of ROB writes +system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407772261 # Number of Instructions Simulated +system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated +system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads +system.cpu.int_regfile_writes 653799671 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads +system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes +system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads +system.cpu.misc_regfile_writes 402440 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1435258580 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141587747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14741736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 105191645 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 953576 # number of replacements -system.cpu.icache.tags.tagsinuse 510.036469 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7463561 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 954088 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.822718 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147479259250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.036469 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996165 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996165 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7463561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7463561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7463561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7463561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7463561 # number of overall hits -system.cpu.icache.overall_hits::total 7463561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1006237 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1006237 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1006237 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1006237 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1006237 # number of overall misses -system.cpu.icache.overall_misses::total 1006237 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14239259264 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14239259264 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14239259264 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14239259264 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14239259264 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14239259264 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8469798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8469798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8469798 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8469798 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8469798 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8469798 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118803 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118803 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118803 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118803 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118803 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118803 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14150.999480 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14150.999480 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14150.999480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14150.999480 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7035 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 587 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 207 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.985507 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 587 # average number of cycles each access was blocked +system.cpu.icache.tags.replacements 959142 # number of replacements +system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits +system.cpu.icache.overall_hits::total 7468451 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses +system.cpu.icache.overall_misses::total 1013022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52085 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52085 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52085 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52085 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52085 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52085 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954152 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 954152 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 954152 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 954152 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 954152 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 954152 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11748055164 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11748055164 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11748055164 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11748055164 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11748055164 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11748055164 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112653 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112653 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112653 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12312.561483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12312.561483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12312.561483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12312.561483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12312.561483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12312.561483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53298 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53298 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53298 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53298 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53298 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53298 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959724 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 959724 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 959724 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 959724 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 959724 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 959724 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11694537694 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11694537694 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11694537694 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.113155 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.113155 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12185.313376 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12185.313376 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8937 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.031585 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 20273 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8949 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.265393 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104907998500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031585 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376974 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376974 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20288 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 20288 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 8004 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.959011 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21893 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8020 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.729800 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5103903665500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.959011 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.434938 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.434938 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21891 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21891 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20290 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 20290 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20290 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 20290 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 106143491 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 106143491 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 106143491 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 106143491 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 106143491 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 106143491 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30111 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30111 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21893 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21893 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21893 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21893 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8894 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8894 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8894 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8894 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8894 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8894 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 101842497 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 101842497 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 101842497 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 101842497 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 101842497 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 101842497 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30785 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30785 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30113 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30113 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30113 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30113 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.326226 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.326226 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.326205 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.326205 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.326205 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.326205 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10805.608368 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10805.608368 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10805.608368 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10805.608368 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10805.608368 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10805.608368 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1095,78 +1120,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1536 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1536 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86483019 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86483019 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86483019 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86483019 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86483019 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86483019 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.326226 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.326226 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.326205 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.326205 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8804.135091 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2197 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2197 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8894 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8894 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8894 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8894 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 84047009 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 84047009 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 84047009 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 84047009 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 84047009 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.904441 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92410 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.337976 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 4994136871250 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.904441 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.931528 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.931528 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92410 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92410 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92410 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92410 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92410 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92410 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70084 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 70084 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70084 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 70084 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70084 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 70084 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 863900211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 863900211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 863900211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 863900211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 863900211 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 863900211 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162494 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 162494 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162494 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 162494 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162494 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 162494 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.431302 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.431302 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.431302 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.431302 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.431302 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.431302 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12326.639618 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12326.639618 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12326.639618 # average overall miss latency +system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1175,146 +1200,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 17433 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 17433 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70084 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70084 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70084 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 70084 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70084 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 70084 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 723600921 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 723600921 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 723600921 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 723600921 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 723600921 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 723600921 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.431302 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.431302 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.431302 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10324.766295 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1656223 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995363 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18981681 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1656735 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.457283 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995363 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10886449 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10886449 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8092566 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8092566 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18979015 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18979015 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18979015 # number of overall hits -system.cpu.dcache.overall_hits::total 18979015 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2233485 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2233485 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315362 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2548847 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2548847 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2548847 # number of overall misses -system.cpu.dcache.overall_misses::total 2548847 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33146878091 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33146878091 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12110851955 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12110851955 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45257730046 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45257730046 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45257730046 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45257730046 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13119934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13119934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8407928 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8407928 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21527862 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21527862 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21527862 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21527862 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170236 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170236 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037508 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037508 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118398 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118398 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118398 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118398 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14840.877862 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14840.877862 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38403.016074 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38403.016074 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17756.157998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17756.157998 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 397029 # number of cycles access was blocked +system.cpu.dcache.tags.replacements 1657437 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits +system.cpu.dcache.overall_hits::total 18986697 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2550677 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2550677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2550677 # number of overall misses +system.cpu.dcache.overall_misses::total 2550677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33004921637 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33004921637 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12257889032 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12257889032 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45262810669 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45262810669 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45262810669 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45262810669 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13125399 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13125399 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8411975 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8411975 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21537374 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21537374 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21537374 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21537374 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170241 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17745.410598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17745.410598 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 397669 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42211 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.405818 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558075 # number of writebacks -system.cpu.dcache.writebacks::total 1558075 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863964 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 863964 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25903 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25903 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 889867 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 889867 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 889867 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 889867 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369521 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369521 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289459 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289459 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1658980 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1658980 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1658980 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1658980 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17890697467 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17890697467 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11213904776 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11213904776 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29104602243 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29104602243 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29104602243 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29104602243 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363389500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363389500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537212500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537212500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99900602000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99900602000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104385 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104385 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077062 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13063.470708 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13063.470708 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38740.908992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38740.908992 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17543.672765 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17543.672765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17543.672765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17543.672765 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks +system.cpu.dcache.writebacks::total 1558744 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864490 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25919 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25919 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 890409 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 890409 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 890409 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 890409 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369989 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1369989 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290279 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290279 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1660268 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1660268 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1660268 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1660268 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17836083706 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17836083706 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11362753211 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11362753211 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29198836917 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29198836917 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29198836917 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034508 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034508 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13019.143735 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13019.143735 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39144.248158 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39144.248158 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1322,141 +1347,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111030 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64826.472459 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3778684 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.568570 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111632 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64821.705622 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3786761 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175570 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.568383 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50681.739726 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.389473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3154.839076 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10976.377823 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.773342 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000204 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50709.515998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.756367 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126012 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3028.517183 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.790063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.773766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000118 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.167486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989173 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64025 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7316 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 937955 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1333061 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2342357 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1577044 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1577044 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154757 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154757 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 64025 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 7316 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 937955 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1487818 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2497114 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 64025 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 7316 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 937955 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1487818 # number of overall hits -system.cpu.l2cache.overall_hits::total 2497114 # number of overall hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046212 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.169003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989101 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7222 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 943511 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1333169 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2348748 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1585586 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1585586 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 155047 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 155047 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 64846 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 7222 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 943511 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1488216 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2503795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 64846 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 7222 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 943511 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1488216 # number of overall hits +system.cpu.l2cache.overall_hits::total 2503795 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16091 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35754 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 51911 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1443 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1443 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132547 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132547 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16089 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 36006 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 52161 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133062 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133062 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16091 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 168301 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 184458 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16089 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169068 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185223 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16091 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 168301 # number of overall misses -system.cpu.l2cache.overall_misses::total 184458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5633750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 417750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1393223986 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2996305709 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4395581195 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16716837 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16716837 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9332768700 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9332768700 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5633750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 417750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1393223986 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12329074409 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13728349895 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5633750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 417750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1393223986 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12329074409 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13728349895 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64086 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7321 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 954046 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1368815 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2394268 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1577044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1577044 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1759 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1759 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287304 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287304 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64086 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 7321 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 954046 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1656119 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2681572 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64086 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 7321 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 954046 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1656119 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2681572 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000952 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000683 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016866 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026120 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021681 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820352 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820352 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461348 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461348 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000683 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016866 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.101624 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.068787 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000683 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016866 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.101624 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.068787 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92356.557377 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83550 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86584.052327 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83803.370504 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84675.332685 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11584.779626 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11584.779626 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70411.014206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70411.014206 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92356.557377 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86584.052327 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73256.097165 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74425.342869 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92356.557377 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86584.052327 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73256.097165 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74425.342869 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 16089 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169068 # number of overall misses +system.cpu.l2cache.overall_misses::total 185223 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5260500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1277797734 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940044940 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4223492924 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17900790 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 17900790 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9477459899 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9477459899 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5260500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1277797734 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12417504839 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13700952823 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5260500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1277797734 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12417504839 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13700952823 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64907 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7227 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 959600 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1369175 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2400909 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1585586 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1585586 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1776 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1776 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 288109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 288109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64907 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 7227 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 959600 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1657284 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2689018 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64907 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 7227 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 959600 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1657284 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2689018 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000940 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000692 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016766 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026298 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823198 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823198 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461846 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.461846 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000940 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000692 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016766 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102015 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.068881 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000940 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000692 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016766 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102015 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.068881 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86237.704918 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77950 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79420.581391 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81654.305949 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80970.321198 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12244.042408 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12244.042408 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71225.893937 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71225.893937 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73970.040562 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73970.040562 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1465,99 +1490,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101658 # number of writebacks -system.cpu.l2cache.writebacks::total 101658 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101920 # number of writebacks +system.cpu.l2cache.writebacks::total 101920 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16089 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35751 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 51906 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1443 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1443 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132547 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 132547 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16087 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36005 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52158 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133062 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133062 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16089 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 168298 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 184453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16087 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169067 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185220 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16089 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 168298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 184453 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4857750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 353750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1189838014 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545516291 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3740565805 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15357924 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15357924 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7668131300 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7668131300 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4857750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 353750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1189838014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10213647591 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11408697105 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4857750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 353750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1189838014 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10213647591 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11408697105 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250267000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250267000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2371416000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2371416000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91621683000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91621683000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026118 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021679 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820352 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820352 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068785 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068785 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73953.509479 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71201.261251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72064.227739 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10643.051975 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10643.051975 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57852.167910 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57852.167910 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16087 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169067 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185220 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4502000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075523016 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2491735810 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3572087076 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15586943 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15586943 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7807116101 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7807116101 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4502000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075523016 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10298851911 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11379203177 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4502000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075523016 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10298851911 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11379203177 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251387000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251387000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372677500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372677500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823198 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823198 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461846 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461846 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068880 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068880 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index e0fd581aa..d95103a1f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,365 +1,323 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.304492 # Number of seconds simulated -sim_ticks 5304492233500 # Number of ticks simulated -final_tick 5304492233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.303604 # Number of seconds simulated +sim_ticks 5303604289000 # Number of ticks simulated +final_tick 5303604289000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155930 # Simulator instruction rate (inst/s) -host_op_rate 299191 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7641192165 # Simulator tick rate (ticks/s) -host_mem_usage 831032 # Number of bytes of host memory used -host_seconds 694.20 # Real time elapsed on the host -sim_insts 108246430 # Number of instructions simulated -sim_ops 207697456 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 136600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 67168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 857797264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 68434149 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 89360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 41152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 170486264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 28476493 # Number of bytes read from this memory -system.physmem.bytes_read::total 1125563554 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857797264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 170486264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1028283528 # Number of instructions bytes read from this memory +host_inst_rate 170166 # Simulator instruction rate (inst/s) +host_op_rate 326512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8335943745 # Simulator tick rate (ticks/s) +host_mem_usage 875260 # Number of bytes of host memory used +host_seconds 636.23 # Real time elapsed on the host +sim_insts 108265301 # Number of instructions simulated +sim_ops 207738037 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 87544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 33280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 839536560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 65163112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 137640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 74624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 188924512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 31786983 # Number of bytes read from this memory +system.physmem.bytes_read::total 1125779383 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 839536560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 188924512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1028461072 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 47724441 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 22209848 # Number of bytes written to this memory -system.physmem.bytes_written::total 72925409 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 17075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 107224658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 11945854 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 21310783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4242510 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144766394 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 45585342 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 24372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 72949070 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 104942070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 11447211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 9328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 23615564 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4748353 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144795641 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 7033055 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 3067077 # Number of write requests responded to by this memory -system.physmem.num_writes::total 10146870 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 25752 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 12662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 161711475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12901169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 16846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 7758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32139978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5368373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 212190631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 161711475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32139978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 193851453 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563881 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 6738169 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 3365460 # Number of write requests responded to by this memory +system.physmem.num_writes::total 10150367 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 16507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 6275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 158295475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12286571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 25952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 14070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35621909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5993468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 212266851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 158295475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35621909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 193917384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563976 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 8996986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 4186989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13747859 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 25752 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 12665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 161711475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 21898154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 16846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 7758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32139978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 9555362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 225938490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 804 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 46736 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 804 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 46736 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 51456 # Total number of bytes read from memory -system.physmem.bytesWritten 2991104 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 35104 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 3280 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 3344 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 3056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2576 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2608 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2816 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3072 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2720 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 3008 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 3136 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 163206922999 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 292 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 512 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 46736 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 537 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5562.279330 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3318.964815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3321.501933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 31 5.77% 5.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 6 1.12% 6.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4 0.74% 7.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 7 1.30% 8.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 7 1.30% 10.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2 0.37% 10.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1 0.19% 10.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 2 0.37% 11.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1 0.19% 11.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1 0.19% 11.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2 0.37% 11.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1 0.19% 12.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.56% 12.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1 0.19% 12.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1 0.19% 13.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 62 11.55% 24.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.19% 24.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.19% 24.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.56% 25.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2 0.37% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.19% 26.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 16 2.98% 29.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.19% 29.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.19% 29.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 5 0.93% 30.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.19% 30.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.19% 30.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.19% 30.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 1 0.19% 31.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.19% 31.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.19% 31.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 35 6.52% 37.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.19% 38.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.19% 38.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.19% 38.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 8 1.49% 40.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.19% 40.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.56% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.19% 40.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 6 1.12% 42.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.19% 42.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 310 57.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 537 # Bytes accessed per row activation -system.physmem.totQLat 42021352 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 52311352 # Sum of mem lat for all requests -system.physmem.totBusLat 4020000 # Total cycles spent in databus access -system.physmem.totBankLat 6270000 # Total cycles spent in bank access -system.physmem.avgQLat 52265.36 # Average queueing delay per request -system.physmem.avgBankLat 7798.51 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 65063.87 # Average memory access latency -system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bw_write::cpu0.data 8595163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 4595480 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13754622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 16507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 6278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 158295475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 20881734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 25952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 14070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35621909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 10588948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 226021473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 0 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 0 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 0 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 0 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation +system.physmem.totQLat 0 # Total ticks spent queuing +system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 0 # Total ticks spent in databus transfers +system.physmem.totBankLat 0 # Total ticks spent accessing banks +system.physmem.avgQLat nan # Average queueing delay per DRAM burst +system.physmem.avgBankLat nan # Average bank access latency per DRAM burst +system.physmem.avgBusLat nan # Average bus latency per DRAM burst +system.physmem.avgMemAccLat nan # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.00 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 735 # Number of row buffer hits during reads -system.physmem.writeRowHits 46268 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 99.00 # Row buffer hit rate for writes -system.physmem.avgGap 3433044.24 # Average gap between requests -system.piobus.throughput 959190 # Throughput (bytes/s) -system.piobus.trans_dist::ReadReq 865004 # Transaction distribution -system.piobus.trans_dist::ReadResp 865004 # Transaction distribution -system.piobus.trans_dist::WriteReq 86867 # Transaction distribution -system.piobus.trans_dist::WriteResp 86867 # Transaction distribution -system.piobus.trans_dist::MessageReq 2698 # Transaction distribution -system.piobus.trans_dist::MessageResp 2698 # Transaction distribution -system.piobus.pkt_count_system.pc.south_bridge.ide.dma::system.physmem.port 95080 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.ide.dma::total 95080 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1704 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1648 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3352 # Packet count per connected master and slave (bytes) +system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests +system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state +system.piobus.throughput 388759 # Throughput (bytes/s) +system.piobus.trans_dist::ReadReq 864194 # Transaction distribution +system.piobus.trans_dist::ReadResp 864194 # Transaction distribution +system.piobus.trans_dist::WriteReq 40126 # Transaction distribution +system.piobus.trans_dist::WriteResp 40126 # Transaction distribution +system.piobus.trans_dist::MessageReq 2700 # Transaction distribution +system.piobus.trans_dist::MessageResp 2700 # Transaction distribution +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1702 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1644 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3346 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 7290 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 5756 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 988 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 82 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 46 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1028 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1014 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 178 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 20480 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 20120 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 751796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 751828 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1723300 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3752 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1721420 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 5240 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 376 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 8 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 33180 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 344 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 340 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 33180 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 6188 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 8322 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 85362 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 1020 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1020 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1024 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1024 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::total 1909138 # Packet count per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026208 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3408 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3296 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6704 # Cumulative packet size per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 6556 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 8324 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 87220 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 1032 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1032 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1022 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1022 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 1814040 # Packet count per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3404 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3288 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6692 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 4565 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 3669 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 494 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 41 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 23 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2028 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 89 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 10240 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 10060 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1503586 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1503650 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1995120 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 2095 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1994078 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 2965 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 188 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 4 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 16590 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 688 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 680 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 16590 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 3094 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 16641 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 55896 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 2040 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2040 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2048 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2048 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::total 5088016 # Cumulative packet size per connected master and slave (bytes) -system.piobus.data_through_bus 5088016 # Total data (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 3278 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 16645 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 56948 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 2064 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2064 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2044 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2044 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::total 2061826 # Cumulative packet size per connected master and slave (bytes) +system.piobus.data_through_bus 2061826 # Total data (bytes) system.piobus.reqLayer0.occupancy 51000 # Layer occupancy (ticks) system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer2.occupancy 10166500 # Layer occupancy (ticks) +system.piobus.reqLayer2.occupancy 10114500 # Layer occupancy (ticks) system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer3.occupancy 152000 # Layer occupancy (ticks) system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer4.occupancy 1062500 # Layer occupancy (ticks) +system.piobus.reqLayer4.occupancy 1060500 # Layer occupancy (ticks) system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer5.occupancy 98500 # Layer occupancy (ticks) system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%) @@ -369,13 +327,13 @@ system.piobus.reqLayer7.occupancy 22149500 # La system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks) system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer9.occupancy 1330000 # Layer occupancy (ticks) +system.piobus.reqLayer9.occupancy 1313000 # Layer occupancy (ticks) system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer10.occupancy 41670000 # Layer occupancy (ticks) system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer12.occupancy 23281000 # Layer occupancy (ticks) +system.piobus.reqLayer12.occupancy 23288000 # Layer occupancy (ticks) system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -385,36 +343,32 @@ system.piobus.reqLayer15.occupancy 10500 # La system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer17.occupancy 473785500 # Layer occupancy (ticks) +system.piobus.reqLayer17.occupancy 473822500 # Layer occupancy (ticks) system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer18.occupancy 3210816 # Layer occupancy (ticks) +system.piobus.reqLayer18.occupancy 3230956 # Layer occupancy (ticks) system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer19.occupancy 8819500 # Layer occupancy (ticks) +system.piobus.reqLayer19.occupancy 8830000 # Layer occupancy (ticks) system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer20.occupancy 3135584 # Layer occupancy (ticks) +system.piobus.reqLayer20.occupancy 3180944 # Layer occupancy (ticks) system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer21.occupancy 421722676 # Layer occupancy (ticks) -system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer22.occupancy 1069500 # Layer occupancy (ticks) system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer0.occupancy 52207182 # Layer occupancy (ticks) +system.piobus.respLayer0.occupancy 2420900 # Layer occupancy (ticks) system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer1.occupancy 2368900 # Layer occupancy (ticks) +system.piobus.respLayer1.occupancy 1925709500 # Layer occupancy (ticks) system.piobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer2.occupancy 1927202500 # Layer occupancy (ticks) +system.piobus.respLayer2.occupancy 68943500 # Layer occupancy (ticks) system.piobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer3.occupancy 67468000 # Layer occupancy (ticks) +system.piobus.respLayer3.occupancy 649000 # Layer occupancy (ticks) system.piobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer4.occupancy 641000 # Layer occupancy (ticks) +system.piobus.respLayer4.occupancy 642000 # Layer occupancy (ticks) system.piobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer5.occupancy 638500 # Layer occupancy (ticks) -system.piobus.respLayer5.utilization 0.0 # Layer utilization (%) -system.ruby.l1_cntrl0.L1Dcache.demand_hits 17400971 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 1603411 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 19004382 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 106716418 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 508240 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 107224658 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 16641315 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 1559170 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 18200485 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 104473354 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 468716 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 104942070 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -424,12 +378,12 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.L1Dcache.demand_hits 7028238 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 297663 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 7325901 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 21021438 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 289345 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 21310783 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 7796271 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 344075 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8140346 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 23285981 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 329583 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 23615564 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -439,514 +393,580 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l2_cntrl0.L2cache.demand_hits 2449214 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 249445 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2698659 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 0.088789 -system.ruby.network.routers0.msg_count.Control::0 2111651 -system.ruby.network.routers0.msg_count.Request_Control::0 68326 -system.ruby.network.routers0.msg_count.Response_Data::1 2154834 -system.ruby.network.routers0.msg_count.Response_Control::1 1565369 -system.ruby.network.routers0.msg_count.Response_Control::2 1557069 -system.ruby.network.routers0.msg_count.Writeback_Data::0 1435847 -system.ruby.network.routers0.msg_count.Writeback_Data::1 52 -system.ruby.network.routers0.msg_count.Writeback_Control::0 59460 -system.ruby.network.routers0.msg_bytes.Control::0 16893208 -system.ruby.network.routers0.msg_bytes.Request_Control::0 546608 -system.ruby.network.routers0.msg_bytes.Response_Data::1 155148048 -system.ruby.network.routers0.msg_bytes.Response_Control::1 12522952 -system.ruby.network.routers0.msg_bytes.Response_Control::2 12456552 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 103380984 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 3744 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 475680 -system.ruby.network.routers1.percent_links_utilized 0.020109 -system.ruby.network.routers1.msg_count.Control::0 587008 -system.ruby.network.routers1.msg_count.Request_Control::0 61976 -system.ruby.network.routers1.msg_count.Response_Data::1 624789 -system.ruby.network.routers1.msg_count.Response_Control::1 278706 -system.ruby.network.routers1.msg_count.Response_Control::2 271876 -system.ruby.network.routers1.msg_count.Writeback_Data::0 187266 -system.ruby.network.routers1.msg_count.Writeback_Data::1 273 -system.ruby.network.routers1.msg_count.Writeback_Control::0 22758 -system.ruby.network.routers1.msg_bytes.Control::0 4696064 -system.ruby.network.routers1.msg_bytes.Request_Control::0 495808 -system.ruby.network.routers1.msg_bytes.Response_Data::1 44984808 -system.ruby.network.routers1.msg_bytes.Response_Control::1 2229648 -system.ruby.network.routers1.msg_bytes.Response_Control::2 2175008 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 13483152 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 19656 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 182064 -system.ruby.network.routers2.percent_links_utilized 0.111786 -system.ruby.network.routers2.msg_count.Control::0 2871394 -system.ruby.network.routers2.msg_count.Request_Control::0 128339 -system.ruby.network.routers2.msg_count.Response_Data::1 2893297 -system.ruby.network.routers2.msg_count.Response_Control::1 1875820 -system.ruby.network.routers2.msg_count.Response_Control::2 1828945 -system.ruby.network.routers2.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers2.msg_count.Writeback_Data::1 325 -system.ruby.network.routers2.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers2.msg_bytes.Control::0 22971152 -system.ruby.network.routers2.msg_bytes.Request_Control::0 1026712 -system.ruby.network.routers2.msg_bytes.Response_Data::1 208317384 -system.ruby.network.routers2.msg_bytes.Response_Control::1 15006560 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 657744 -system.ruby.dir_cntrl0.memBuffer.memReq 267094 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 172735 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 94359 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 684452 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 920715 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 18 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 5950 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 926683 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 3.469501 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 909950 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 7902 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 10 # memory stalls due to read write turnaround +system.ruby.l2_cntrl0.L2cache.demand_hits 2450353 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 251191 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2701544 # Number of cache demand accesses +system.ruby.network.routers0.percent_links_utilized 0.085942 +system.ruby.network.routers0.msg_count.Control::0 2027886 +system.ruby.network.routers0.msg_count.Request_Control::0 68787 +system.ruby.network.routers0.msg_count.Response_Data::1 2071049 +system.ruby.network.routers0.msg_count.Response_Control::1 1525279 +system.ruby.network.routers0.msg_count.Response_Control::2 1517023 +system.ruby.network.routers0.msg_count.Writeback_Data::0 1403655 +system.ruby.network.routers0.msg_count.Writeback_Data::1 171 +system.ruby.network.routers0.msg_count.Writeback_Control::0 51157 +system.ruby.network.routers0.msg_bytes.Control::0 16223088 +system.ruby.network.routers0.msg_bytes.Request_Control::0 550296 +system.ruby.network.routers0.msg_bytes.Response_Data::1 149115528 +system.ruby.network.routers0.msg_bytes.Response_Control::1 12202232 +system.ruby.network.routers0.msg_bytes.Response_Control::2 12136184 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 101063160 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12312 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 409256 +system.ruby.network.routers1.percent_links_utilized 0.023064 +system.ruby.network.routers1.msg_count.Control::0 673658 +system.ruby.network.routers1.msg_count.Request_Control::0 62763 +system.ruby.network.routers1.msg_count.Response_Data::1 711847 +system.ruby.network.routers1.msg_count.Response_Control::1 320652 +system.ruby.network.routers1.msg_count.Response_Control::2 313476 +system.ruby.network.routers1.msg_count.Writeback_Data::0 219226 +system.ruby.network.routers1.msg_count.Writeback_Data::1 383 +system.ruby.network.routers1.msg_count.Writeback_Control::0 32004 +system.ruby.network.routers1.msg_bytes.Control::0 5389264 +system.ruby.network.routers1.msg_bytes.Request_Control::0 502104 +system.ruby.network.routers1.msg_bytes.Response_Data::1 51252984 +system.ruby.network.routers1.msg_bytes.Response_Control::1 2565216 +system.ruby.network.routers1.msg_bytes.Response_Control::2 2507808 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 15784272 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 27576 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 256032 +system.ruby.network.routers2.percent_links_utilized 0.111968 +system.ruby.network.routers2.msg_count.Control::0 2875657 +system.ruby.network.routers2.msg_count.Request_Control::0 129481 +system.ruby.network.routers2.msg_count.Response_Data::1 2899412 +system.ruby.network.routers2.msg_count.Response_Control::1 1882104 +system.ruby.network.routers2.msg_count.Response_Control::2 1830499 +system.ruby.network.routers2.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers2.msg_count.Writeback_Data::1 554 +system.ruby.network.routers2.msg_count.Writeback_Control::0 83161 +system.ruby.network.routers2.msg_bytes.Control::0 23005256 +system.ruby.network.routers2.msg_bytes.Request_Control::0 1035848 +system.ruby.network.routers2.msg_bytes.Response_Data::1 208757664 +system.ruby.network.routers2.msg_bytes.Response_Control::1 15056832 +system.ruby.network.routers2.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers2.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers2.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers2.msg_bytes.Writeback_Control::0 665288 +system.ruby.dir_cntrl0.memBuffer.memReq 315825 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 174561 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 141264 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 718428 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 922537 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 6012 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 928595 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.940220 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 911376 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 8161 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 74 # memory stalls due to read write turnaround system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 2845 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 8698 3.26% 3.26% | 8135 3.05% 6.30% | 8180 3.06% 9.36% | 8226 3.08% 12.44% | 8503 3.18% 15.63% | 8270 3.10% 18.72% | 8182 3.06% 21.79% | 8201 3.07% 24.86% | 8425 3.15% 28.01% | 8229 3.08% 31.09% | 8315 3.11% 34.21% | 8269 3.10% 37.30% | 8279 3.10% 40.40% | 8033 3.01% 43.41% | 8159 3.05% 46.46% | 7316 2.74% 49.20% | 8194 3.07% 52.27% | 8382 3.14% 55.41% | 8204 3.07% 58.48% | 8117 3.04% 61.52% | 8878 3.32% 64.84% | 8321 3.12% 67.96% | 8274 3.10% 71.06% | 8202 3.07% 74.13% | 8422 3.15% 77.28% | 8239 3.08% 80.37% | 8482 3.18% 83.54% | 9065 3.39% 86.94% | 8995 3.37% 90.30% | 8927 3.34% 93.65% | 8865 3.32% 96.96% | 8107 3.04% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 267094 # Number of accesses per bank - -system.ruby.network.routers3.percent_links_utilized 0.006355 -system.ruby.network.routers3.msg_count.Control::0 172735 -system.ruby.network.routers3.msg_count.Response_Data::1 267094 -system.ruby.network.routers3.msg_count.Response_Control::1 120099 -system.ruby.network.routers3.msg_bytes.Control::0 1381880 -system.ruby.network.routers3.msg_bytes.Response_Data::1 19230768 -system.ruby.network.routers3.msg_bytes.Response_Control::1 960792 -system.ruby.network.routers4.percent_links_utilized 0 -system.ruby.network.routers5.percent_links_utilized 0.045409 -system.ruby.network.routers5.msg_count.Control::0 2871394 -system.ruby.network.routers5.msg_count.Request_Control::0 130302 -system.ruby.network.routers5.msg_count.Response_Data::1 2970007 -system.ruby.network.routers5.msg_count.Response_Control::1 1919997 -system.ruby.network.routers5.msg_count.Response_Control::2 1828945 -system.ruby.network.routers5.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers5.msg_count.Writeback_Data::1 325 -system.ruby.network.routers5.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers5.msg_bytes.Control::0 22971152 -system.ruby.network.routers5.msg_bytes.Request_Control::0 1042416 -system.ruby.network.routers5.msg_bytes.Response_Data::1 213840504 -system.ruby.network.routers5.msg_bytes.Response_Control::1 15359976 -system.ruby.network.routers5.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers5.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers5.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers5.msg_bytes.Writeback_Control::0 657744 -system.ruby.network.msg_count.Control 8614182 -system.ruby.network.msg_count.Request_Control 388943 -system.ruby.network.msg_count.Response_Data 8910021 -system.ruby.network.msg_count.Response_Control 11246826 -system.ruby.network.msg_count.Writeback_Data 4870314 -system.ruby.network.msg_count.Writeback_Control 246654 -system.ruby.network.msg_byte.Control 68913456 -system.ruby.network.msg_byte.Request_Control 3111544 -system.ruby.network.msg_byte.Response_Data 641521512 -system.ruby.network.msg_byte.Response_Control 89974608 -system.ruby.network.msg_byte.Writeback_Data 350662608 -system.ruby.network.msg_byte.Writeback_Control 1973232 +system.ruby.dir_cntrl0.memBuffer.memArbWait 2918 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 10778 3.41% 3.41% | 9652 3.06% 6.47% | 9746 3.09% 9.55% | 9756 3.09% 12.64% | 10001 3.17% 15.81% | 9844 3.12% 18.93% | 9739 3.08% 22.01% | 9701 3.07% 25.08% | 9912 3.14% 28.22% | 9771 3.09% 31.31% | 9821 3.11% 34.42% | 9856 3.12% 37.55% | 9814 3.11% 40.65% | 9541 3.02% 43.67% | 9708 3.07% 46.75% | 8720 2.76% 49.51% | 9704 3.07% 52.58% | 9910 3.14% 55.72% | 9720 3.08% 58.80% | 9615 3.04% 61.84% | 10345 3.28% 65.12% | 9799 3.10% 68.22% | 9732 3.08% 71.30% | 9663 3.06% 74.36% | 9975 3.16% 77.52% | 9775 3.10% 80.61% | 9975 3.16% 83.77% | 10515 3.33% 87.10% | 10479 3.32% 90.42% | 10356 3.28% 93.70% | 10312 3.27% 96.96% | 9590 3.04% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 315825 # Number of accesses per bank + +system.ruby.network.routers3.percent_links_utilized 0.006686 +system.ruby.network.routers3.msg_count.Control::0 174113 +system.ruby.network.routers3.msg_count.Response_Data::1 271479 +system.ruby.network.routers3.msg_count.Response_Control::1 125011 +system.ruby.network.routers3.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers3.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers3.msg_bytes.Control::0 1392904 +system.ruby.network.routers3.msg_bytes.Response_Data::1 19546488 +system.ruby.network.routers3.msg_bytes.Response_Control::1 1000088 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers4.percent_links_utilized 0.000239 +system.ruby.network.routers4.msg_count.Response_Data::1 807 +system.ruby.network.routers4.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers4.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers4.msg_bytes.Response_Data::1 58104 +system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers5.percent_links_utilized 0.045581 +system.ruby.network.routers5.msg_count.Control::0 2875657 +system.ruby.network.routers5.msg_count.Request_Control::0 131550 +system.ruby.network.routers5.msg_count.Response_Data::1 2977297 +system.ruby.network.routers5.msg_count.Response_Control::1 1926523 +system.ruby.network.routers5.msg_count.Response_Control::2 1830499 +system.ruby.network.routers5.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers5.msg_count.Writeback_Data::1 554 +system.ruby.network.routers5.msg_count.Writeback_Control::0 130704 +system.ruby.network.routers5.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers5.msg_bytes.Control::0 23005256 +system.ruby.network.routers5.msg_bytes.Request_Control::0 1052400 +system.ruby.network.routers5.msg_bytes.Response_Data::1 214365384 +system.ruby.network.routers5.msg_bytes.Response_Control::1 15412184 +system.ruby.network.routers5.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers5.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers5.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers5.msg_bytes.Writeback_Control::0 1045632 +system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.msg_count.Control 8626971 +system.ruby.network.msg_count.Request_Control 392581 +system.ruby.network.msg_count.Response_Data 8931891 +system.ruby.network.msg_count.Response_Control 11271066 +system.ruby.network.msg_count.Writeback_Data 4870305 +system.ruby.network.msg_count.Writeback_Control 532320 +system.ruby.network.msg_byte.Control 69015768 +system.ruby.network.msg_byte.Request_Control 3140648 +system.ruby.network.msg_byte.Response_Data 643096152 +system.ruby.network.msg_byte.Response_Control 90168528 +system.ruby.network.msg_byte.Writeback_Data 350661960 +system.ruby.network.msg_byte.Writeback_Control 4258560 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10606783749 # number of cpu cycles simulated +system.cpu0.numCycles 10606043496 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 91841555 # Number of instructions committed -system.cpu0.committedOps 177241434 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 167144917 # Number of integer alu accesses +system.cpu0.committedInsts 90093236 # Number of instructions committed +system.cpu0.committedOps 174126687 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 164075837 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 2106041 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16306998 # number of instructions that are conditional controls -system.cpu0.num_int_insts 167144917 # number of integer instructions +system.cpu0.num_func_calls 2042485 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16069367 # number of instructions that are conditional controls +system.cpu0.num_int_insts 164075837 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315702148 # number of times the integer registers were read -system.cpu0.num_int_register_writes 141403252 # number of times the integer registers were written +system.cpu0.num_int_register_reads 309321057 # number of times the integer registers were read +system.cpu0.num_int_register_writes 138932000 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 97172274 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 67502160 # number of times the CC registers were written -system.cpu0.num_mem_refs 19838885 # number of memory refs -system.cpu0.num_load_insts 12792113 # Number of load instructions -system.cpu0.num_store_insts 7046772 # Number of store instructions -system.cpu0.num_idle_cycles 9879393312.871359 # Number of idle cycles -system.cpu0.num_busy_cycles 727390436.128641 # Number of busy cycles -system.cpu0.not_idle_fraction 0.068578 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.931422 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 95439290 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 66446258 # number of times the CC registers were written +system.cpu0.num_mem_refs 19043793 # number of memory refs +system.cpu0.num_load_insts 12292919 # Number of load instructions +system.cpu0.num_store_insts 6750874 # Number of store instructions +system.cpu0.num_idle_cycles 9893327113.048590 # Number of idle cycles +system.cpu0.num_busy_cycles 712716382.951410 # Number of busy cycles +system.cpu0.not_idle_fraction 0.067199 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.932801 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10608984467 # number of cpu cycles simulated +system.cpu1.numCycles 10607208578 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 16404875 # Number of instructions committed -system.cpu1.committedOps 30456022 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29781645 # Number of integer alu accesses +system.cpu1.committedInsts 18172065 # Number of instructions committed +system.cpu1.committedOps 33611350 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 32888204 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 684501 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2123636 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29781645 # number of integer instructions +system.cpu1.num_func_calls 748563 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2364634 # number of instructions that are conditional controls +system.cpu1.num_int_insts 32888204 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 60931294 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23868275 # number of times the integer registers were written +system.cpu1.num_int_register_reads 67386533 # number of times the integer registers were read +system.cpu1.num_int_register_writes 26370518 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 16456023 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 10042488 # number of times the CC registers were written -system.cpu1.num_mem_refs 7344657 # number of memory refs -system.cpu1.num_load_insts 4252428 # Number of load instructions -system.cpu1.num_store_insts 3092229 # Number of store instructions -system.cpu1.num_idle_cycles 10473305727.446026 # Number of idle cycles -system.cpu1.num_busy_cycles 135678739.553974 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012789 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987211 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 18215408 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 11108428 # number of times the CC registers were written +system.cpu1.num_mem_refs 8150413 # number of memory refs +system.cpu1.num_load_insts 4758811 # Number of load instructions +system.cpu1.num_store_insts 3391602 # Number of store instructions +system.cpu1.num_idle_cycles 10456532847.286028 # Number of idle cycles +system.cpu1.num_busy_cycles 150675730.713972 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014205 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985795 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.ruby.network.routers0.throttle0.link_utilization 0.096297 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 68326 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 2091943 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 1536429 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 546608 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 150619896 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 12291432 -system.ruby.network.routers0.throttle1.link_utilization 0.081281 -system.ruby.network.routers0.throttle1.msg_count.Control::0 2111651 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 62891 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 28940 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 1557069 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 1435847 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 52 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 59460 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 16893208 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 4528152 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 231520 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 12456552 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 103380984 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 3744 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 475680 -system.ruby.network.routers1.throttle0.link_utilization 0.025474 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 61976 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 565416 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 254379 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 495808 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 40709952 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 2035032 -system.ruby.network.routers1.throttle1.link_utilization 0.014743 -system.ruby.network.routers1.throttle1.msg_count.Control::0 587008 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 59373 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 24327 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 271876 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 187266 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 273 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 22758 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4696064 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 4274856 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 194616 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 2175008 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 13483152 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 19656 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 182064 -system.ruby.network.routers2.throttle0.link_utilization 0.100395 -system.ruby.network.routers2.throttle0.msg_count.Control::0 2698659 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 218289 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 116319 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1828945 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 325 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21589272 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 15716808 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 930552 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 657744 -system.ruby.network.routers2.throttle1.link_utilization 0.123177 -system.ruby.network.routers2.throttle1.msg_count.Control::0 172735 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::0 128339 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2675008 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1759501 -system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1381880 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::0 1026712 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 192600576 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 14076008 -system.ruby.network.routers3.throttle0.link_utilization 0.004877 -system.ruby.network.routers3.throttle0.msg_count.Control::0 172735 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 94359 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 12870 -system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1381880 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 6793848 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 102960 -system.ruby.network.routers3.throttle1.link_utilization 0.007832 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 172735 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 107229 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12436920 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 857832 -system.ruby.network.routers4.throttle0.link_utilization 0 -system.ruby.network.routers4.throttle1.link_utilization 0 -system.ruby.network.routers5.throttle0.link_utilization 0.096297 -system.ruby.network.routers5.throttle0.msg_count.Request_Control::0 68326 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 2091943 -system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 1536429 -system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::0 546608 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 150619896 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 12291432 -system.ruby.network.routers5.throttle1.link_utilization 0.025474 -system.ruby.network.routers5.throttle1.msg_count.Request_Control::0 61976 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 565416 -system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 254379 -system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::0 495808 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 40709952 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 2035032 -system.ruby.network.routers5.throttle2.link_utilization 0.100395 -system.ruby.network.routers5.throttle2.msg_count.Control::0 2698659 -system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 218289 -system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 116319 -system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1828945 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 325 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21589272 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 15716808 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 930552 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 657744 -system.ruby.network.routers5.throttle3.link_utilization 0.004877 -system.ruby.network.routers5.throttle3.msg_count.Control::0 172735 -system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 94359 -system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 12870 -system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1381880 -system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 6793848 -system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 102960 -system.ruby.network.routers5.throttle4.link_utilization 0 -system.ruby.l1_cntrl0.Load | 11423199 74.37% 74.37% | 3936524 25.63% 100.00% -system.ruby.l1_cntrl0.Load::total 15359723 - -system.ruby.l1_cntrl0.Ifetch | 107224661 83.42% 83.42% | 21310786 16.58% 100.00% -system.ruby.l1_cntrl0.Ifetch::total 128535447 - -system.ruby.l1_cntrl0.Store | 7581183 69.10% 69.10% | 3389377 30.90% 100.00% -system.ruby.l1_cntrl0.Store::total 10970560 - -system.ruby.l1_cntrl0.Inv | 28992 54.10% 54.10% | 24600 45.90% 100.00% -system.ruby.l1_cntrl0.Inv::total 53592 - -system.ruby.l1_cntrl0.L1_Replacement | 2066674 79.29% 79.29% | 539794 20.71% 100.00% -system.ruby.l1_cntrl0.L1_Replacement::total 2606468 - -system.ruby.l1_cntrl0.Fwd_GETX | 15777 50.64% 50.64% | 15379 49.36% 100.00% -system.ruby.l1_cntrl0.Fwd_GETX::total 31156 - -system.ruby.l1_cntrl0.Fwd_GETS | 23553 51.71% 51.71% | 21997 48.29% 100.00% -system.ruby.l1_cntrl0.Fwd_GETS::total 45550 - -system.ruby.l1_cntrl0.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 4 - -system.ruby.l1_cntrl0.Data | 1706 59.30% 59.30% | 1171 40.70% 100.00% -system.ruby.l1_cntrl0.Data::total 2877 - -system.ruby.l1_cntrl0.Data_Exclusive | 1216870 92.56% 92.56% | 97821 7.44% 100.00% -system.ruby.l1_cntrl0.Data_Exclusive::total 1314691 - -system.ruby.l1_cntrl0.DataS_fromL1 | 21997 48.29% 48.29% | 23557 51.71% 100.00% -system.ruby.l1_cntrl0.DataS_fromL1::total 45554 - -system.ruby.l1_cntrl0.Data_all_Acks | 851370 65.78% 65.78% | 442867 34.22% 100.00% -system.ruby.l1_cntrl0.Data_all_Acks::total 1294237 - -system.ruby.l1_cntrl0.Ack | 19708 47.72% 47.72% | 21592 52.28% 100.00% -system.ruby.l1_cntrl0.Ack::total 41300 - -system.ruby.l1_cntrl0.Ack_all | 21414 48.47% 48.47% | 22763 51.53% 100.00% -system.ruby.l1_cntrl0.Ack_all::total 44177 - -system.ruby.l1_cntrl0.WB_Ack | 1495307 87.68% 87.68% | 210024 12.32% 100.00% -system.ruby.l1_cntrl0.WB_Ack::total 1705331 - -system.ruby.l1_cntrl0.NP.Load | 1269187 90.60% 90.60% | 131722 9.40% 100.00% -system.ruby.l1_cntrl0.NP.Load::total 1400909 - -system.ruby.l1_cntrl0.NP.Ifetch | 507807 63.72% 63.72% | 289135 36.28% 100.00% -system.ruby.l1_cntrl0.NP.Ifetch::total 796942 - -system.ruby.l1_cntrl0.NP.Store | 290704 70.79% 70.79% | 119960 29.21% 100.00% -system.ruby.l1_cntrl0.NP.Store::total 410664 - -system.ruby.l1_cntrl0.NP.Inv | 6486 66.07% 66.07% | 3331 33.93% 100.00% -system.ruby.l1_cntrl0.NP.Inv::total 9817 - -system.ruby.l1_cntrl0.I.Load | 16022 50.92% 50.92% | 15443 49.08% 100.00% -system.ruby.l1_cntrl0.I.Load::total 31465 +system.ruby.network.routers0.throttle0.link_utilization 0.092567 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 68787 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 2008081 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 1496069 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 550296 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 144581832 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 11968552 +system.ruby.network.routers0.throttle1.link_utilization 0.079316 +system.ruby.network.routers0.throttle1.msg_count.Control::0 2027886 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 62968 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 29210 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 1517023 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 1403655 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 171 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 51157 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 16223088 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 4533696 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 233680 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 12136184 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 101063160 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 12312 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 409256 +system.ruby.network.routers1.throttle0.link_utilization 0.029348 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 62763 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 651911 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 295944 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 502104 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 46937592 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 2367552 +system.ruby.network.routers1.throttle1.link_utilization 0.016780 +system.ruby.network.routers1.throttle1.msg_count.Control::0 673658 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 59936 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 24708 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 313476 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 219226 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 383 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 32004 +system.ruby.network.routers1.throttle1.msg_bytes.Control::0 5389264 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 4315392 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 197664 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 2507808 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 15784272 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 27576 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 256032 +system.ruby.network.routers2.throttle0.link_utilization 0.100531 +system.ruby.network.routers2.throttle0.msg_count.Control::0 2701544 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 219939 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 121479 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1830499 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 554 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 83161 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21612352 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 15835608 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 971832 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 665288 +system.ruby.network.routers2.throttle1.link_utilization 0.123404 +system.ruby.network.routers2.throttle1.msg_count.Control::0 174113 +system.ruby.network.routers2.throttle1.msg_count.Request_Control::0 129481 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2679473 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1760625 +system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1392904 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::0 1035848 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 192922056 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 14085000 +system.ruby.network.routers3.throttle0.link_utilization 0.005203 +system.ruby.network.routers3.throttle0.msg_count.Control::0 174113 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 96559 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 13031 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1392904 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 6952248 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 104248 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers3.throttle1.link_utilization 0.008169 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 174920 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 111980 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12594240 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 895840 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers4.throttle0.link_utilization 0.000255 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 807 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58104 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers4.throttle1.link_utilization 0.000224 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers5.throttle0.link_utilization 0.092567 +system.ruby.network.routers5.throttle0.msg_count.Request_Control::0 68787 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 2008081 +system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 1496069 +system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::0 550296 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 144581832 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 11968552 +system.ruby.network.routers5.throttle1.link_utilization 0.029348 +system.ruby.network.routers5.throttle1.msg_count.Request_Control::0 62763 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 651911 +system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 295944 +system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::0 502104 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 46937592 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 2367552 +system.ruby.network.routers5.throttle2.link_utilization 0.100531 +system.ruby.network.routers5.throttle2.msg_count.Control::0 2701544 +system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 219939 +system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 121479 +system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1830499 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 554 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 83161 +system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21612352 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 15835608 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 971832 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 665288 +system.ruby.network.routers5.throttle3.link_utilization 0.005203 +system.ruby.network.routers5.throttle3.msg_count.Control::0 174113 +system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 96559 +system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 13031 +system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1392904 +system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 6952248 +system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 104248 +system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers5.throttle4.link_utilization 0.000255 +system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 807 +system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58104 +system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888 +system.ruby.l1_cntrl0.Load | 10937660 71.18% 71.18% | 4428777 28.82% 100.00% +system.ruby.l1_cntrl0.Load::total 15366437 + +system.ruby.l1_cntrl0.Ifetch | 104942071 81.63% 81.63% | 23615568 18.37% 100.00% +system.ruby.l1_cntrl0.Ifetch::total 128557639 + +system.ruby.l1_cntrl0.Store | 7262825 66.18% 66.18% | 3711569 33.82% 100.00% +system.ruby.l1_cntrl0.Store::total 10974394 + +system.ruby.l1_cntrl0.Inv | 29381 53.94% 53.94% | 25091 46.06% 100.00% +system.ruby.l1_cntrl0.Inv::total 54472 + +system.ruby.l1_cntrl0.L1_Replacement | 1982628 75.99% 75.99% | 626364 24.01% 100.00% +system.ruby.l1_cntrl0.L1_Replacement::total 2608992 + +system.ruby.l1_cntrl0.Fwd_GETX | 15844 50.70% 50.70% | 15408 49.30% 100.00% +system.ruby.l1_cntrl0.Fwd_GETX::total 31252 + +system.ruby.l1_cntrl0.Fwd_GETS | 23557 51.41% 51.41% | 22264 48.59% 100.00% +system.ruby.l1_cntrl0.Fwd_GETS::total 45821 + +system.ruby.l1_cntrl0.Fwd_GET_INSTR | 5 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 5 + +system.ruby.l1_cntrl0.Data | 1647 57.45% 57.45% | 1220 42.55% 100.00% +system.ruby.l1_cntrl0.Data::total 2867 + +system.ruby.l1_cntrl0.Data_Exclusive | 1191679 90.64% 90.64% | 123071 9.36% 100.00% +system.ruby.l1_cntrl0.Data_Exclusive::total 1314750 + +system.ruby.l1_cntrl0.DataS_fromL1 | 22264 48.58% 48.58% | 23562 51.42% 100.00% +system.ruby.l1_cntrl0.DataS_fromL1::total 45826 + +system.ruby.l1_cntrl0.Data_all_Acks | 792491 61.12% 61.12% | 504058 38.88% 100.00% +system.ruby.l1_cntrl0.Data_all_Acks::total 1296549 + +system.ruby.l1_cntrl0.Ack | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.Ack::total 41552 + +system.ruby.l1_cntrl0.Ack_all | 21452 48.29% 48.29% | 22967 51.71% 100.00% +system.ruby.l1_cntrl0.Ack_all::total 44419 + +system.ruby.l1_cntrl0.WB_Ack | 1454812 85.27% 85.27% | 251230 14.73% 100.00% +system.ruby.l1_cntrl0.WB_Ack::total 1706042 + +system.ruby.l1_cntrl0.NP.Load | 1239865 88.45% 88.45% | 161879 11.55% 100.00% +system.ruby.l1_cntrl0.NP.Load::total 1401744 + +system.ruby.l1_cntrl0.NP.Ifetch | 468275 58.71% 58.71% | 329378 41.29% 100.00% +system.ruby.l1_cntrl0.NP.Ifetch::total 797653 + +system.ruby.l1_cntrl0.NP.Store | 275512 66.93% 66.93% | 136131 33.07% 100.00% +system.ruby.l1_cntrl0.NP.Store::total 411643 + +system.ruby.l1_cntrl0.NP.Inv | 6534 64.01% 64.01% | 3673 35.99% 100.00% +system.ruby.l1_cntrl0.NP.Inv::total 10207 -system.ruby.l1_cntrl0.I.Ifetch | 433 67.34% 67.34% | 210 32.66% 100.00% -system.ruby.l1_cntrl0.I.Ifetch::total 643 +system.ruby.l1_cntrl0.I.Load | 16225 51.38% 51.38% | 15353 48.62% 100.00% +system.ruby.l1_cntrl0.I.Load::total 31578 -system.ruby.l1_cntrl0.I.Store | 7790 46.55% 46.55% | 8946 53.45% 100.00% -system.ruby.l1_cntrl0.I.Store::total 16736 +system.ruby.l1_cntrl0.I.Ifetch | 441 68.27% 68.27% | 205 31.73% 100.00% +system.ruby.l1_cntrl0.I.Ifetch::total 646 -system.ruby.l1_cntrl0.I.L1_Replacement | 13955 53.66% 53.66% | 12049 46.34% 100.00% -system.ruby.l1_cntrl0.I.L1_Replacement::total 26004 +system.ruby.l1_cntrl0.I.Store | 7763 46.41% 46.41% | 8965 53.59% 100.00% +system.ruby.l1_cntrl0.I.Store::total 16728 -system.ruby.l1_cntrl0.S.Load | 738807 59.22% 59.22% | 508786 40.78% 100.00% -system.ruby.l1_cntrl0.S.Load::total 1247593 +system.ruby.l1_cntrl0.I.L1_Replacement | 14196 53.57% 53.57% | 12303 46.43% 100.00% +system.ruby.l1_cntrl0.I.L1_Replacement::total 26499 -system.ruby.l1_cntrl0.S.Ifetch | 106716418 83.54% 83.54% | 21021438 16.46% 100.00% -system.ruby.l1_cntrl0.S.Ifetch::total 127737856 +system.ruby.l1_cntrl0.S.Load | 716363 57.80% 57.80% | 523017 42.20% 100.00% +system.ruby.l1_cntrl0.S.Load::total 1239380 -system.ruby.l1_cntrl0.S.Store | 19708 47.72% 47.72% | 21592 52.28% 100.00% -system.ruby.l1_cntrl0.S.Store::total 41300 +system.ruby.l1_cntrl0.S.Ifetch | 104473354 81.77% 81.77% | 23285981 18.23% 100.00% +system.ruby.l1_cntrl0.S.Ifetch::total 127759335 -system.ruby.l1_cntrl0.S.Inv | 22433 51.85% 51.85% | 20836 48.15% 100.00% -system.ruby.l1_cntrl0.S.Inv::total 43269 +system.ruby.l1_cntrl0.S.Store | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.S.Store::total 41552 -system.ruby.l1_cntrl0.S.L1_Replacement | 557412 63.69% 63.69% | 317721 36.31% 100.00% -system.ruby.l1_cntrl0.S.L1_Replacement::total 875133 +system.ruby.l1_cntrl0.S.Inv | 22660 52.04% 52.04% | 20885 47.96% 100.00% +system.ruby.l1_cntrl0.S.Inv::total 43545 -system.ruby.l1_cntrl0.E.Load | 3045109 82.70% 82.70% | 636901 17.30% 100.00% -system.ruby.l1_cntrl0.E.Load::total 3682010 +system.ruby.l1_cntrl0.S.L1_Replacement | 513620 58.60% 58.60% | 362831 41.40% 100.00% +system.ruby.l1_cntrl0.S.L1_Replacement::total 876451 -system.ruby.l1_cntrl0.E.Store | 119075 77.49% 77.49% | 34591 22.51% 100.00% -system.ruby.l1_cntrl0.E.Store::total 153666 +system.ruby.l1_cntrl0.E.Load | 2877485 78.07% 78.07% | 808285 21.93% 100.00% +system.ruby.l1_cntrl0.E.Load::total 3685770 -system.ruby.l1_cntrl0.E.Inv | 21 11.60% 11.60% | 160 88.40% 100.00% -system.ruby.l1_cntrl0.E.Inv::total 181 +system.ruby.l1_cntrl0.E.Store | 114491 74.50% 74.50% | 39180 25.50% 100.00% +system.ruby.l1_cntrl0.E.Store::total 153671 -system.ruby.l1_cntrl0.E.L1_Replacement | 1096110 94.67% 94.67% | 61694 5.33% 100.00% -system.ruby.l1_cntrl0.E.L1_Replacement::total 1157804 +system.ruby.l1_cntrl0.E.Inv | 16 9.64% 9.64% | 150 90.36% 100.00% +system.ruby.l1_cntrl0.E.Inv::total 166 -system.ruby.l1_cntrl0.E.Fwd_GETX | 178 53.13% 53.13% | 157 46.87% 100.00% -system.ruby.l1_cntrl0.E.Fwd_GETX::total 335 +system.ruby.l1_cntrl0.E.L1_Replacement | 1075597 92.92% 92.92% | 82009 7.08% 100.00% +system.ruby.l1_cntrl0.E.L1_Replacement::total 1157606 -system.ruby.l1_cntrl0.E.Fwd_GETS | 1386 57.01% 57.01% | 1045 42.99% 100.00% -system.ruby.l1_cntrl0.E.Fwd_GETS::total 2431 +system.ruby.l1_cntrl0.E.Fwd_GETX | 157 36.77% 36.77% | 270 63.23% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GETX::total 427 -system.ruby.l1_cntrl0.M.Load | 6354074 70.62% 70.62% | 2643672 29.38% 100.00% -system.ruby.l1_cntrl0.M.Load::total 8997746 +system.ruby.l1_cntrl0.E.Fwd_GETS | 1309 50.17% 50.17% | 1300 49.83% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GETS::total 2609 -system.ruby.l1_cntrl0.M.Store | 7143906 69.04% 69.04% | 3204288 30.96% 100.00% -system.ruby.l1_cntrl0.M.Store::total 10348194 +system.ruby.l1_cntrl0.E.Fwd_GET_INSTR | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GET_INSTR::total 1 -system.ruby.l1_cntrl0.M.Inv | 52 16.00% 16.00% | 273 84.00% 100.00% -system.ruby.l1_cntrl0.M.Inv::total 325 +system.ruby.l1_cntrl0.M.Load | 6087722 67.58% 67.58% | 2920243 32.42% 100.00% +system.ruby.l1_cntrl0.M.Load::total 9007965 -system.ruby.l1_cntrl0.M.L1_Replacement | 399197 72.91% 72.91% | 148330 27.09% 100.00% -system.ruby.l1_cntrl0.M.L1_Replacement::total 547527 +system.ruby.l1_cntrl0.M.Store | 6845254 66.13% 66.13% | 3505546 33.87% 100.00% +system.ruby.l1_cntrl0.M.Store::total 10350800 -system.ruby.l1_cntrl0.M.Fwd_GETX | 15599 50.61% 50.61% | 15222 49.39% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GETX::total 30821 +system.ruby.l1_cntrl0.M.Inv | 171 30.87% 30.87% | 383 69.13% 100.00% +system.ruby.l1_cntrl0.M.Inv::total 554 -system.ruby.l1_cntrl0.M.Fwd_GETS | 22167 51.41% 51.41% | 20952 48.59% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GETS::total 43119 +system.ruby.l1_cntrl0.M.L1_Replacement | 379215 69.14% 69.14% | 169221 30.86% 100.00% +system.ruby.l1_cntrl0.M.L1_Replacement::total 548436 + +system.ruby.l1_cntrl0.M.Fwd_GETX | 15687 50.89% 50.89% | 15138 49.11% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GETX::total 30825 + +system.ruby.l1_cntrl0.M.Fwd_GETS | 22248 51.49% 51.49% | 20963 48.51% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GETS::total 43211 system.ruby.l1_cntrl0.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.l1_cntrl0.M.Fwd_GET_INSTR::total 4 -system.ruby.l1_cntrl0.IS.Data_Exclusive | 1216870 92.56% 92.56% | 97821 7.44% 100.00% -system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1314691 - -system.ruby.l1_cntrl0.IS.DataS_fromL1 | 21997 48.29% 48.29% | 23557 51.71% 100.00% -system.ruby.l1_cntrl0.IS.DataS_fromL1::total 45554 - -system.ruby.l1_cntrl0.IS.Data_all_Acks | 554582 63.77% 63.77% | 315132 36.23% 100.00% -system.ruby.l1_cntrl0.IS.Data_all_Acks::total 869714 - -system.ruby.l1_cntrl0.IM.Data | 1706 59.30% 59.30% | 1171 40.70% 100.00% -system.ruby.l1_cntrl0.IM.Data::total 2877 - -system.ruby.l1_cntrl0.IM.Data_all_Acks | 296788 69.91% 69.91% | 127735 30.09% 100.00% -system.ruby.l1_cntrl0.IM.Data_all_Acks::total 424523 - -system.ruby.l1_cntrl0.SM.Ack | 19708 47.72% 47.72% | 21592 52.28% 100.00% -system.ruby.l1_cntrl0.SM.Ack::total 41300 - -system.ruby.l1_cntrl0.SM.Ack_all | 21414 48.47% 48.47% | 22763 51.53% 100.00% -system.ruby.l1_cntrl0.SM.Ack_all::total 44177 - -system.ruby.l1_cntrl0.M_I.Ifetch | 3 50.00% 50.00% | 3 50.00% 100.00% -system.ruby.l1_cntrl0.M_I.Ifetch::total 6 - -system.ruby.l1_cntrl0.M_I.WB_Ack | 1495307 87.68% 87.68% | 210024 12.32% 100.00% -system.ruby.l1_cntrl0.M_I.WB_Ack::total 1705331 - -system.ruby.l2_cntrl0.L1_GET_INSTR 797586 0.00% 0.00% -system.ruby.l2_cntrl0.L1_GETS 1432569 0.00% 0.00% -system.ruby.l2_cntrl0.L1_GETX 427401 0.00% 0.00% -system.ruby.l2_cntrl0.L1_UPGRADE 41300 0.00% 0.00% -system.ruby.l2_cntrl0.L1_PUTX 1705331 0.00% 0.00% -system.ruby.l2_cntrl0.L2_Replacement 94194 0.00% 0.00% -system.ruby.l2_cntrl0.L2_Replacement_clean 13035 0.00% 0.00% -system.ruby.l2_cntrl0.Mem_Data 172735 0.00% 0.00% -system.ruby.l2_cntrl0.Mem_Ack 107229 0.00% 0.00% -system.ruby.l2_cntrl0.WB_Data 45318 0.00% 0.00% -system.ruby.l2_cntrl0.WB_Data_clean 561 0.00% 0.00% -system.ruby.l2_cntrl0.Ack 1963 0.00% 0.00% -system.ruby.l2_cntrl0.Ack_all 7127 0.00% 0.00% -system.ruby.l2_cntrl0.Unblock 45554 0.00% 0.00% -system.ruby.l2_cntrl0.Exclusive_Unblock 1783391 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15440 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GETS 31271 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GETX 126024 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GET_INSTR 781852 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GETS 72133 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GETX 3021 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_UPGRADE 41300 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L2_Replacement 241 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6705 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GET_INSTR 289 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GETS 1283420 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GETX 267199 0.00% 0.00% -system.ruby.l2_cntrl0.M.L2_Replacement 93756 0.00% 0.00% -system.ruby.l2_cntrl0.M.L2_Replacement_clean 6021 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GETS 45550 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GETX 31156 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_PUTX 1705331 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L2_Replacement 197 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L2_Replacement_clean 309 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive | 1191679 90.64% 90.64% | 123071 9.36% 100.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1314750 + +system.ruby.l1_cntrl0.IS.DataS_fromL1 | 22264 48.58% 48.58% | 23562 51.42% 100.00% +system.ruby.l1_cntrl0.IS.DataS_fromL1::total 45826 + +system.ruby.l1_cntrl0.IS.Data_all_Acks | 510863 58.65% 58.65% | 360182 41.35% 100.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks::total 871045 + +system.ruby.l1_cntrl0.IM.Data | 1647 57.45% 57.45% | 1220 42.55% 100.00% +system.ruby.l1_cntrl0.IM.Data::total 2867 + +system.ruby.l1_cntrl0.IM.Data_all_Acks | 281628 66.19% 66.19% | 143876 33.81% 100.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks::total 425504 + +system.ruby.l1_cntrl0.SM.Ack | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.SM.Ack::total 41552 + +system.ruby.l1_cntrl0.SM.Ack_all | 21452 48.29% 48.29% | 22967 51.71% 100.00% +system.ruby.l1_cntrl0.SM.Ack_all::total 44419 + +system.ruby.l1_cntrl0.M_I.Ifetch | 1 20.00% 20.00% | 4 80.00% 100.00% +system.ruby.l1_cntrl0.M_I.Ifetch::total 5 + +system.ruby.l1_cntrl0.M_I.Fwd_GETS | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.l1_cntrl0.M_I.Fwd_GETS::total 1 + +system.ruby.l1_cntrl0.M_I.WB_Ack | 1454812 85.27% 85.27% | 251229 14.73% 100.00% +system.ruby.l1_cntrl0.M_I.WB_Ack::total 1706041 + +system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack::total 1 + +system.ruby.l2_cntrl0.L1_GET_INSTR 798300 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 1433505 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 428371 0.00% 0.00% +system.ruby.l2_cntrl0.L1_UPGRADE 41552 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 1706043 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 93999 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 13201 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 174113 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 109590 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 45725 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data_clean 655 0.00% 0.00% +system.ruby.l2_cntrl0.Ack 2069 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 7430 0.00% 0.00% +system.ruby.l2_cntrl0.Unblock 45826 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 1784673 0.00% 0.00% +system.ruby.l2_cntrl0.MEM_Inv 4780 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15882 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 31693 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 126538 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GET_INSTR 782387 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETS 72751 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETX 3011 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_UPGRADE 41552 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_PUTX 1 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement 271 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6989 0.00% 0.00% +system.ruby.l2_cntrl0.SS.MEM_Inv 4 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GET_INSTR 25 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 1283057 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 267570 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 93550 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 5909 0.00% 0.00% +system.ruby.l2_cntrl0.M.MEM_Inv 2147 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GET_INSTR 5 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GETS 45821 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GETX 31252 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 1706041 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement 178 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 303 0.00% 0.00% +system.ruby.l2_cntrl0.MT.MEM_Inv 239 0.00% 0.00% system.ruby.l2_cntrl0.M_I.L1_GET_INSTR 1 0.00% 0.00% -system.ruby.l2_cntrl0.M_I.Mem_Ack 107229 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.WB_Data 160 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.Ack_all 37 0.00% 0.00% -system.ruby.l2_cntrl0.MCT_I.WB_Data 165 0.00% 0.00% -system.ruby.l2_cntrl0.MCT_I.Ack_all 144 0.00% 0.00% -system.ruby.l2_cntrl0.I_I.Ack 1732 0.00% 0.00% -system.ruby.l2_cntrl0.I_I.Ack_all 6705 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.Ack 231 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.Ack_all 241 0.00% 0.00% -system.ruby.l2_cntrl0.ISS.Mem_Data 31271 0.00% 0.00% -system.ruby.l2_cntrl0.IS.Mem_Data 15440 0.00% 0.00% -system.ruby.l2_cntrl0.IM.Mem_Data 126024 0.00% 0.00% -system.ruby.l2_cntrl0.SS_MB.L1_GETS 136 0.00% 0.00% -system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 44321 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.L1_GETS 59 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.L1_GETX 1 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1739070 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.WB_Data 44897 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 561 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.Unblock 96 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IB.WB_Data 96 0.00% 0.00% -system.ruby.l2_cntrl0.MT_SB.Unblock 45458 0.00% 0.00% -system.ruby.dir_cntrl0.Fetch 172735 0.00% 0.00% -system.ruby.dir_cntrl0.Data 94359 0.00% 0.00% -system.ruby.dir_cntrl0.Memory_Data 172735 0.00% 0.00% -system.ruby.dir_cntrl0.Memory_Ack 94359 0.00% 0.00% -system.ruby.dir_cntrl0.CleanReplacement 12870 0.00% 0.00% -system.ruby.dir_cntrl0.I.Fetch 172735 0.00% 0.00% -system.ruby.dir_cntrl0.M.Data 94359 0.00% 0.00% -system.ruby.dir_cntrl0.M.CleanReplacement 12870 0.00% 0.00% -system.ruby.dir_cntrl0.IM.Memory_Data 172735 0.00% 0.00% -system.ruby.dir_cntrl0.MI.Memory_Ack 94359 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 109590 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.MEM_Inv 2147 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.WB_Data 384 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.Ack_all 33 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.MEM_Inv 239 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 170 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 133 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack 1795 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 6989 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.Ack 274 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.Ack_all 275 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.MEM_Inv 4 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 31693 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 15882 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 126538 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.L1_GETS 134 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 44563 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_GETS 49 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1740110 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.L1_PUTX 1 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.WB_Data 45078 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 654 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.Unblock 94 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IB.WB_Data 93 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IB.WB_Data_clean 1 0.00% 0.00% +system.ruby.l2_cntrl0.MT_SB.Unblock 45732 0.00% 0.00% +system.ruby.dma_cntrl0.ReadRequest 807 0.00% 0.00% +system.ruby.dma_cntrl0.WriteRequest 46736 0.00% 0.00% +system.ruby.dma_cntrl0.Data 807 0.00% 0.00% +system.ruby.dma_cntrl0.Ack 46736 0.00% 0.00% +system.ruby.dma_cntrl0.READY.ReadRequest 807 0.00% 0.00% +system.ruby.dma_cntrl0.READY.WriteRequest 46736 0.00% 0.00% +system.ruby.dma_cntrl0.BUSY_RD.Data 807 0.00% 0.00% +system.ruby.dma_cntrl0.BUSY_WR.Ack 46736 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 174113 0.00% 0.00% +system.ruby.dir_cntrl0.Data 96559 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 174561 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 141264 0.00% 0.00% +system.ruby.dir_cntrl0.DMA_READ 807 0.00% 0.00% +system.ruby.dir_cntrl0.DMA_WRITE 46736 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 13031 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 174113 0.00% 0.00% +system.ruby.dir_cntrl0.I.DMA_READ 448 0.00% 0.00% +system.ruby.dir_cntrl0.I.DMA_WRITE 44705 0.00% 0.00% +system.ruby.dir_cntrl0.ID.Memory_Data 448 0.00% 0.00% +system.ruby.dir_cntrl0.ID_W.Memory_Ack 44705 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 94169 0.00% 0.00% +system.ruby.dir_cntrl0.M.DMA_READ 359 0.00% 0.00% +system.ruby.dir_cntrl0.M.DMA_WRITE 2031 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 13031 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 174113 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 94169 0.00% 0.00% +system.ruby.dir_cntrl0.M_DRD.Data 359 0.00% 0.00% +system.ruby.dir_cntrl0.M_DRDI.Memory_Ack 359 0.00% 0.00% +system.ruby.dir_cntrl0.M_DWR.Data 2031 0.00% 0.00% +system.ruby.dir_cntrl0.M_DWRI.Memory_Ack 2031 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index f1500ba2f..e884e1c2d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,155 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137889 # Number of seconds simulated -sim_ticks 5137889173500 # Number of ticks simulated -final_tick 5137889173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137942 # Number of seconds simulated +sim_ticks 5137941673500 # Number of ticks simulated +final_tick 5137941673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239672 # Simulator instruction rate (inst/s) -host_op_rate 476391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5046842796 # Simulator tick rate (ticks/s) -host_mem_usage 957396 # Number of bytes of host memory used -host_seconds 1018.04 # Real time elapsed on the host -sim_insts 243995320 # Number of instructions simulated -sim_ops 484985266 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2475904 # Number of bytes read from this memory +host_inst_rate 248874 # Simulator instruction rate (inst/s) +host_op_rate 494699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5246911955 # Simulator tick rate (ticks/s) +host_mem_usage 994832 # Number of bytes of host memory used +host_seconds 979.23 # Real time elapsed on the host +sim_insts 243705182 # Number of instructions simulated +sim_ops 484425104 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2466368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 403712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5648960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 122048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1730432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 426944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5894144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1789248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 439808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2919040 # Number of bytes read from this memory -system.physmem.bytes_read::total 13741824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 403712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 122048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 439808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 965568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9081216 # Number of bytes written to this memory -system.physmem.bytes_written::total 9081216 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38686 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu2.inst 385728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2633280 # Number of bytes read from this memory +system.physmem.bytes_read::total 13744640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 426944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 385728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 959872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9091584 # Number of bytes written to this memory +system.physmem.bytes_written::total 9091584 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38537 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6308 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 88265 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 27038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 92096 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2300 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 27957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6872 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 45610 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214716 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141894 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141894 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481891 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 6027 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41145 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214760 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142056 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142056 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 480030 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 78575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1099471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 23755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 336798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 83096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1147180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 348242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 85601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 568140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2674605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 78575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 23755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 85601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1767499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1767499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1767499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 75074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 512517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2675126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 83096 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 75074 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 186820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1769499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1769499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1769499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 480030 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 78575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1099471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 23755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 336798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 83096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1147180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 85601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 568140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4442104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 101962 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 77214 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 101962 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 77214 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 6525568 # Total number of bytes read from memory -system.physmem.bytesWritten 4941696 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6525568 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4941696 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 761 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 5804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 5639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6828 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4748 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5043 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4974 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4576 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4071 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4483 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4133 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5171 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 5136889044500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 101962 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 77214 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 78859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 669 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.bw_total::cpu2.inst 75074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 512517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4444625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 100936 # Number of read requests accepted +system.physmem.writeReqs 78380 # Number of write requests accepted +system.physmem.readBursts 100936 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 78380 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6458816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue +system.physmem.bytesWritten 5015040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6459904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5016320 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 699 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5898 # Per bank write bursts +system.physmem.perBankRdBursts::1 6403 # Per bank write bursts +system.physmem.perBankRdBursts::2 6411 # Per bank write bursts +system.physmem.perBankRdBursts::3 6523 # Per bank write bursts +system.physmem.perBankRdBursts::4 6306 # Per bank write bursts +system.physmem.perBankRdBursts::5 6840 # Per bank write bursts +system.physmem.perBankRdBursts::6 6199 # Per bank write bursts +system.physmem.perBankRdBursts::7 6896 # Per bank write bursts +system.physmem.perBankRdBursts::8 5528 # Per bank write bursts +system.physmem.perBankRdBursts::9 5898 # Per bank write bursts +system.physmem.perBankRdBursts::10 6128 # Per bank write bursts +system.physmem.perBankRdBursts::11 6570 # Per bank write bursts +system.physmem.perBankRdBursts::12 6317 # Per bank write bursts +system.physmem.perBankRdBursts::13 6334 # Per bank write bursts +system.physmem.perBankRdBursts::14 6542 # Per bank write bursts +system.physmem.perBankRdBursts::15 6126 # Per bank write bursts +system.physmem.perBankWrBursts::0 4721 # Per bank write bursts +system.physmem.perBankWrBursts::1 4902 # Per bank write bursts +system.physmem.perBankWrBursts::2 4923 # Per bank write bursts +system.physmem.perBankWrBursts::3 5159 # Per bank write bursts +system.physmem.perBankWrBursts::4 5192 # Per bank write bursts +system.physmem.perBankWrBursts::5 5457 # Per bank write bursts +system.physmem.perBankWrBursts::6 4843 # Per bank write bursts +system.physmem.perBankWrBursts::7 5797 # Per bank write bursts +system.physmem.perBankWrBursts::8 4085 # Per bank write bursts +system.physmem.perBankWrBursts::9 4367 # Per bank write bursts +system.physmem.perBankWrBursts::10 4807 # Per bank write bursts +system.physmem.perBankWrBursts::11 4903 # Per bank write bursts +system.physmem.perBankWrBursts::12 4884 # Per bank write bursts +system.physmem.perBankWrBursts::13 4699 # Per bank write bursts +system.physmem.perBankWrBursts::14 5116 # Per bank write bursts +system.physmem.perBankWrBursts::15 4505 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 5136941479000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 100936 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 78380 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 75816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -161,534 +163,549 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 349.964889 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.240831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1180.348858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14687 44.84% 44.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5019 15.32% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3032 9.26% 69.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2021 6.17% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1281 3.91% 79.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1132 3.46% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 832 2.54% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 693 2.12% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 503 1.54% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 527 1.61% 90.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 287 0.88% 91.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 266 0.81% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 203 0.62% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 195 0.60% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 197 0.60% 94.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 238 0.73% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 149 0.45% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 112 0.34% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 86 0.26% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 79 0.24% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 89 0.27% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 70 0.21% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 290 0.89% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 98 0.30% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 48 0.15% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 49 0.15% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 27 0.08% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 22 0.07% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 16 0.05% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 13 0.04% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 5 0.02% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 10 0.03% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 3 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 4 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 5 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 9 0.03% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 48 0.15% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 2 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 13 0.04% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 7 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 3 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 3 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 3 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 3 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 9 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 10 0.03% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 15 0.05% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 34 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17667 2 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32753 # Bytes accessed per row activation -system.physmem.totQLat 1954361749 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3940385499 # Sum of mem lat for all requests -system.physmem.totBusLat 509480000 # Total cycles spent in databus access -system.physmem.totBankLat 1476543750 # Total cycles spent in bank access -system.physmem.avgQLat 19179.97 # Average queueing delay per request -system.physmem.avgBankLat 14490.69 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38670.66 # Average memory access latency -system.physmem.avgRdBW 1.27 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.96 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.96 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.217991 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.094116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1121.662575 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16547 46.47% 46.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5535 15.54% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3551 9.97% 71.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2213 6.22% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1334 3.75% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1101 3.09% 85.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 807 2.27% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 584 1.64% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 515 1.45% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 517 1.45% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 309 0.87% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 309 0.87% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 205 0.58% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 200 0.56% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 177 0.50% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 272 0.76% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 139 0.39% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 84 0.24% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 95 0.27% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 94 0.26% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 81 0.23% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 178 0.50% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 83 0.23% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 58 0.16% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 45 0.13% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 38 0.11% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 29 0.08% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 19 0.05% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 15 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 14 0.04% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 11 0.03% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 8 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 6 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 5 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 5 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 8 0.02% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 3 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 5 0.01% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 6 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 6 0.02% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 4 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 3 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 4 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 3 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 20 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 2 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 2 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 2 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 2 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 3 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 3 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 3 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 12 0.03% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 6 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 10 0.03% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 3 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 5 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 9 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 8 0.02% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 29 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35607 # Bytes accessed per row activation +system.physmem.totQLat 2741683498 # Total ticks spent queuing +system.physmem.totMemAccLat 4643457248 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 504595000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1397178750 # Total ticks spent accessing banks +system.physmem.avgQLat 27167.17 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13844.56 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 46011.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.12 # Average write queue length over time -system.physmem.readRowHits 89443 # Number of row buffer hits during reads -system.physmem.writeRowHits 56909 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes -system.physmem.avgGap 28669515.14 # Average gap between requests -system.membus.throughput 6421183 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 424471 # Transaction distribution -system.membus.trans_dist::ReadResp 424470 # Transaction distribution -system.membus.trans_dist::WriteReq 6959 # Transaction distribution -system.membus.trans_dist::WriteResp 6959 # Transaction distribution -system.membus.trans_dist::Writeback 77214 # Transaction distribution -system.membus.trans_dist::UpgradeReq 768 # Transaction distribution -system.membus.trans_dist::UpgradeResp 768 # Transaction distribution -system.membus.trans_dist::ReadExReq 79729 # Transaction distribution -system.membus.trans_dist::ReadExResp 79729 # Transaction distribution -system.membus.trans_dist::MessageReq 903 # Transaction distribution -system.membus.trans_dist::MessageResp 903 # Transaction distribution +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing +system.physmem.readRowHits 85240 # Number of row buffer hits during reads +system.physmem.writeRowHits 58432 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes +system.physmem.avgGap 28647423.98 # Average gap between requests +system.physmem.pageHitRate 80.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6427951 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 423177 # Transaction distribution +system.membus.trans_dist::ReadResp 423176 # Transaction distribution +system.membus.trans_dist::WriteReq 6474 # Transaction distribution +system.membus.trans_dist::WriteResp 6474 # Transaction distribution +system.membus.trans_dist::Writeback 78380 # Transaction distribution +system.membus.trans_dist::UpgradeReq 714 # Transaction distribution +system.membus.trans_dist::UpgradeResp 714 # Transaction distribution +system.membus.trans_dist::ReadExReq 80216 # Transaction distribution +system.membus.trans_dist::ReadExResp 80216 # Transaction distribution +system.membus.trans_dist::MessageReq 892 # Transaction distribution +system.membus.trans_dist::MessageResp 892 # Transaction distribution system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497960 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 218608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 310648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497624 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 207711 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1028904 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 68108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1098818 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3612 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3612 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160445 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995917 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8655808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9812170 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2811456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2811456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12627238 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32732190 # Total data (bytes) -system.membus.snoop_data_through_bus 259136 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 164966500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::total 1015985 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 78748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 78748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1096517 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159467 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995245 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8228608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9383320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 3247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12634504 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32719620 # Total data (bytes) +system.membus.snoop_data_through_bus 306816 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 163512000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315386000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315210000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1806000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1784000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 820026249 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 830204748 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 903000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 892000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1636763940 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1595294481 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 218001500 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 252511249 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 103793 # number of replacements -system.l2c.tags.tagsinuse 64823.461690 # Cycle average of tags in use -system.l2c.tags.total_refs 3658744 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167885 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.793156 # Average number of references to valid blocks. +system.l2c.tags.replacements 103855 # number of replacements +system.l2c.tags.tagsinuse 64822.347448 # Cycle average of tags in use +system.l2c.tags.total_refs 3646219 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167877 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.719586 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51284.674060 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121869 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1299.911935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4544.856644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 221.437918 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1509.586927 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.216404 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003202 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1337.967786 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4616.684944 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782542 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51292.264352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121895 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1278.615227 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4499.945934 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 292.458405 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1505.357985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.212632 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1370.507166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4576.860668 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.782658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019835 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.069349 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000125 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.019510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.068664 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004463 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022970 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989128 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22091 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11658 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 334413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 510225 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10171 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 152259 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 227659 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 50814 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 351942 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 566551 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2254148 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu2.inst 0.020912 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.069837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989111 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 19693 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10326 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 346717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 513928 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10907 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 155624 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 47020 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 9087 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 331652 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 566093 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2240790 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1543420 # number of Writeback hits -system.l2c.Writeback_hits::total 1543420 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 83 # number of UpgradeReq hits +system.l2c.Writeback_hits::writebacks 1542501 # number of Writeback hits +system.l2c.Writeback_hits::total 1542501 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 57 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 69377 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 36565 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 61899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 167841 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22091 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11660 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 334413 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 579602 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10171 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5452 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 152259 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 264224 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 50814 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 351942 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 628450 # number of demand (read+write) hits -system.l2c.demand_hits::total 2421991 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22091 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11660 # number of overall hits -system.l2c.overall_hits::cpu0.inst 334413 # number of overall hits -system.l2c.overall_hits::cpu0.data 579602 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10171 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5452 # number of overall hits -system.l2c.overall_hits::cpu1.inst 152259 # number of overall hits -system.l2c.overall_hits::cpu1.data 264224 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 50814 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10913 # number of overall hits -system.l2c.overall_hits::cpu2.inst 351942 # number of overall hits -system.l2c.overall_hits::cpu2.data 628450 # number of overall hits -system.l2c.overall_hits::total 2421991 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 70841 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 36082 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 59675 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 166598 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 19693 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10328 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 346717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 584769 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5932 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 155624 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 259893 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 47020 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 9087 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 331652 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 625768 # number of demand (read+write) hits +system.l2c.demand_hits::total 2407390 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 19693 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10328 # number of overall hits +system.l2c.overall_hits::cpu0.inst 346717 # number of overall hits +system.l2c.overall_hits::cpu0.data 584769 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10907 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5932 # number of overall hits +system.l2c.overall_hits::cpu1.inst 155624 # number of overall hits +system.l2c.overall_hits::cpu1.data 259893 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 47020 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 9087 # number of overall hits +system.l2c.overall_hits::cpu2.inst 331652 # number of overall hits +system.l2c.overall_hits::cpu2.data 625768 # number of overall hits +system.l2c.overall_hits::total 2407390 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6308 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 16059 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1908 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3914 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 25 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6671 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 16268 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2301 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4539 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 22 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 6873 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 12824 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47916 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 775 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 221 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 356 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1352 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 72577 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 23336 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 33144 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 129057 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu2.inst 6029 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 11901 # number of ReadReq misses +system.l2c.ReadReq_misses::total 47736 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 761 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 281 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 269 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1311 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 76320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 23649 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 29451 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 129420 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6308 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 88636 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 27250 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 25 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6671 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 92588 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2301 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 28188 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 22 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 6873 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 45968 # number of demand (read+write) misses -system.l2c.demand_misses::total 176973 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 6029 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 41352 # number of demand (read+write) misses +system.l2c.demand_misses::total 177156 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6308 # number of overall misses -system.l2c.overall_misses::cpu0.data 88636 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses -system.l2c.overall_misses::cpu1.data 27250 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 25 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6671 # number of overall misses +system.l2c.overall_misses::cpu0.data 92588 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2301 # number of overall misses +system.l2c.overall_misses::cpu1.data 28188 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 22 # number of overall misses system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu2.inst 6873 # number of overall misses -system.l2c.overall_misses::cpu2.data 45968 # number of overall misses -system.l2c.overall_misses::total 176973 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 145483750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 305732245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2908500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 619386243 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1056307494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2129906982 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2658895 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 4530318 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7189213 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1598265396 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2458778359 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4057043755 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 145483750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1903997641 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2908500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 619386243 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3515085853 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6186950737 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 145483750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1903997641 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2908500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 619386243 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3515085853 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6186950737 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22091 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 11662 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 340721 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 526284 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10171 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5452 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 154167 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 231573 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 50839 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 10914 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 358815 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 579375 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2302064 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu2.inst 6029 # number of overall misses +system.l2c.overall_misses::cpu2.data 41352 # number of overall misses +system.l2c.overall_misses::total 177156 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 178484750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 352246744 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2002250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 488673998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 943243246 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1964725488 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 3587383 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 3136875 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 6724258 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1676320610 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2179701143 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3856021753 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 178484750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2028567354 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 2002250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 488673998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3122944389 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 5820747241 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 178484750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2028567354 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 2002250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 74500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 488673998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3122944389 # number of overall miss cycles +system.l2c.overall_miss_latency::total 5820747241 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 19693 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 10330 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 353388 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 530196 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10907 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 157925 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 228350 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 47042 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 9088 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 337681 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 577994 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2288526 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1543420 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1543420 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 890 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 277 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 439 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1606 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 141954 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 59901 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 95043 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296898 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22091 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 11664 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 340721 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 668238 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10171 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5452 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 154167 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 291474 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 50839 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 10914 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358815 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 674418 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2598964 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22091 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 11664 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 340721 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 668238 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10171 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5452 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 154167 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 291474 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 50839 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 10914 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358815 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 674418 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2598964 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000343 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.030514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.012376 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.016902 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000092 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.019155 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.022134 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020814 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.870787 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.797834 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.810934 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.841843 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.511271 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.389576 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.348726 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.434685 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000343 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018514 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.132641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.012376 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.093490 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000092 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.019155 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.068160 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.068094 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000343 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018514 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.132641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.012376 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.093490 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000092 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.019155 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.068160 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.068094 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76249.344864 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78112.479561 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 116340 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90118.760803 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 82369.580006 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 44450.851114 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12031.199095 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12725.612360 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5317.465237 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68489.261056 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74184.719979 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 31436.061237 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76249.344864 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69871.473064 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 116340 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 90118.760803 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 76468.105051 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 34959.856797 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76249.344864 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69871.473064 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 116340 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 90118.760803 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 76468.105051 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 34959.856797 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1542501 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1542501 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 900 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 339 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 326 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1565 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 147161 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 59731 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 89126 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296018 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 19693 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 10332 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 353388 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 677357 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 157925 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 288081 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 47042 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 9088 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 337681 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 667120 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2584546 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 19693 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 10332 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 353388 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 677357 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 157925 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 288081 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 47042 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 9088 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 337681 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 667120 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2584546 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000387 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018877 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.030683 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014570 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.019877 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000110 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.017854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.020590 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020859 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.845556 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828909 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.825153 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.837700 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.518616 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.395925 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.330442 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.437203 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000387 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018877 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.136690 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014570 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.097847 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000110 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.017854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.061986 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.068544 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000387 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018877 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.136690 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014570 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.097847 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000110 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.017854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.061986 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.068544 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77568.339852 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77604.482045 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 81053.905789 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 79257.478027 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 41158.150830 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12766.487544 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11661.245353 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5129.106026 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70883.361241 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74011.108044 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 29794.635705 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77568.339852 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71965.636228 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 81053.905789 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75520.999927 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 32856.619256 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77568.339852 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71965.636228 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 81053.905789 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75520.999927 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 32856.619256 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,131 +714,131 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95227 # number of writebacks -system.l2c.writebacks::total 95227 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.inst 1908 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3914 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 25 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 95389 # number of writebacks +system.l2c.writebacks::total 95389 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.inst 2301 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4539 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 22 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 6872 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 12824 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25544 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 221 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 356 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 577 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 23336 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 33144 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 56480 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1908 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 27250 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 25 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 6027 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 11901 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 24791 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 281 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 269 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 550 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 23649 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 29451 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 53100 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2301 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 28188 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 22 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 6872 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 45968 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 82024 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1908 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 27250 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 25 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 6027 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 41352 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 77891 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2301 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 28188 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 22 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 6872 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 45968 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 82024 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 121373750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 256053755 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 532537507 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 893917000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1806552262 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2360218 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3787353 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 6147571 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1304557104 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2042074099 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3346631203 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 121373750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1560610859 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 532537507 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2935991099 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5153183465 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 121373750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1560610859 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 532537507 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2935991099 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5153183465 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28189792500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30481780500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58671573000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 471155500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 768000500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1239156000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28660948000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31249781000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59910729000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.022134 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.011096 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.797834 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.810934 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.359278 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.389576 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348726 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.190234 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.093490 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.068160 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.031560 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.093490 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.068160 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.031560 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65419.968063 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 69706.565814 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 70723.154635 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10679.719457 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10638.632022 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10654.369151 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55903.201234 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61612.180153 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 59253.385322 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57270.123266 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63870.324987 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62825.312896 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57270.123266 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63870.324987 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62825.312896 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu2.inst 6027 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 41352 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 77891 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 149580250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 295478756 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 413107752 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 794213750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1654174258 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3410269 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 2847765 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 6258034 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1378867890 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1809513813 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3188381703 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 149580250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1674346646 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 413107752 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2603727563 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4842555961 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 149580250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1674346646 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 413107752 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2603727563 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4842555961 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28165267500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30426261500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58591529000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 495358500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 671313500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1166672000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28660626000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31097575000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59758201000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019877 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020590 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010833 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828909 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.825153 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.351438 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.395925 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.330442 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.179381 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.030137 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.030137 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65097.765147 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66735.043274 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 66724.789561 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12136.188612 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10586.486989 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11378.243636 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58305.547380 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61441.506672 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60044.853164 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -832,39 +849,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47570 # number of replacements -system.iocache.tags.tagsinuse 0.094174 # Cycle average of tags in use +system.iocache.tags.replacements 47575 # number of replacements +system.iocache.tags.tagsinuse 0.094274 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000166705009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094174 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005886 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005886 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5000200819009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094274 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005892 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131928771 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 131928771 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5225930177 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5225930177 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 5357858948 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5357858948 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 5357858948 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5357858948 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses +system.iocache.demand_misses::total 47630 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses +system.iocache.overall_misses::total 47630 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129801048 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 129801048 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6845673540 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6845673540 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6975474588 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6975474588 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6975474588 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6975474588 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -873,56 +890,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145777.647514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145777.647514 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 111856.382213 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 111856.382213 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 112500.975286 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 112500.975286 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 75733 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142638.514286 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 142638.514286 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 146525.546661 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 146525.546661 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 146451.282553 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 146451.282553 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 105453 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7002 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6453 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.815910 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.341702 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 739 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 23440 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 23440 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 24179 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 24179 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 24179 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 24179 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93470771 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93470771 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4006299177 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4006299177 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4099769948 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4099769948 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816575 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.816575 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.501712 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.501712 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.507696 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.507696 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126482.775372 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 126482.775372 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170917.200384 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 170917.200384 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 724 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 27280 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 27280 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 28004 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 28004 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 28004 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 28004 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92126548 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92126548 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 5426189542 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5426189542 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5518316090 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5518316090 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.795604 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.795604 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.583904 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.583904 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.587949 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.587949 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127246.613260 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127246.613260 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 198907.241276 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 198907.241276 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -936,459 +953,459 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52280174 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1811511 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1810976 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6959 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6959 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 914733 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 178384 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 154949 # Transaction distribution +system.toL2Bus.throughput 52188015 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1787129 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1786595 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 6474 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 6474 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 905502 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 665 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 665 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 176137 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 148862 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1025990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3658453 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 36523 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 129481 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4850447 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32830848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 121529738 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 130928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 488080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 154979594 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268493674 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 116064 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5106548110 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 991248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3625702 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34347 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 125379 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4776676 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31718784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120252184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 463592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152554720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268001344 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 137632 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5049278590 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 882000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2311338505 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2232669307 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4765806692 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4714355905 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 20170721 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19343965 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 68576287 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 67521559 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1274820 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 150850 # Transaction distribution -system.iobus.trans_dist::ReadResp 150850 # Transaction distribution -system.iobus.trans_dist::WriteReq 29496 # Transaction distribution -system.iobus.trans_dist::WriteResp 29496 # Transaction distribution -system.iobus.trans_dist::MessageReq 903 # Transaction distribution -system.iobus.trans_dist::MessageResp 903 # Transaction distribution +system.iobus.throughput 1276093 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 150466 # Transaction distribution +system.iobus.trans_dist::ReadResp 150466 # Transaction distribution +system.iobus.trans_dist::WriteReq 32862 # Transaction distribution +system.iobus.trans_dist::WriteResp 32862 # Transaction distribution +system.iobus.trans_dist::MessageReq 892 # Transaction distribution +system.iobus.trans_dist::MessageResp 892 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5804 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4556 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287488 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 552 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 500 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15072 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14980 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 312334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 48358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 48358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1806 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1806 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 362498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 310648 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 56008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 56008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1784 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1784 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 368440 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3277 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2572 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 17 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143595 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1000 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7490 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 160445 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1536536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1536536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1700593 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6549885 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2124548 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 159467 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1782176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1782176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1945211 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6556491 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2113460 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4801000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3772000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143745000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143596000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 436000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 394000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11266000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11170000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 213288448 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 248070339 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 306278000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 305066000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29307500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 32957751 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 903000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 892000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1216464910 # number of cpu cycles simulated +system.cpu0.numCycles 1184263733 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71961421 # Number of instructions committed -system.cpu0.committedOps 146368954 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134434152 # Number of integer alu accesses +system.cpu0.committedInsts 72124506 # Number of instructions committed +system.cpu0.committedOps 146682326 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134713165 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 983451 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14191112 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134434152 # number of integer instructions +system.cpu0.num_func_calls 981373 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14229217 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134713165 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 247103574 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115380288 # number of times the integer registers were written +system.cpu0.num_int_register_reads 247622256 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115606613 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83614520 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55784493 # number of times the CC registers were written -system.cpu0.num_mem_refs 14023782 # number of memory refs -system.cpu0.num_load_insts 10248970 # Number of load instructions -system.cpu0.num_store_insts 3774812 # Number of store instructions -system.cpu0.num_idle_cycles 1155422884.085227 # Number of idle cycles -system.cpu0.num_busy_cycles 61042025.914772 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050180 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949820 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 83816060 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55907358 # number of times the CC registers were written +system.cpu0.num_mem_refs 14049102 # number of memory refs +system.cpu0.num_load_insts 10253492 # Number of load instructions +system.cpu0.num_store_insts 3795610 # Number of store instructions +system.cpu0.num_idle_cycles 1123870108.492543 # Number of idle cycles +system.cpu0.num_busy_cycles 60393624.507457 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050997 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949003 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 853207 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.801369 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129244758 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 853719 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 151.390279 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147441059000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 310.509377 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 127.091120 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 73.200872 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.606464 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.248225 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.142970 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997659 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 87593978 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38906796 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2743984 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129244758 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87593978 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38906796 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2743984 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129244758 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87593978 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38906796 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2743984 # number of overall hits -system.cpu0.icache.overall_hits::total 129244758 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 340722 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 154167 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 378624 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 873513 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 340722 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 154167 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 378624 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 873513 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 340722 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 154167 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 378624 # number of overall misses -system.cpu0.icache.overall_misses::total 873513 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2138351750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5548047899 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7686399649 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2138351750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5548047899 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7686399649 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2138351750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5548047899 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7686399649 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87934700 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39060963 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3122608 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130118271 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87934700 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39060963 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3122608 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130118271 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87934700 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39060963 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3122608 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130118271 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003875 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003947 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121252 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006713 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003875 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003947 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121252 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006713 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003875 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003947 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121252 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006713 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13870.359740 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14653.186008 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8799.410712 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8799.410712 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8799.410712 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6480 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 848510 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.789516 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129618382 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 849022 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 152.667872 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147463418500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 302.993641 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 130.368033 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 77.427843 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.591784 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.254625 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.151226 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997636 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 87771297 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39145197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2701888 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129618382 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87771297 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39145197 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2701888 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129618382 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87771297 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39145197 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2701888 # number of overall hits +system.cpu0.icache.overall_hits::total 129618382 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 353389 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 157925 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 356099 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 867413 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 353389 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 157925 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 356099 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 867413 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 353389 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 157925 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 356099 # number of overall misses +system.cpu0.icache.overall_misses::total 867413 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2216316250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5093590204 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7309906454 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2216316250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5093590204 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7309906454 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2216316250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5093590204 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7309906454 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 88124686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39303122 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3057987 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130485795 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 88124686 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39303122 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3057987 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130485795 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 88124686 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39303122 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3057987 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130485795 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004010 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004018 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116449 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006648 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004010 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004018 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116449 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006648 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004010 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004018 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116449 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006648 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14033.979737 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14303.859893 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8427.250288 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8427.250288 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8427.250288 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4049 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 236 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.887967 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.156780 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 19783 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 19783 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 19783 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 19783 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 19783 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 19783 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 154167 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 358841 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 513008 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 154167 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 358841 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 513008 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 154167 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 358841 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 513008 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1829084250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4581098483 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6410182733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1829084250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4581098483 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6410182733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1829084250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4581098483 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6410182733 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003943 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.003943 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.003943 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12495.288052 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12495.288052 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12495.288052 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18382 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 18382 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 18382 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 18382 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 18382 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 18382 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 157925 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 337717 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 495642 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 157925 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 337717 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 495642 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 157925 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 337717 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 495642 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1899637750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4221033432 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6120671182 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1899637750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4221033432 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6120671182 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1899637750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4221033432 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6120671182 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003798 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003798 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003798 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.976039 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1633606 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999469 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19601664 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1634118 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.995256 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1632030 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997838 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19577218 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1632542 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.991862 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 202.875385 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 302.501214 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.622869 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.396241 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.590823 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012935 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5120812 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2495791 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3903609 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11520212 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3628684 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1642970 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2808111 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8079765 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8749496 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4138761 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6711720 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19599977 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8749496 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4138761 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6711720 # number of overall hits -system.cpu0.dcache.overall_hits::total 19599977 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 526284 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 231573 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 944815 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1702672 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 142844 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 60178 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 112298 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 315320 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 669128 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 291751 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1057113 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2017992 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 669128 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 291751 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1057113 # number of overall misses -system.cpu0.dcache.overall_misses::total 2017992 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3286416755 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15267347781 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18553764536 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2165300822 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3604529651 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5769830473 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5451717577 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 18871877432 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24323595009 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5451717577 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 18871877432 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24323595009 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5647096 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2727364 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4848424 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13222884 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3771528 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1703148 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2920409 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8395085 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9418624 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4430512 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7768833 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21617969 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9418624 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4430512 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7768833 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21617969 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093196 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.084907 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.194871 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037874 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035333 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.038453 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037560 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071043 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065850 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.136071 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093348 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071043 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065850 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136071 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093348 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14191.709547 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16159.086997 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10896.851852 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35981.601615 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32097.897122 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18298.333353 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18686.200140 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17852.280155 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12053.365429 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18686.200140 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17852.280155 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12053.365429 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 177204 # number of cycles access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 205.523243 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 299.707974 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.766620 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.401413 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.585367 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013216 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5112635 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2556554 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 3831407 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11500596 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3643791 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1689050 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2742153 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8074994 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8756426 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4245604 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6573560 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19575590 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8756426 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4245604 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6573560 # number of overall hits +system.cpu0.dcache.overall_hits::total 19575590 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 530196 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 228350 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 940486 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1699032 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 148061 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 60070 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 106578 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 314709 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 678257 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 288420 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1047064 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2013741 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 678257 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 288420 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1047064 # number of overall misses +system.cpu0.dcache.overall_misses::total 2013741 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3284093256 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15033857981 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18317951237 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2239487659 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3281341546 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5520829205 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5523580915 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 18315199527 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 23838780442 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5523580915 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 18315199527 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 23838780442 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5642831 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2784904 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4771893 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13199628 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3791852 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1749120 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2848731 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8389703 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9434683 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4534024 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7620624 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21589331 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9434683 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4534024 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7620624 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21589331 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093959 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081996 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.197089 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128718 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.039047 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034343 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037412 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037511 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071890 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.063612 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137399 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.093275 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071890 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063612 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137399 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.093275 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14381.840403 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.201248 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10781.404492 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37281.299467 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.169660 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17542.647986 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11838.056851 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11838.056851 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 171453 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11696 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11788 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.150821 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.544706 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1543420 # number of writebacks -system.cpu0.dcache.writebacks::total 1543420 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 365400 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 365400 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 16856 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 16856 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 382256 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 382256 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 382256 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 382256 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231573 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 579415 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 810988 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60178 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95442 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 155620 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 291751 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 674857 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 966608 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 291751 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 674857 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 966608 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2821426245 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8425862038 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11247288283 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2033592178 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3216384846 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5249977024 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4855018423 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11642246884 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16497265307 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4855018423 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11642246884 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16497265307 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30662990000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33250431500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63913421500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 506056500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 816755500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1322812000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31169046500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34067187000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65236233500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084907 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.119506 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061332 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035333 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032681 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018537 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044713 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044713 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12183.744413 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14542.015719 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13868.624792 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33792.950547 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33699.889420 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33735.876006 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1542501 # number of writebacks +system.cpu0.dcache.writebacks::total 1542501 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 362466 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362466 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17153 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17153 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 379619 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 379619 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 379619 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 379619 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 228350 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578020 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 806370 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60070 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89425 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 149495 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 288420 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 667445 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 955865 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 288420 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 667445 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 955865 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2826173744 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8314744809 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11140918553 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2108252341 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2905747700 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5014000041 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4934426085 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11220492509 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16154918594 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4934426085 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11220492509 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16154918594 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30636255000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33190282000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63826537000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 532271000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 712236000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1244507000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31168526000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33902518000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65071044000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081996 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121130 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061090 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031391 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017819 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.044275 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.044275 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.499864 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14384.873895 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13816.137199 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35096.592992 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32493.684093 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33539.583538 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1399,306 +1416,306 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606006645 # number of cpu cycles simulated +system.cpu1.numCycles 2606010326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35315213 # Number of instructions committed -system.cpu1.committedOps 68682433 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63797816 # Number of integer alu accesses +system.cpu1.committedInsts 35502902 # Number of instructions committed +system.cpu1.committedOps 69019443 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64128875 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 457734 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6497995 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63797816 # number of integer instructions +system.cpu1.num_func_calls 466888 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6511590 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64128875 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 117816925 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55078781 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118555351 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55341107 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36195960 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26980721 # number of times the CC registers were written -system.cpu1.num_mem_refs 4621452 # number of memory refs -system.cpu1.num_load_insts 2916499 # Number of load instructions -system.cpu1.num_store_insts 1704953 # Number of store instructions -system.cpu1.num_idle_cycles 2477007170.096548 # Number of idle cycles -system.cpu1.num_busy_cycles 128999474.903452 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049501 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950499 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 36337345 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27074895 # number of times the CC registers were written +system.cpu1.num_mem_refs 4724906 # number of memory refs +system.cpu1.num_load_insts 2973846 # Number of load instructions +system.cpu1.num_store_insts 1751060 # Number of store instructions +system.cpu1.num_idle_cycles 2477242501.972853 # Number of idle cycles +system.cpu1.num_busy_cycles 128767824.027147 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049412 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950588 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28832932 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28832932 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 311283 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26470595 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25835663 # Number of BTB hits +system.cpu2.branchPred.lookups 28668505 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28668505 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 293936 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26313496 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25716329 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.601369 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 539109 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63758 # Number of incorrect RAS predictions. -system.cpu2.numCycles 156318365 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.730568 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 531231 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 59742 # Number of incorrect RAS predictions. +system.cpu2.numCycles 154176343 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9648571 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142153316 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28832932 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26374772 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54477061 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1438031 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 74339 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 25017392 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 3513 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6379 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 22688 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3122610 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 142940 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 90361689 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.101501 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.407201 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9183670 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141279801 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28668505 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26247560 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54165747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1372429 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 60595 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 24017130 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 2633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7414 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 19025 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3057990 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 134510 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1720 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 88520588 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.147296 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.411069 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 36017869 39.86% 39.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 584325 0.65% 40.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23803917 26.34% 66.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 312236 0.35% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 599559 0.66% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 810629 0.90% 68.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 333254 0.37% 69.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 522143 0.58% 69.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27377757 30.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 34483261 38.96% 38.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 569039 0.64% 39.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23712203 26.79% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 303942 0.34% 66.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 596203 0.67% 67.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 791828 0.89% 68.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 321684 0.36% 68.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 518300 0.59% 69.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27224128 30.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 90361689 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184450 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.909383 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 11120847 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 23921754 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 35744474 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1291324 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1114642 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279457828 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 12 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1114642 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12111653 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14421944 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4371925 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 35874443 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5298501 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278479903 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 7178 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2457632 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2167618 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 332694530 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605890178 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 372281709 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 54 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 322791874 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9902651 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 146965 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 147763 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11459312 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6166984 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3428654 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 344111 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 288647 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276817235 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 412713 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 275284943 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 59120 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6994425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10714687 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 55194 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 90361689 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.046479 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.402703 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 88520588 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185946 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.916352 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10629848 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 22917593 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 30946726 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1286674 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1067388 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 277843876 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 5 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1067388 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11607450 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13707721 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4125990 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 31086433 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5253313 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 276918591 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6816 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2458805 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2129053 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 330941436 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 602250525 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 370032440 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321416172 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9525262 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 139074 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 139963 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11350220 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6069912 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3334552 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 325084 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 284462 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275324678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 401766 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273874447 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 58026 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6719880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10332541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 51920 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 88520588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.093907 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.392477 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26846835 29.71% 29.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6154250 6.81% 36.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3929000 4.35% 40.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2711977 3.00% 43.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25114660 27.79% 71.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1340428 1.48% 73.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23928680 26.48% 99.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 282970 0.31% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 52889 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 25429283 28.73% 28.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6033030 6.82% 35.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3870306 4.37% 39.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2690716 3.04% 42.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25010151 28.25% 71.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1323131 1.49% 72.70% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23827077 26.92% 99.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 285216 0.32% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 51678 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 90361689 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 88520588 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 125502 33.84% 33.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 241 0.06% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 190694 51.42% 85.33% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 54418 14.67% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 120453 33.21% 33.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 124 0.03% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 190037 52.39% 85.63% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 52134 14.37% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 78208 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 265424287 96.42% 96.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56044 0.02% 96.47% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 46278 0.02% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6463688 2.35% 98.83% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3216438 1.17% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 69880 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264196051 96.47% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 53857 0.02% 96.51% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 45427 0.02% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6378380 2.33% 98.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3130852 1.14% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 275284943 # Type of FU issued -system.cpu2.iq.rate 1.761053 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 370855 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001347 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641401400 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284227989 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273934511 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 90 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 102 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 273874447 # Type of FU issued +system.cpu2.iq.rate 1.776371 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 362748 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001325 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 636728050 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 282449613 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272560977 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 75 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275577549 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 41 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 638960 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 274167280 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 35 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 638144 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 974310 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6664 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4257 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 503319 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 933920 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 7005 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3826 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 481474 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656257 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10390 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656274 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10618 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1114642 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9684851 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 815798 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277229948 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 71784 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6166984 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3428654 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 232570 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 630862 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4638 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4257 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 175308 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 177843 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 353151 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 274790127 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6353973 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 494815 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9024497 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 812904 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275726444 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 67814 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6069912 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3334552 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 224273 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 631637 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3885 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3826 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 167894 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164610 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 332504 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273407129 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6276348 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 467317 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9504896 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27944071 # Number of branches executed -system.cpu2.iew.exec_stores 3150923 # Number of stores executed -system.cpu2.iew.exec_rate 1.757888 # Inst execution rate -system.cpu2.iew.wb_sent 274642284 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273934533 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213583516 # num instructions producing a value -system.cpu2.iew.wb_consumers 349233536 # num instructions consuming a value +system.cpu2.iew.exec_refs 9343774 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27815177 # Number of branches executed +system.cpu2.iew.exec_stores 3067426 # Number of stores executed +system.cpu2.iew.exec_rate 1.773340 # Inst execution rate +system.cpu2.iew.wb_sent 273265355 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272560999 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212629872 # num instructions producing a value +system.cpu2.iew.wb_consumers 347702126 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.752414 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611578 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.767852 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611529 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7294558 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357518 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 313650 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 89247046 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.024569 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.872131 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7002811 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 349846 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 295934 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 87453200 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.072767 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.870996 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 31615758 35.42% 35.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4405793 4.94% 40.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1230871 1.38% 41.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24727866 27.71% 69.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 857199 0.96% 70.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 581394 0.65% 71.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 343629 0.39% 71.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23391082 26.21% 97.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2093454 2.35% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 30168588 34.50% 34.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4310788 4.93% 39.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1198483 1.37% 40.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24616834 28.15% 68.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 847666 0.97% 69.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 576601 0.66% 70.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 339942 0.39% 70.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23302626 26.65% 97.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2091672 2.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 89247046 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136718686 # Number of instructions committed -system.cpu2.commit.committedOps 269933879 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 87453200 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136077774 # Number of instructions committed +system.cpu2.commit.committedOps 268723335 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8118007 # Number of memory references committed -system.cpu2.commit.loads 5192672 # Number of loads committed -system.cpu2.commit.membars 165488 # Number of memory barriers committed -system.cpu2.commit.branches 27614013 # Number of branches committed +system.cpu2.commit.refs 7989069 # Number of memory references committed +system.cpu2.commit.loads 5135991 # Number of loads committed +system.cpu2.commit.membars 163538 # Number of memory barriers committed +system.cpu2.commit.branches 27499066 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 246437097 # Number of committed integer instructions. -system.cpu2.commit.function_calls 432570 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2093454 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 245318960 # Number of committed integer instructions. +system.cpu2.commit.function_calls 428759 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2091672 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 364355237 # The number of ROB reads -system.cpu2.rob.rob_writes 555575410 # The number of ROB writes -system.cpu2.timesIdled 476451 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65956676 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4907452688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136718686 # Number of Instructions Simulated -system.cpu2.committedOps 269933879 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136718686 # Number of Instructions Simulated -system.cpu2.cpi 1.143358 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.143358 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.874617 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.874617 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 365607519 # number of integer regfile reads -system.cpu2.int_regfile_writes 219416427 # number of integer regfile writes +system.cpu2.rob.rob_reads 361063162 # The number of ROB reads +system.cpu2.rob.rob_writes 552523197 # The number of ROB writes +system.cpu2.timesIdled 466136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65655755 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4909695924 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136077774 # Number of Instructions Simulated +system.cpu2.committedOps 268723335 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 136077774 # Number of Instructions Simulated +system.cpu2.cpi 1.133002 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.133002 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.882611 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.882611 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363659019 # number of integer regfile reads +system.cpu2.int_regfile_writes 218348978 # number of integer regfile writes system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139623375 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107543298 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89002893 # number of misc regfile reads -system.cpu2.misc_regfile_writes 130765 # number of misc regfile writes +system.cpu2.cc_regfile_reads 138971726 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107072573 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88484504 # number of misc regfile reads +system.cpu2.misc_regfile_writes 124462 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 5d8366912..6e907f4cc 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026877 # Number of seconds simulated -sim_ticks 26877484000 # Number of ticks simulated -final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026913 # Number of seconds simulated +sim_ticks 26912680500 # Number of ticks simulated +final_tick 26912680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158705 # Simulator instruction rate (inst/s) -host_op_rate 159844 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47086787 # Simulator tick rate (ticks/s) -host_mem_usage 380172 # Number of bytes of host memory used -host_seconds 570.81 # Real time elapsed on the host +host_inst_rate 145850 # Simulator instruction rate (inst/s) +host_op_rate 146897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43329539 # Simulator tick rate (ticks/s) +host_mem_usage 407732 # Number of bytes of host memory used +host_seconds 621.12 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory -system.physmem.bytes_read::total 992384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 992384 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 876 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 896 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26877282500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15506 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 11153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::total 992896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1681289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35211951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36893241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1681289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1681289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1681289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35211951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36893241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15514 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 988 # Per bank write bursts +system.physmem.perBankRdBursts::1 886 # Per bank write bursts +system.physmem.perBankRdBursts::2 943 # Per bank write bursts +system.physmem.perBankRdBursts::3 1028 # Per bank write bursts +system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::5 1105 # Per bank write bursts +system.physmem.perBankRdBursts::6 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1078 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts +system.physmem.perBankRdBursts::9 956 # Per bank write bursts +system.physmem.perBankRdBursts::10 938 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::13 865 # Per bank write bursts +system.physmem.perBankRdBursts::14 877 # Per bank write bursts +system.physmem.perBankRdBursts::15 896 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 26912480500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 15514 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 11168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,90 +152,163 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3465.405018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 823.463699 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3831.282142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 22 7.89% 32.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 15 5.38% 37.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 12 4.30% 41.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 10 3.58% 45.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 2.15% 47.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2 0.72% 48.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 2 0.72% 49.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 4 1.43% 52.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1 0.36% 53.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1 0.36% 53.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1 0.36% 53.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 2 0.72% 54.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.36% 54.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.36% 55.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.72% 55.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.36% 56.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.36% 56.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.36% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation -system.physmem.totQLat 38456500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 288012750 # Sum of mem lat for all requests -system.physmem.totBusLat 77530000 # Total cycles spent in databus access -system.physmem.totBankLat 172026250 # Total cycles spent in bank access -system.physmem.avgQLat 2480.10 # Average queueing delay per request -system.physmem.avgBankLat 11094.17 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18574.28 # Average memory access latency -system.physmem.avgRdBW 36.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 36.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1603.423015 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 482.832317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2202.245443 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 156 25.28% 25.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 69 11.18% 36.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 40 6.48% 42.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 21 3.40% 46.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 12 1.94% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 0.97% 49.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 26 4.21% 53.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 13 2.11% 55.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.81% 56.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 9 1.46% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.65% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.65% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.81% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.30% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.49% 61.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.49% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.49% 64.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 19 3.08% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.49% 71.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.49% 72.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.49% 75.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.49% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.49% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.49% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.49% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.16% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.49% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.32% 83.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 3 0.49% 84.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.49% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.81% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.49% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 7 1.13% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 2 0.32% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.49% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.49% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.49% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.32% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 617 # Bytes accessed per row activation +system.physmem.totQLat 103133500 # Total ticks spent queuing +system.physmem.totMemAccLat 356414750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers +system.physmem.totBankLat 175711250 # Total ticks spent accessing banks +system.physmem.avgQLat 6647.77 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11325.98 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 22973.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15227 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 14897 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads +system.physmem.readRowHitRate 96.02 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1733347.25 # Average gap between requests -system.membus.throughput 36922504 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 968 # Transaction distribution -system.membus.trans_dist::ReadResp 968 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.physmem.avgGap 1734722.22 # Average gap between requests +system.physmem.pageHitRate 96.02 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.95 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36893241 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 976 # Transaction distribution +system.membus.trans_dist::ReadResp 976 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992384 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31028 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992896 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19247000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145153250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.branchPred.lookups 26677800 # Number of BP lookups -system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 841974 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11370900 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11281126 # Number of BTB hits +system.cpu.branchPred.lookups 26684421 # Number of BP lookups +system.cpu.branchPred.condPredicted 22003515 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 842640 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11361703 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11279248 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.210493 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69875 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 190 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.274273 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70578 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 175 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -277,134 +352,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53754969 # number of cpu cycles simulated +system.cpu.numCycles 53825362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14167360 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127859416 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26677800 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11351001 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24030535 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4760658 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11306613 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 14170521 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127888749 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26684421 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11349826 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24033756 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4765472 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11324127 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13839893 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329843 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53406892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410540 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13841798 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 328713 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53434811 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.409872 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214791 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29414657 55.08% 55.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389704 6.35% 61.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028213 3.80% 65.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1552667 2.91% 68.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1667858 3.12% 71.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2917621 5.46% 76.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1511775 2.83% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090045 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9834352 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29439353 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3386965 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028576 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1554110 2.91% 68.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1668608 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2917595 5.46% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1511603 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1091436 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9836565 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53406892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.496285 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.378560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16930336 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9153085 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22398033 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031812 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3893626 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442083 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8660 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126043342 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3893626 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18711323 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3589161 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 177598 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21546569 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5488615 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123125799 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 427703 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4597767 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499912232 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 925 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53434811 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495759 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.375994 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16934142 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9169646 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22402191 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031199 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3897633 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442994 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8719 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126071688 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42592 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3897633 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18714767 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3594336 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 187938 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21550636 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5489501 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123153089 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 427273 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4600360 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1278 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143605134 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536434214 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 500014017 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 784 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4613 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12549588 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29468785 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5519570 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2135216 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1252898 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118144684 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8486 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105149299 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26716988 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65524839 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 268 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53406892 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968834 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.909318 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36190948 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4612 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4610 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12546346 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29477793 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5522687 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2151443 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1269536 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118168344 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8478 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105154526 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78994 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26741749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65618769 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 260 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53434811 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908534 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15356551 28.75% 28.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11649216 21.81% 50.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8254544 15.46% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6822524 12.77% 78.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4944372 9.26% 88.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2950581 5.52% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2452903 4.59% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 533996 1.00% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442205 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15376938 28.78% 28.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11654897 21.81% 50.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8243564 15.43% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6824643 12.77% 78.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4966766 9.30% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2946722 5.51% 93.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2453138 4.59% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 526074 0.98% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442069 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53406892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53434811 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45764 6.91% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 341696 51.58% 58.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 274978 41.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45800 6.91% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340417 51.39% 58.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 276226 41.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74418524 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74421271 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -426,90 +501,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 156 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 210 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25604703 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5114728 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25608548 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5113387 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105149299 # Type of FU issued -system.cpu.iq.rate 1.956085 # Inst issue rate -system.cpu.iq.fu_busy_cnt 662465 # FU busy when requested +system.cpu.iq.FU_type_0::total 105154526 # Type of FU issued +system.cpu.iq.rate 1.953624 # Inst issue rate +system.cpu.iq.fu_busy_cnt 662470 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264446249 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144874513 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102679810 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 818 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1193 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 350 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105811363 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 401 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 442313 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 264484578 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144923147 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102682900 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 749 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 323 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105816623 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441366 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6894819 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6564 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6306 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 774726 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6903827 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6492 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6312 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 777843 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31505 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31495 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3893626 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 957081 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126869 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118165864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309166 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29468785 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5519570 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4598 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65994 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6719 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6306 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446848 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 444951 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891799 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104175749 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25286286 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 973550 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3897633 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 959563 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126871 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118189516 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 310121 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29477793 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5522687 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65719 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6709 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6312 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446751 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446217 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892968 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104180481 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25289750 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 974045 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12694 # number of nop insts executed -system.cpu.iew.exec_refs 30344072 # number of memory reference insts executed -system.cpu.iew.exec_branches 21323909 # Number of branches executed -system.cpu.iew.exec_stores 5057786 # Number of stores executed -system.cpu.iew.exec_rate 1.937974 # Inst execution rate -system.cpu.iew.wb_sent 102957516 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102680160 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62240823 # num instructions producing a value -system.cpu.iew.wb_consumers 104288348 # num instructions consuming a value +system.cpu.iew.exec_refs 30346354 # number of memory reference insts executed +system.cpu.iew.exec_branches 21325110 # Number of branches executed +system.cpu.iew.exec_stores 5056604 # Number of stores executed +system.cpu.iew.exec_rate 1.935528 # Inst execution rate +system.cpu.iew.wb_sent 102961531 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102683223 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62241416 # num instructions producing a value +system.cpu.iew.wb_consumers 104299638 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.910152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596815 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907711 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596756 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26915742 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26939491 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833391 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49513266 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.843000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540951 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834010 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49537178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540648 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20021121 40.44% 40.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13151741 26.56% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4165163 8.41% 75.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3429722 6.93% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1536672 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 726445 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 951437 1.92% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253528 0.51% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5277437 10.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20048697 40.47% 40.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13146284 26.54% 67.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4166513 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3429547 6.92% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533299 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 729419 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 954733 1.93% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253168 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275518 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49513266 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49537178 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -520,222 +595,218 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5277437 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275518 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162398797 # The number of ROB reads -system.cpu.rob.rob_writes 240250691 # The number of ROB writes -system.cpu.timesIdled 46136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 348077 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162448377 # The number of ROB reads +system.cpu.rob.rob_writes 240302265 # The number of ROB writes +system.cpu.timesIdled 46020 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 390551 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.593389 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.593389 # CPI: Total CPI of All Threads -system.cpu.ipc 1.685236 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.685236 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495533268 # number of integer regfile reads -system.cpu.int_regfile_writes 120542090 # number of integer regfile writes -system.cpu.fp_regfile_reads 173 # number of floating regfile reads -system.cpu.fp_regfile_writes 448 # number of floating regfile writes -system.cpu.misc_regfile_reads 29087390 # number of misc regfile reads +system.cpu.cpi 0.594166 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594166 # CPI: Total CPI of All Threads +system.cpu.ipc 1.683032 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.683032 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495553334 # number of integer regfile reads +system.cpu.int_regfile_writes 120547287 # number of integer regfile writes +system.cpu.fp_regfile_reads 170 # number of floating regfile reads +system.cpu.fp_regfile_writes 410 # number of floating regfile writes +system.cpu.misc_regfile_reads 29088502 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4497529557 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43698 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838143 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888541000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424134990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 633.195127 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13840808 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 732 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18908.207650 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits -system.cpu.icache.overall_hits::total 13838909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses -system.cpu.icache.overall_misses::total 983 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64555998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64555998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64555998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64555998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64555998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64555998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13839892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13839892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13839892 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13839892 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13839892 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13839892 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 633.195127 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.309177 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.309177 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13840808 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13840808 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13840808 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13840808 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13840808 # number of overall hits +system.cpu.icache.overall_hits::total 13840808 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 989 # number of overall misses +system.cpu.icache.overall_misses::total 989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66791248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66791248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66791248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66791248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66791248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66791248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13841797 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13841797 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13841797 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13841797 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13841797 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13841797 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65672.429298 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65672.429298 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65672.429298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65672.429298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65672.429298 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 629 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67534.123357 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67534.123357 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67534.123357 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67534.123357 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.900000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 54.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 729 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 729 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 729 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 729 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 729 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 729 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49190750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49190750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49190750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49190750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49190750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49190750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 256 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 256 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 256 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 256 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50590750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50590750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50590750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50590750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50590750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50590750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67477.023320 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67477.023320 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69018.758527 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69018.758527 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10730.387703 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831429 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.179583 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942919 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942919 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 9881.039169 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 619.212620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 230.135914 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.301545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018897 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007023 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.327465 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903638 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903662 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 29198 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 29198 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932813 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932836 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932813 # number of overall hits -system.cpu.l2cache.overall_hits::total 932836 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 703 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 979 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 29160 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 29160 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932798 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932822 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932798 # number of overall hits +system.cpu.l2cache.overall_hits::total 932822 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 987 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 703 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15517 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 703 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses -system.cpu.l2cache.overall_misses::total 15517 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48235000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19323500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 67558500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 897218750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 897218750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48235000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 916542250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 964777250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 48235000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 916542250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 964777250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 726 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903891 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904617 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942919 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942919 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43736 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43736 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 726 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947627 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948353 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 726 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947627 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948353 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968320 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000305 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001082 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332404 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.332404 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968320 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016362 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968320 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016362 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.086771 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70012.681159 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69007.660878 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61715.418214 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61715.418214 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68613.086771 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61870.004725 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62175.501063 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68613.086771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61870.004725 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62175.501063 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15525 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses +system.cpu.l2cache.overall_misses::total 15525 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49612500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21119250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70731750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962947000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 962947000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 49612500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 984066250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1033678750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 49612500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 984066250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1033678750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 732 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903917 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904649 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942911 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942911 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43698 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43698 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 732 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947615 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948347 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 732 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947615 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948347 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967213 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332693 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.332693 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967213 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016371 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967213 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016371 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70074.152542 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75696.236559 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71663.373860 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66236.552483 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66236.552483 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66581.561997 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66581.561997 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,184 +824,176 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 702 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 266 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 976 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 702 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15506 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 702 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15506 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39349250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15357000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54706250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714814750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714814750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39349250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730171750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 769521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39349250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730171750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 769521000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001070 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332404 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332404 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016350 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.966942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016350 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56053.062678 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57733.082707 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56514.721074 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49168.713028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49168.713028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40706750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17150500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57857250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780571000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780571000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40706750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797721500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 838428250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40706750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797721500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 838428250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001079 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332693 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332693 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57576.732673 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63756.505576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59279.969262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53691.773284 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53691.773284 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943531 # number of replacements -system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532905 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3915 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3915 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 943519 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.753264 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28141899 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947615 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.697608 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8006034000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.753264 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896424 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23601231 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23601231 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532867 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532867 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28130035 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28130035 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28130035 # number of overall hits -system.cpu.dcache.overall_hits::total 28130035 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173788 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173788 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202076 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1375864 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1375864 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1375864 # number of overall misses -system.cpu.dcache.overall_misses::total 1375864 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887695479 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13887695479 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7918602355 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7918602355 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 251250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21806297834 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21806297834 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21806297834 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21806297834 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24770918 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24770918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 28134098 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28134098 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28134098 # number of overall hits +system.cpu.dcache.overall_hits::total 28134098 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173780 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173780 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202114 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202114 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1375894 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1375894 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1375894 # number of overall misses +system.cpu.dcache.overall_misses::total 1375894 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893621478 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13893621478 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458573839 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8458573839 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22352195317 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22352195317 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22352195317 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22352195317 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24775011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24775011 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3923 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3917 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29505899 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29505899 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29505899 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29505899 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047386 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047386 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042677 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042677 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002039 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002039 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046630 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046630 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046630 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046630 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.519388 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.519388 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39186.258413 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39186.258413 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31406.250000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31406.250000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15849.166657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15849.166657 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15849.166657 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154131 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29509992 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29509992 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29509992 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29509992 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047378 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047378 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042685 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042685 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.648672 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.648672 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41850.509312 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41850.509312 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16245.579468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16245.579468 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154256 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23950 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.435532 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.440483 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942919 # number of writebacks -system.cpu.dcache.writebacks::total 942919 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269877 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269877 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158357 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158357 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428234 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428234 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428234 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428234 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903911 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903911 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43719 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43719 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947630 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947630 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947630 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947630 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9992457010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9992457010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254142688 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254142688 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11246599698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11246599698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11246599698 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11246599698 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009233 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009233 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.691236 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.691236 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28686.444978 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28686.444978 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11868.133869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11868.133869 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks +system.cpu.dcache.writebacks::total 942911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269842 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269842 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158436 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158436 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 428278 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428278 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428278 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428278 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903938 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903938 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43678 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43678 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947616 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947616 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947616 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947616 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994572760 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994572760 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319332173 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319332173 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313904933 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11313904933 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313904933 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11313904933 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.701632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.701632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30205.874193 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30205.874193 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 3b6f53bfa..1149689b6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,102 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065497 # Number of seconds simulated -sim_ticks 65497052500 # Number of ticks simulated -final_tick 65497052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065614 # Number of seconds simulated +sim_ticks 65613727000 # Number of ticks simulated +final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99498 # Simulator instruction rate (inst/s) -host_op_rate 175200 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41248682 # Simulator tick rate (ticks/s) -host_mem_usage 388584 # Number of bytes of host memory used -host_seconds 1587.86 # Real time elapsed on the host +host_inst_rate 90206 # Simulator instruction rate (inst/s) +host_op_rate 158838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37463203 # Simulator tick rate (ticks/s) +host_mem_usage 416624 # Number of bytes of host memory used +host_seconds 1751.42 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 63296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882240 # Number of bytes read from this memory -system.physmem.bytes_read::total 1945536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9984 # Number of bytes written to this memory -system.physmem.bytes_written::total 9984 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29410 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30399 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 156 # Number of write requests responded to by this memory -system.physmem.num_writes::total 156 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 966395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28737782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29704176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 966395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 966395 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 152434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 152434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 152434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 966395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28737782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29856611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30400 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 156 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 30400 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 156 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 1945536 # Total number of bytes read from memory -system.physmem.bytesWritten 9984 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1945536 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9984 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1932 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1820 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65497035500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30400 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 156 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory +system.physmem.bytes_written::total 10688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 167 # Number of write requests responded to by this memory +system.physmem.num_writes::total 167 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 969553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28700336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29669889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 969553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 969553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 162893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 162893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 162893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 969553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28700336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29832782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30419 # Number of read requests accepted +system.physmem.writeReqs 167 # Number of write requests accepted +system.physmem.readBursts 30419 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 167 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2880 # Total number of bytes read from write queue +system.physmem.bytesWritten 9856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1946816 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 45 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1928 # Per bank write bursts +system.physmem.perBankRdBursts::1 2077 # Per bank write bursts +system.physmem.perBankRdBursts::2 2029 # Per bank write bursts +system.physmem.perBankRdBursts::3 1927 # Per bank write bursts +system.physmem.perBankRdBursts::4 2026 # Per bank write bursts +system.physmem.perBankRdBursts::5 1899 # Per bank write bursts +system.physmem.perBankRdBursts::6 1963 # Per bank write bursts +system.physmem.perBankRdBursts::7 1862 # Per bank write bursts +system.physmem.perBankRdBursts::8 1939 # Per bank write bursts +system.physmem.perBankRdBursts::9 1933 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts +system.physmem.perBankRdBursts::11 1795 # Per bank write bursts +system.physmem.perBankRdBursts::12 1792 # Per bank write bursts +system.physmem.perBankRdBursts::13 1800 # Per bank write bursts +system.physmem.perBankRdBursts::14 1821 # Per bank write bursts +system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankWrBursts::0 15 # Per bank write bursts +system.physmem.perBankWrBursts::1 95 # Per bank write bursts +system.physmem.perBankWrBursts::2 7 # Per bank write bursts +system.physmem.perBankWrBursts::3 11 # Per bank write bursts +system.physmem.perBankWrBursts::4 6 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 12 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 5 # Per bank write bursts +system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 65613689500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 30419 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 167 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -125,29 +127,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -157,331 +159,386 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3610.915888 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 887.471357 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3852.235562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 128 23.93% 23.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 47 8.79% 32.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 24 4.49% 37.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 12 2.24% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 11 2.06% 41.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11 2.06% 43.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8 1.50% 45.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 3 0.56% 45.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.68% 47.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.87% 49.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2 0.37% 49.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 7 1.31% 50.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1 0.19% 51.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.56% 51.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.56% 52.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.19% 52.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 9 1.68% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.37% 54.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.19% 54.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.19% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.19% 54.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.37% 55.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.19% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.19% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.37% 56.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.19% 56.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.37% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.19% 56.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.19% 57.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.19% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.37% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.19% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.19% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.19% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.19% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.19% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.37% 58.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.19% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.37% 59.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.19% 59.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.19% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 215 40.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 535 # Bytes accessed per row activation -system.physmem.totQLat 5969250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 581474250 # Sum of mem lat for all requests -system.physmem.totBusLat 151785000 # Total cycles spent in databus access -system.physmem.totBankLat 423720000 # Total cycles spent in bank access -system.physmem.avgQLat 196.64 # Average queueing delay per request -system.physmem.avgBankLat 13957.90 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19154.54 # Average memory access latency -system.physmem.avgRdBW 29.70 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.70 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1527.767843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 562.023414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1657.823974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 326 25.57% 25.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 105 8.24% 33.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 43 3.37% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 28 2.20% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 22 1.73% 41.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 22 1.73% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 19 1.49% 44.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 15 1.18% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 17 1.33% 46.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 13 1.02% 47.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 46 3.61% 51.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 12 0.94% 52.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 8 0.63% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 7 0.55% 53.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 12 0.94% 54.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 11 0.86% 55.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 8 0.63% 56.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 16 1.25% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 7 0.55% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 9 0.71% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 9 0.71% 59.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 7 0.55% 59.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 11 0.86% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 6 0.47% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 14 1.10% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 4 0.31% 62.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 9 0.71% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 6 0.47% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 3 0.24% 63.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 12 0.94% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 12 0.94% 65.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 8 0.63% 66.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 32 2.51% 68.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 7 0.55% 69.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 7 0.55% 70.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 5 0.39% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 6 0.47% 70.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 10 0.78% 71.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 5 0.39% 72.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 7 0.55% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 3 0.24% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 9 0.71% 73.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 7 0.55% 74.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 6 0.47% 74.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 5 0.39% 74.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 11 0.86% 75.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 9 0.71% 76.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 7 0.55% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 5 0.39% 77.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 5 0.39% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 8 0.63% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 11 0.86% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 9 0.71% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 10 0.78% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 12 0.94% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 15 1.18% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 10 0.78% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 14 1.10% 84.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 9 0.71% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 8 0.63% 86.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 8 0.63% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 15 1.18% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 13 1.02% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 11 0.86% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 21 1.65% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 10 0.78% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 6 0.47% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 7 0.55% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 4 0.31% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 5 0.39% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 4 0.31% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 4 0.31% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 6 0.47% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 7 0.55% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 5 0.39% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 6 0.47% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 5 0.39% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 6 0.47% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 5 0.39% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 6 0.47% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 4 0.31% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 2 0.16% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 2 0.16% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 2 0.16% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 2 0.16% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 1 0.08% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 1 0.08% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 1 0.08% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 1 0.08% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 1 0.08% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 1 0.08% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592 1 0.08% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656 3 0.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1275 # Bytes accessed per row activation +system.physmem.totQLat 92483500 # Total ticks spent queuing +system.physmem.totMemAccLat 678771000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers +system.physmem.totBankLat 434417500 # Total ticks spent accessing banks +system.physmem.avgQLat 3044.82 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14302.28 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 22347.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 12.39 # Average write queue length over time -system.physmem.readRowHits 29864 # Number of row buffer hits during reads -system.physmem.writeRowHits 96 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.54 # Row buffer hit rate for writes -system.physmem.avgGap 2143508.17 # Average gap between requests -system.membus.throughput 29855634 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1399 # Transaction distribution -system.membus.trans_dist::ReadResp 1397 # Transaction distribution -system.membus.trans_dist::Writeback 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 29001 # Transaction distribution -system.membus.trans_dist::ReadExResp 29001 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60954 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1955456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1955456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1955456 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1955456 # Total data (bytes) +system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.96 # Average write queue length when enqueuing +system.physmem.readRowHits 29156 # Number of row buffer hits during reads +system.physmem.writeRowHits 97 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes +system.physmem.avgGap 2145219.69 # Average gap between requests +system.physmem.pageHitRate 95.78 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.92 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 29832782 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1416 # Transaction distribution +system.membus.trans_dist::ReadResp 1415 # Transaction distribution +system.membus.trans_dist::Writeback 167 # Transaction distribution +system.membus.trans_dist::ReadExReq 29003 # Transaction distribution +system.membus.trans_dist::ReadExResp 29003 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1957440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35006500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284183250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.branchPred.lookups 33858224 # Number of BP lookups -system.cpu.branchPred.condPredicted 33858224 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774589 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19295548 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19203800 # Number of BTB hits +system.cpu.branchPred.lookups 33859770 # Number of BP lookups +system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.524512 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5017950 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5443 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 130994109 # number of cpu cycles simulated +system.cpu.numCycles 131227460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26134025 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182258914 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33858224 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24221750 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55458228 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5352681 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44757241 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 354 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 26135230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182265293 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33859770 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24219454 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55459629 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5354571 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44982751 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25574362 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166199 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 130892614 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.454818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314961 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 25575393 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166244 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131122211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.450609 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313707 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77910684 59.52% 59.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1961091 1.50% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2941416 2.25% 63.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3833946 2.93% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7767539 5.93% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757616 3.63% 75.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2666164 2.04% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316720 1.01% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27737438 21.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78139546 59.59% 59.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1960111 1.49% 61.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2942175 2.24% 63.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3833696 2.92% 66.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7767416 5.92% 72.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757872 3.63% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2665225 2.03% 77.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316047 1.00% 78.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27740123 21.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 130892614 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258471 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.391352 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36819659 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36980368 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43894473 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8655405 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4542709 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318839804 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4542709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42306626 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9548363 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7363 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46754553 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27733000 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 314999780 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25879667 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 317173158 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836491506 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 515038229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131122211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258024 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.388926 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36831320 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37195756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43906245 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8644656 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4544234 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318852911 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4544234 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42322552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9742718 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7418 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46754999 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27750290 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 315016174 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 215 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26317 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25895473 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 317188133 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836523485 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 515056961 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 484 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37960411 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 483 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62657657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101560400 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34776362 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39636404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5873969 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311477073 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1619 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300261813 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 90477 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32704303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46143152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1174 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 130892614 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.293955 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698909 # Number of insts issued each cycle +system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24143436 18.45% 18.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23235636 17.75% 36.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25474582 19.46% 55.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25828603 19.73% 75.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18887958 14.43% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8220714 6.28% 96.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3961121 3.03% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 955436 0.73% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 185128 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 130892614 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31366 1.52% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1915737 93.06% 94.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 111488 5.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169828970 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11213 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97302750 32.41% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33087237 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300261813 # Type of FU issued -system.cpu.iq.rate 2.292178 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2058591 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733564971 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344215080 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298003281 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 337 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 435 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 126 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302288959 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 169 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54190051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued +system.cpu.iq.rate 2.288206 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10781015 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32177 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33336 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3336610 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3220 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4542709 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2622554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162089 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311478692 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 196017 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101560400 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34776362 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 469 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2626 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33336 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393441 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427689 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 821130 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298856938 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96890588 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1404875 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129814899 # number of memory reference insts executed -system.cpu.iew.exec_branches 30818444 # Number of branches executed -system.cpu.iew.exec_stores 32924311 # Number of stores executed -system.cpu.iew.exec_rate 2.281453 # Inst execution rate -system.cpu.iew.wb_sent 298373185 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298003407 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218253384 # num instructions producing a value -system.cpu.iew.wb_consumers 296750864 # num instructions consuming a value +system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed +system.cpu.iew.exec_branches 30820824 # Number of branches executed +system.cpu.iew.exec_stores 32925944 # Number of stores executed +system.cpu.iew.exec_rate 2.277516 # Inst execution rate +system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218260008 # num instructions producing a value +system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.274937 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735477 # average fanout of values written-back +system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33298978 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774634 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126349905 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.201762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.972659 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58072656 45.96% 45.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19155409 15.16% 61.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11632100 9.21% 70.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9445412 7.48% 77.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1855076 1.47% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2067896 1.64% 80.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1301136 1.03% 81.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 691741 0.55% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22128479 17.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11719383 9.26% 70.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9409192 7.43% 77.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1839491 1.45% 79.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2078967 1.64% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1287907 1.02% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 695737 0.55% 82.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22125649 17.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126349905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126577977 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -492,214 +549,214 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22128479 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415712868 # The number of ROB reads -system.cpu.rob.rob_writes 627529396 # The number of ROB writes -system.cpu.timesIdled 13705 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101495 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415950983 # The number of ROB reads +system.cpu.rob.rob_writes 627545403 # The number of ROB writes +system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.829137 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829137 # CPI: Total CPI of All Threads -system.cpu.ipc 1.206074 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.206074 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483722109 # number of integer regfile reads -system.cpu.int_regfile_writes 234582139 # number of integer regfile writes -system.cpu.fp_regfile_reads 117 # number of floating regfile reads -system.cpu.fp_regfile_writes 75 # number of floating regfile writes -system.cpu.cc_regfile_reads 107053198 # number of cc regfile reads -system.cpu.cc_regfile_writes 64000024 # number of cc regfile writes -system.cpu.misc_regfile_reads 191821503 # number of misc regfile reads +system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads +system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 483744134 # number of integer regfile reads +system.cpu.int_regfile_writes 234595253 # number of integer regfile writes +system.cpu.fp_regfile_reads 141 # number of floating regfile reads +system.cpu.fp_regfile_writes 77 # number of floating regfile writes +system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads +system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes +system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4049501312 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82299 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2012 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219810 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265166016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265230400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265230400 # Total data (bytes) +system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6220108 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6222130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265183808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265248512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265248512 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138743500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4139141500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1699750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1689999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3122104250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3122002000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 55 # number of replacements -system.cpu.icache.tags.tagsinuse 816.683247 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25573067 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1006 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25420.543738 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 57 # number of replacements +system.cpu.icache.tags.tagsinuse 819.642194 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25574088 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1011 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25295.833828 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 816.683247 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.398771 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.398771 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25573067 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25573067 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25573067 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25573067 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25573067 # number of overall hits -system.cpu.icache.overall_hits::total 25573067 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses -system.cpu.icache.overall_misses::total 1295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 85604250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 85604250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 85604250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 85604250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 85604250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 85604250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25574362 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25574362 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25574362 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25574362 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25574362 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25574362 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 819.642194 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.400216 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.400216 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25574088 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25574088 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25574088 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25574088 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25574088 # number of overall hits +system.cpu.icache.overall_hits::total 25574088 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1305 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1305 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1305 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses +system.cpu.icache.overall_misses::total 1305 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25575393 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25575393 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25575393 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66103.667954 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66103.667954 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66103.667954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66103.667954 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 289 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 289 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 289 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 289 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1006 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1006 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1006 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1006 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1006 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1006 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67541250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 67541250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67541250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 67541250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67541250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 67541250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67138.419483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67138.419483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 294 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 294 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 294 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 294 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 294 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 294 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1011 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1011 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1011 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 461 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20819.547231 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4029398 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30381 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.628880 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 479 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4029616 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30401 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.548798 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19905.791561 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.283783 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 246.471887 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.607477 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007522 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.635362 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 19891.107618 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 670.515764 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 244.870550 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.607028 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020463 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007473 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.634964 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993882 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993899 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2066630 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2066630 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53298 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53298 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993866 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993883 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066887 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066887 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53320 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53320 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2047180 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2047197 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2047186 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2047203 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2047180 # number of overall hits -system.cpu.l2cache.overall_hits::total 2047197 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1399 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 989 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29411 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30400 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 989 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29411 # number of overall misses -system.cpu.l2cache.overall_misses::total 30400 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 66362250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27817000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94179250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1783074500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1783074500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 66362250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1810891500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1877253750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 66362250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1810891500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1877253750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1006 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1994292 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995298 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2066630 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2066630 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82299 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82299 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1006 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076591 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077597 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1006 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076591 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077597 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983101 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000206 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000701 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352386 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352386 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983101 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014163 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014632 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983101 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014163 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014632 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67100.353893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67846.341463 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67318.977841 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61483.207476 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61483.207476 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67100.353893 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61571.911870 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61751.768092 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67100.353893 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61571.911870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61751.768092 # average overall miss latency +system.cpu.l2cache.overall_hits::cpu.data 2047186 # number of overall hits +system.cpu.l2cache.overall_hits::total 2047203 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 994 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1416 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 29003 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29003 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 994 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29425 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30419 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses +system.cpu.l2cache.overall_misses::total 30419 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1011 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076611 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077622 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1011 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076611 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077622 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983185 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000212 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000710 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352307 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352307 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983185 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014641 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -708,160 +765,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 156 # number of writebacks -system.cpu.l2cache.writebacks::total 156 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 989 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 410 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1399 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 989 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29411 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30400 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 989 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29411 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30400 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53927250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22692500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 76619750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1417840500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1417840500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53927250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1440533000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1494460250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53927250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1440533000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1494460250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000206 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352386 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352386 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014632 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014632 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54527.047523 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55347.560976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54767.512509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48889.365884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48889.365884 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 167 # number of writebacks +system.cpu.l2cache.writebacks::total 167 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 994 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1416 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29003 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29003 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 994 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30419 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 994 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30419 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55574500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24773500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80348000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1511756500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1511756500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55574500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1536530000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1592104500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55574500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1536530000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1592104500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55909.959759 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58704.976303 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56742.937853 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52124.142330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52124.142330 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072493 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.881910 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71371808 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076589 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.369732 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20650704250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.881910 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40030061 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40030061 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341747 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71371808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71371808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71371808 # number of overall hits -system.cpu.dcache.overall_hits::total 71371808 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2626396 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2626396 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98005 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98005 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2724401 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2724401 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2724401 # number of overall misses -system.cpu.dcache.overall_misses::total 2724401 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31387330250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31387330250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2685755248 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2685755248 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34073085498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34073085498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34073085498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34073085498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42656457 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42656457 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 2072514 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits +system.cpu.dcache.overall_hits::total 71413624 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98059 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2723805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2723805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2723805 # number of overall misses +system.cpu.dcache.overall_misses::total 2723805 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399016250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31399016250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2779679498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2779679498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74096209 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74096209 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74096209 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74096209 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061571 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061571 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003117 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003117 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036768 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036768 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036768 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036768 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11950.722682 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11950.722682 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27404.267619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27404.267619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12506.633751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12506.633751 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32988 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036740 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036740 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036740 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036740 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.131613 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.131613 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28347.010453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28347.010453 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12548.143405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12548.143405 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32707 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.476080 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443930 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066630 # number of writebacks -system.cpu.dcache.writebacks::total 2066630 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631996 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631996 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15814 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15814 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647810 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647810 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647810 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647810 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994400 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994400 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82191 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82191 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076591 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076591 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076591 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076591 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994515250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994515250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397679498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397679498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392194748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24392194748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392194748 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24392194748 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046755 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046755 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028026 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.136407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.136407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29172.044360 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29172.044360 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2066887 # number of writebacks +system.cpu.dcache.writebacks::total 2066887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631351 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631351 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15843 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15843 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647194 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647194 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994395 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994395 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076611 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076611 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076611 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076611 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996462750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996462750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2491650748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2491650748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488113498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24488113498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488113498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24488113498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028010 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028010 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.140541 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.140541 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30306.153887 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30306.153887 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 76f42f35e..293b4caca 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202350 # Number of seconds simulated -sim_ticks 202349747500 # Number of ticks simulated -final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202724 # Number of seconds simulated +sim_ticks 202723760000 # Number of ticks simulated +final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125600 # Simulator instruction rate (inst/s) -host_op_rate 141606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50303215 # Simulator tick rate (ticks/s) -host_mem_usage 251352 # Number of bytes of host memory used -host_seconds 4022.61 # Real time elapsed on the host +host_inst_rate 119496 # Simulator instruction rate (inst/s) +host_op_rate 134724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47946894 # Simulator tick rate (ticks/s) +host_mem_usage 278932 # Number of bytes of host memory used +host_seconds 4228.09 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9268224 # Number of bytes read from this memory -system.physmem.bytes_read::total 9485120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6250688 # Number of bytes written to this memory -system.physmem.bytes_written::total 6250688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144816 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148205 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97667 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97667 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1071887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45802993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46874879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1071887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1071887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30890515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30890515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30890515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148206 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 97667 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 148206 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 97667 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 9485120 # Total number of bytes read from memory -system.physmem.bytesWritten 6250688 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9807 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8806 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9453 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5891 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5812 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5895 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6360 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6066 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6146 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry -system.physmem.totGap 202349728000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148206 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97667 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory +system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory +system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148203 # Number of read requests accepted +system.physmem.writeReqs 97674 # Number of write requests accepted +system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue +system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9589 # Per bank write bursts +system.physmem.perBankRdBursts::1 9263 # Per bank write bursts +system.physmem.perBankRdBursts::2 9230 # Per bank write bursts +system.physmem.perBankRdBursts::3 8983 # Per bank write bursts +system.physmem.perBankRdBursts::4 9781 # Per bank write bursts +system.physmem.perBankRdBursts::5 9608 # Per bank write bursts +system.physmem.perBankRdBursts::6 9123 # Per bank write bursts +system.physmem.perBankRdBursts::7 8333 # Per bank write bursts +system.physmem.perBankRdBursts::8 8801 # Per bank write bursts +system.physmem.perBankRdBursts::9 8921 # Per bank write bursts +system.physmem.perBankRdBursts::10 8939 # Per bank write bursts +system.physmem.perBankRdBursts::11 9732 # Per bank write bursts +system.physmem.perBankRdBursts::12 9670 # Per bank write bursts +system.physmem.perBankRdBursts::13 9771 # Per bank write bursts +system.physmem.perBankRdBursts::14 8945 # Per bank write bursts +system.physmem.perBankRdBursts::15 9431 # Per bank write bursts +system.physmem.perBankWrBursts::0 6268 # Per bank write bursts +system.physmem.perBankWrBursts::1 6168 # Per bank write bursts +system.physmem.perBankWrBursts::2 6085 # Per bank write bursts +system.physmem.perBankWrBursts::3 5885 # Per bank write bursts +system.physmem.perBankWrBursts::4 6259 # Per bank write bursts +system.physmem.perBankWrBursts::5 6263 # Per bank write bursts +system.physmem.perBankWrBursts::6 6041 # Per bank write bursts +system.physmem.perBankWrBursts::7 5560 # Per bank write bursts +system.physmem.perBankWrBursts::8 5811 # Per bank write bursts +system.physmem.perBankWrBursts::9 5905 # Per bank write bursts +system.physmem.perBankWrBursts::10 5991 # Per bank write bursts +system.physmem.perBankWrBursts::11 6522 # Per bank write bursts +system.physmem.perBankWrBursts::12 6386 # Per bank write bursts +system.physmem.perBankWrBursts::13 6332 # Per bank write bursts +system.physmem.perBankWrBursts::14 6056 # Per bank write bursts +system.physmem.perBankWrBursts::15 6134 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 202723740000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 148203 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 97674 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,198 +127,177 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 56168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.051275 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.674597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 689.024149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 28075 49.98% 49.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 10399 18.51% 68.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4642 8.26% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2823 5.03% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1837 3.27% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1236 2.20% 87.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 832 1.48% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 663 1.18% 89.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 489 0.87% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 349 0.62% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 274 0.49% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 236 0.42% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 206 0.37% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 181 0.32% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 152 0.27% 93.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 162 0.29% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 167 0.30% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 157 0.28% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 185 0.33% 95.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 244 0.43% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 965 1.72% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 247 0.44% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 159 0.28% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 168 0.30% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 90 0.16% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 119 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 59 0.11% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 42 0.07% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 39 0.07% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 20 0.04% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 31 0.06% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.03% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 11 0.02% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 21 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 16 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 11 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 15 0.03% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 11 0.02% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 8 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 7 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 8 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 7 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 7 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 6 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 8 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 56168 # Bytes accessed per row activation -system.physmem.totQLat 1531991500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4652987750 # Sum of mem lat for all requests -system.physmem.totBusLat 740665000 # Total cycles spent in databus access -system.physmem.totBankLat 2380331250 # Total cycles spent in bank access -system.physmem.avgQLat 10342.00 # Average queueing delay per request -system.physmem.avgBankLat 16068.88 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31410.88 # Average memory access latency -system.physmem.avgRdBW 46.87 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 30.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.87 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 30.89 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation +system.physmem.totQLat 1733533250 # Total ticks spent queuing +system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks +system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.35 # Average write queue length over time -system.physmem.readRowHits 130665 # Number of row buffer hits during reads -system.physmem.writeRowHits 58958 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.37 # Row buffer hit rate for writes -system.physmem.avgGap 822984.74 # Average gap between requests -system.membus.throughput 77765395 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46900 # Transaction distribution -system.membus.trans_dist::ReadResp 46899 # Transaction distribution -system.membus.trans_dist::Writeback 97667 # Transaction distribution -system.membus.trans_dist::UpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 101306 # Transaction distribution -system.membus.trans_dist::ReadExResp 101306 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394092 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15735808 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15735808 # Total data (bytes) +system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing +system.physmem.readRowHits 118615 # Number of row buffer hits during reads +system.physmem.writeRowHits 57916 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes +system.physmem.avgGap 824492.49 # Average gap between requests +system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 77623185 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46911 # Transaction distribution +system.membus.trans_dist::ReadResp 46910 # Transaction distribution +system.membus.trans_dist::Writeback 97674 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11 # Transaction distribution +system.membus.trans_dist::ReadExReq 101292 # Transaction distribution +system.membus.trans_dist::ReadExResp 101292 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15736064 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1402154244 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182791904 # Number of BP lookups -system.cpu.branchPred.condPredicted 143107699 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265665 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 92799489 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87211157 # Number of BTB hits +system.cpu.branchPred.lookups 182800422 # Number of BP lookups +system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.978057 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12678036 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116300 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,99 +341,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404699496 # number of cpu cycles simulated +system.cpu.numCycles 405447521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119376230 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761574875 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182791904 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99889193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170142836 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35680693 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77102658 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 212 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114526886 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2438240 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394234025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987457 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224103808 56.85% 56.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14182639 3.60% 60.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22897810 5.81% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22745771 5.77% 72.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20892648 5.30% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11601037 2.94% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13057020 3.31% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11991400 3.04% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52761892 13.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394234025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451673 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.881828 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129061557 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72597650 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158807244 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6229539 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27538035 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26120872 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76664 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825542137 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 294964 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27538035 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135654542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10112461 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47476958 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158262389 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15189640 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800582614 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3045147 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8947899 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242011448 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292995 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41790364 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170263021 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73493180 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28522055 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15837658 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755040585 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665344412 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1377558 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187353857 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479696912 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394234025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.687689 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735339 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138748910 35.19% 35.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69932496 17.74% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71500115 18.14% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53381002 13.54% 84.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31138415 7.90% 92.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15994110 4.06% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8838982 2.24% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2889382 0.73% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1810613 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394234025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479873 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available @@ -481,15 +462,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6514297 68.24% 73.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2551723 26.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447783022 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383422 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -515,84 +496,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153378055 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63799818 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665344412 # Type of FU issued -system.cpu.iq.rate 1.644046 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9545893 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014347 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1735846081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946976022 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646072801 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued +system.cpu.iq.rate 1.641040 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674890194 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8556478 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44233466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41675 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810117 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16632703 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19496 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7207 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27538035 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5291148 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386655 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760374882 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1114721 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170263021 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73493180 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219754 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12032 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810117 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4339015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4002364 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655919187 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150094220 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9425225 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558904 # number of nop insts executed -system.cpu.iew.exec_refs 212597859 # number of memory reference insts executed -system.cpu.iew.exec_branches 138494490 # Number of branches executed -system.cpu.iew.exec_stores 62503639 # Number of stores executed -system.cpu.iew.exec_rate 1.620756 # Inst execution rate -system.cpu.iew.wb_sent 651040733 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646072817 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374723288 # num instructions producing a value -system.cpu.iew.wb_consumers 646307001 # num instructions consuming a value +system.cpu.iew.exec_nop 1559155 # number of nop insts executed +system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed +system.cpu.iew.exec_branches 138495848 # Number of branches executed +system.cpu.iew.exec_stores 62487508 # Number of stores executed +system.cpu.iew.exec_rate 1.617786 # Inst execution rate +system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374730881 # num instructions producing a value +system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.596426 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579791 # average fanout of values written-back +system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189435177 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7191667 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366695990 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557061 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.231965 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159030399 43.37% 43.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98569557 26.88% 70.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33781130 9.21% 79.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18728324 5.11% 84.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16185625 4.41% 88.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417790 2.02% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6942685 1.89% 92.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3160022 0.86% 93.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22880458 6.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366695990 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,221 +584,225 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22880458 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104211738 # The number of ROB reads -system.cpu.rob.rob_writes 1548465628 # The number of ROB writes -system.cpu.timesIdled 328564 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10465471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104768676 # The number of ROB reads +system.cpu.rob.rob_writes 1548495185 # The number of ROB writes +system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.801008 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.801008 # CPI: Total CPI of All Threads -system.cpu.ipc 1.248427 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.248427 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058780194 # number of integer regfile reads -system.cpu.int_regfile_writes 751998753 # number of integer regfile writes +system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads +system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads +system.cpu.int_regfile_writes 752016829 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210849013 # number of misc regfile reads +system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 735301298 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864913 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111058 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33804 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147703872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148783104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26125731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1828577727 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15008 # number of replacements -system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15073 # number of replacements +system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114505770 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114505770 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114505770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114505770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114505770 # number of overall hits -system.cpu.icache.overall_hits::total 114505770 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21115 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21115 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21115 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21115 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21115 # number of overall misses -system.cpu.icache.overall_misses::total 21115 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 590629979 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 590629979 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 590629979 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 590629979 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 590629979 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 590629979 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114526885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114526885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114526885 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114526885 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114526885 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114526885 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27972.056784 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27972.056784 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27972.056784 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27972.056784 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 633 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits +system.cpu.icache.overall_hits::total 114510320 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses +system.cpu.icache.overall_misses::total 21232 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27095.550678 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27095.550678 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27095.550678 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27095.550678 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.300000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4174 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4174 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4174 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4174 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4174 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4174 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16941 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16941 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16941 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16941 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16941 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16941 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 425273769 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 425273769 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 425273769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 425273769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 425273769 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 425273769 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25103.227023 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25103.227023 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25103.227023 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25103.227023 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4215 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4215 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4215 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4215 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4215 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4215 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17017 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17017 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17017 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17017 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17017 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17017 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 416333765 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 416333765 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 416333765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 416333765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 416333765 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 416333765 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24465.755715 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24465.755715 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115462 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27105.054655 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1782175 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146717 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.147025 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102215583000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23019.815136 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 365.213065 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.026454 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.702509 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011145 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113526 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.827181 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13469 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804438 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817907 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1111058 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1111058 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 63 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 63 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247536 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247536 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13469 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1051974 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065443 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13469 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1051974 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065443 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3395 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43534 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46929 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101307 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101307 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3395 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144841 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148236 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3395 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144841 # number of overall misses -system.cpu.l2cache.overall_misses::total 148236 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 273316250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3670387750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3943704000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7082585749 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7082585749 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 273316250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10752973499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11026289749 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 273316250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10752973499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11026289749 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16864 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 847972 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864836 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1111058 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1111058 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 69 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 69 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348843 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348843 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 16864 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1196815 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1213679 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16864 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1196815 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1213679 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.201316 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051339 # miss rate for ReadReq accesses +system.cpu.l2cache.tags.replacements 115458 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27089.677773 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1781255 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 146702 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.141995 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 102544951000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23009.492156 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 363.276336 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.909282 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.702194 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011086 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113431 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.826711 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13516 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 804499 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 818015 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1111085 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1111085 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247576 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247576 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13516 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1052075 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065591 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13516 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1052075 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065591 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3400 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 43535 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 46935 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3400 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144828 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3400 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 144828 # number of overall misses +system.cpu.l2cache.overall_misses::total 148228 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263796250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3483365500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3747161750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7556144249 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7556144249 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 263796250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11039509749 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11303305999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 263796250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11039509749 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11303305999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16916 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 848034 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 864950 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1111085 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1111085 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 348869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 348869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 16916 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1196903 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1213819 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16916 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1196903 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1213819 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200993 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051336 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.054263 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.086957 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.086957 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290409 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290409 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.201316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.121022 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122138 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.201316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.121022 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122138 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80505.522828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84310.831764 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84035.543054 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69912.106261 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69912.106261 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80505.522828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74239.845755 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74383.346481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80505.522828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74239.845755 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74383.346481 # average overall miss latency +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290347 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.290347 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200993 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.121002 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.122117 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200993 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.121002 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122117 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77587.132353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80012.989549 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79837.258975 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2299.900000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2299.900000 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74596.904515 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74596.904515 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76256.213394 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76256.213394 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,195 +811,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97667 # number of writebacks -system.cpu.l2cache.writebacks::total 97667 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97674 # number of writebacks +system.cpu.l2cache.writebacks::total 97674 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3390 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43510 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46900 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101307 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101307 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3390 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144817 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148207 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3390 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144817 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148207 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230113250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3119161250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3349274500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 63505 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 63505 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5794278751 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5794278751 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230113250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8913440001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9143553251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230113250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8913440001 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9143553251 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051311 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054230 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.086957 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.086957 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290409 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290409 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67880.014749 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71688.376235 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71413.102345 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10584.166667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10584.166667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57195.245649 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57195.245649 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3395 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43516 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46911 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3395 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144809 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3395 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144809 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148204 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220586000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2937177750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3157763750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6271255251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6271255251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220586000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9208433001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9429019001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220586000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9208433001 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9429019001 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051314 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290347 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290347 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122097 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122097 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64973.784978 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67496.501287 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67313.929569 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61912.029963 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61912.029963 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192719 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136217061 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136217061 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50989456 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488807 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488807 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1192807 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.511512 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190198729 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196903 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.909059 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.511512 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990603 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990603 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136233368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136233368 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50987745 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50987745 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187206517 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187206517 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187206517 # number of overall hits -system.cpu.dcache.overall_hits::total 187206517 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1700496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1700496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3249850 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3249850 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4950346 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4950346 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4950346 # number of overall misses -system.cpu.dcache.overall_misses::total 4950346 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29799414454 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29799414454 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 69603685702 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 69603685702 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 646250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 646250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99403100156 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99403100156 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99403100156 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99403100156 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137917557 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137917557 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187221113 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187221113 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187221113 # number of overall hits +system.cpu.dcache.overall_hits::total 187221113 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1703411 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1703411 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251561 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251561 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses +system.cpu.dcache.overall_misses::total 4954972 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488848 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488848 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192156863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192156863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192156863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192156863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012330 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059917 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025762 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025762 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025762 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025762 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17523.954454 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17523.954454 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21417.507178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21417.507178 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15762.195122 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15762.195122 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20080.030801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20080.030801 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21739 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 43165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1718 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 667 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.653667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 64.715142 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111058 # number of writebacks -system.cpu.dcache.writebacks::total 1111058 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851983 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 851983 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2901479 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2901479 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3753462 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3753462 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3753462 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3753462 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848513 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348371 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348371 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196884 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196884 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196884 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196884 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12602071778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12602071778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9955936491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9955936491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22558008269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22558008269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22558008269 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks +system.cpu.dcache.writebacks::total 1111085 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14851.948972 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14851.948972 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28578.545548 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28578.545548 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c15724aa4..09ddfe08f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,103 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458276 # Number of seconds simulated -sim_ticks 458276279000 # Number of ticks simulated -final_tick 458276279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.459344 # Number of seconds simulated +sim_ticks 459344378000 # Number of ticks simulated +final_tick 459344378000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81967 # Simulator instruction rate (inst/s) -host_op_rate 151565 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45427941 # Simulator tick rate (ticks/s) -host_mem_usage 343960 # Number of bytes of host memory used -host_seconds 10087.98 # Real time elapsed on the host +host_inst_rate 78845 # Simulator instruction rate (inst/s) +host_op_rate 145792 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43799497 # Simulator tick rate (ticks/s) +host_mem_usage 371908 # Number of bytes of host memory used +host_seconds 10487.44 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24475520 # Number of bytes read from this memory -system.physmem.bytes_read::total 24678208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18791744 # Number of bytes written to this memory -system.physmem.bytes_written::total 18791744 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382430 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385597 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293621 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293621 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53407783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53850066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41005273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41005273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41005273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53407783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94855339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385597 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 293621 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 385597 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 293621 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 24678208 # Total number of bytes read from memory -system.physmem.bytesWritten 18791744 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24678208 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18791744 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 129454 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 26368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23840 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 23982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 23151 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 22850 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 23658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23921 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18532 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19819 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18953 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18410 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18941 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18561 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18114 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17718 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 17344 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 16935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 17686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 17818 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry -system.physmem.totGap 458276251500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385597 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293621 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 201792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24475712 # Number of bytes read from this memory +system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 201792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 201792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18789056 # Number of bytes written to this memory +system.physmem.bytes_written::total 18789056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382433 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293579 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293579 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 439304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53284013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53723318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 439304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40904073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40904073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40904073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 439304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53284013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94627391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385586 # Number of read requests accepted +system.physmem.writeReqs 293579 # Number of write requests accepted +system.physmem.readBursts 385586 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293579 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24668096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue +system.physmem.bytesWritten 18787968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24677504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18789056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 137816 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24063 # Per bank write bursts +system.physmem.perBankRdBursts::1 26414 # Per bank write bursts +system.physmem.perBankRdBursts::2 24662 # Per bank write bursts +system.physmem.perBankRdBursts::3 24515 # Per bank write bursts +system.physmem.perBankRdBursts::4 23241 # Per bank write bursts +system.physmem.perBankRdBursts::5 23653 # Per bank write bursts +system.physmem.perBankRdBursts::6 24406 # Per bank write bursts +system.physmem.perBankRdBursts::7 24209 # Per bank write bursts +system.physmem.perBankRdBursts::8 23620 # Per bank write bursts +system.physmem.perBankRdBursts::9 23822 # Per bank write bursts +system.physmem.perBankRdBursts::10 24803 # Per bank write bursts +system.physmem.perBankRdBursts::11 24074 # Per bank write bursts +system.physmem.perBankRdBursts::12 23251 # Per bank write bursts +system.physmem.perBankRdBursts::13 22944 # Per bank write bursts +system.physmem.perBankRdBursts::14 23767 # Per bank write bursts +system.physmem.perBankRdBursts::15 23995 # Per bank write bursts +system.physmem.perBankWrBursts::0 18528 # Per bank write bursts +system.physmem.perBankWrBursts::1 19811 # Per bank write bursts +system.physmem.perBankWrBursts::2 18936 # Per bank write bursts +system.physmem.perBankWrBursts::3 18914 # Per bank write bursts +system.physmem.perBankWrBursts::4 18031 # Per bank write bursts +system.physmem.perBankWrBursts::5 18401 # Per bank write bursts +system.physmem.perBankWrBursts::6 18972 # Per bank write bursts +system.physmem.perBankWrBursts::7 18946 # Per bank write bursts +system.physmem.perBankWrBursts::8 18539 # Per bank write bursts +system.physmem.perBankWrBursts::9 18111 # Per bank write bursts +system.physmem.perBankWrBursts::10 18827 # Per bank write bursts +system.physmem.perBankWrBursts::11 17725 # Per bank write bursts +system.physmem.perBankWrBursts::12 17351 # Per bank write bursts +system.physmem.perBankWrBursts::13 16948 # Per bank write bursts +system.physmem.perBankWrBursts::14 17708 # Per bank write bursts +system.physmem.perBankWrBursts::15 17814 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 459344352000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 385586 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 293579 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,346 +127,324 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 125846 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.334329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.235120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 666.634247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 53836 42.78% 42.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 23576 18.73% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 10431 8.29% 69.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 6405 5.09% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 4091 3.25% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2950 2.34% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2205 1.75% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1721 1.37% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1423 1.13% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1129 0.90% 85.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 1178 0.94% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1088 0.86% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 719 0.57% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 691 0.55% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 593 0.47% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 590 0.47% 89.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 543 0.43% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 555 0.44% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 625 0.50% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 694 0.55% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 625 0.50% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 735 0.58% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6224 4.95% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 501 0.40% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 329 0.26% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 262 0.21% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 235 0.19% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 154 0.12% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 168 0.13% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 127 0.10% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 91 0.07% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 78 0.06% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 63 0.05% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 57 0.05% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 48 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.04% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 32 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 34 0.03% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 24 0.02% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 22 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 28 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 15 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 11 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 26 0.02% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 10 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 12 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 9 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 11 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 10 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 11 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 9 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 9 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 4 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 11 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 3 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 5 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 10 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 12 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 10 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 9 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 5 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 4 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 376 0.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 125846 # Bytes accessed per row activation -system.physmem.totQLat 3013395500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11189631750 # Sum of mem lat for all requests -system.physmem.totBusLat 1927150000 # Total cycles spent in databus access -system.physmem.totBankLat 6249086250 # Total cycles spent in bank access -system.physmem.avgQLat 7818.27 # Average queueing delay per request -system.physmem.avgBankLat 16213.28 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29031.55 # Average memory access latency -system.physmem.avgRdBW 53.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.85 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 13203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 13287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 13327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 13328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 13383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 13355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 13385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 13360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 13377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 13325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 13360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 13383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 13353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 13304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 13344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 13297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 13513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 147608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.394450 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.776614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 442.926634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 63757 43.19% 43.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 27975 18.95% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 12431 8.42% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7117 4.82% 75.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4833 3.27% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3554 2.41% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2743 1.86% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2234 1.51% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1986 1.35% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1585 1.07% 86.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1916 1.30% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1217 0.82% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1133 0.77% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1065 0.72% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 945 0.64% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 876 0.59% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1005 0.68% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1152 0.78% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1143 0.77% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 849 0.58% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 811 0.55% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 5222 3.54% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 320 0.22% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 205 0.14% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 175 0.12% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 129 0.09% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 96 0.07% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 103 0.07% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 90 0.06% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 59 0.04% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 49 0.03% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 46 0.03% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 39 0.03% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 37 0.03% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 41 0.03% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 25 0.02% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 33 0.02% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 21 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 11 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 24 0.02% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 23 0.02% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 26 0.02% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 13 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 15 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 22 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 19 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 16 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 15 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 11 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 21 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 9 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 16 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 10 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 11 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 14 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 17 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 17 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 11 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 7 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 10 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 9 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 7 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 6 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 12 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 24 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 37 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 1 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 9 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 3 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 5 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 3 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 6 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 5 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 4 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 8 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 4 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 3 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 3 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 8 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 10 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 18 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147608 # Bytes accessed per row activation +system.physmem.totQLat 3829490000 # Total ticks spent queuing +system.physmem.totMemAccLat 12088876250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1927195000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6332191250 # Total ticks spent accessing banks +system.physmem.avgQLat 9935.40 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16428.52 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31363.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 53.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 40.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 40.90 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.13 # Average write queue length over time -system.physmem.readRowHits 346215 # Number of row buffer hits during reads -system.physmem.writeRowHits 206987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.49 # Row buffer hit rate for writes -system.physmem.avgGap 674711.58 # Average gap between requests -system.membus.throughput 94855339 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178753 # Transaction distribution -system.membus.trans_dist::ReadResp 178753 # Transaction distribution -system.membus.trans_dist::Writeback 293621 # Transaction distribution -system.membus.trans_dist::UpgradeReq 129454 # Transaction distribution -system.membus.trans_dist::UpgradeResp 129454 # Transaction distribution -system.membus.trans_dist::ReadExReq 206844 # Transaction distribution -system.membus.trans_dist::ReadExResp 206844 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1323723 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1323723 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1323723 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469952 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469952 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43469952 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43469952 # Total data (bytes) +system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing +system.physmem.readRowHits 326974 # Number of row buffer hits during reads +system.physmem.writeRowHits 204419 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.63 # Row buffer hit rate for writes +system.physmem.avgGap 676336.90 # Average gap between requests +system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.85 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 94627391 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178768 # Transaction distribution +system.membus.trans_dist::ReadResp 178768 # Transaction distribution +system.membus.trans_dist::Writeback 293579 # Transaction distribution +system.membus.trans_dist::UpgradeReq 137816 # Transaction distribution +system.membus.trans_dist::UpgradeResp 137816 # Transaction distribution +system.membus.trans_dist::ReadExReq 206818 # Transaction distribution +system.membus.trans_dist::ReadExResp 206818 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1340383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1340383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1340383 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43466560 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43466560 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3387419250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3394511250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3898953053 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3904983950 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.branchPred.lookups 205598458 # Number of BP lookups -system.cpu.branchPred.condPredicted 205598458 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9896380 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117174051 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114692881 # Number of BTB hits +system.cpu.branchPred.lookups 205617659 # Number of BP lookups +system.cpu.branchPred.condPredicted 205617659 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9903777 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117094014 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114674529 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.882492 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25059076 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1793638 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.933724 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25071350 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1805580 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 916711426 # number of cpu cycles simulated +system.cpu.numCycles 918847215 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167358741 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131763090 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205598458 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139751957 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352259726 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71078928 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 303625713 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47908 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254198 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162013852 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2539166 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 884476430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167424119 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131762166 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205617659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139745879 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352279607 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71096448 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 305445808 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47309 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 248301 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162018331 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2527029 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 886385524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.375664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.323603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536284008 60.63% 60.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23384253 2.64% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25253496 2.86% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27902300 3.15% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17749201 2.01% 71.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22913352 2.59% 73.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29416028 3.33% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26647385 3.01% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174926407 19.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 538173800 60.72% 60.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23402088 2.64% 63.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25255439 2.85% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27875375 3.14% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17753006 2.00% 71.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22920695 2.59% 73.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29402684 3.32% 77.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26636320 3.01% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174966117 19.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 884476430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224278 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.234590 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222500802 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258763432 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295392395 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46889742 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60930059 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071354254 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60930059 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 255984410 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 114277740 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18348 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306680368 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146585505 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035184371 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 17660 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24877077 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106438010 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2138008878 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150477195 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273486109 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 27867 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 886385524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.223778 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.231720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222535838 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 260614631 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295382827 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46911879 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60940349 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071401768 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60940349 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256088737 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 115827091 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17786 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306634612 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146876949 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035245404 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18048 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25034239 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106622478 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138089384 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150744592 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273505517 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 42043 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523968024 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1260 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1188 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 346256555 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495848123 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194451746 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195373810 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54752041 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975440933 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 14060 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772196947 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 491373 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441593338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734714175 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13508 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 884476430 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883218 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524048530 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1277 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346982000 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495887036 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194435860 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195573190 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54925274 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975493038 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13839 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772240867 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441634059 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734815554 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13287 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 886385524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.999402 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.882776 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 267871954 30.29% 30.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151795933 17.16% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137193879 15.51% 62.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131984117 14.92% 77.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91584837 10.35% 88.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55972472 6.33% 94.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34407043 3.89% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11912621 1.35% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1753574 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269512858 30.41% 30.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151842775 17.13% 47.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137668751 15.53% 63.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131788792 14.87% 77.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91572274 10.33% 88.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55974345 6.31% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34415050 3.88% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11842339 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1768340 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 884476430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 886385524 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4900873 32.33% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7664927 50.56% 82.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2594883 17.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4916629 32.41% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7656958 50.48% 82.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2596197 17.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2622931 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165806661 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353241 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880883 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2627446 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165802431 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352933 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880848 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -491,84 +471,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429278261 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170254965 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429321200 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170256004 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772196947 # Type of FU issued -system.cpu.iq.rate 1.933211 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15160683 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008555 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4444507102 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417272272 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744936391 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15278 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 33048 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3640 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784727445 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7254 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172555642 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772240867 # Type of FU issued +system.cpu.iq.rate 1.928766 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15169784 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008560 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4446506063 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417344315 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744979494 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15843 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 54000 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3681 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784775700 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7505 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172548732 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111746790 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 385650 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 328822 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45291560 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111785908 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 387968 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 329381 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45275674 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15317 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14622 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 560 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60930059 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 66792766 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7181188 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975454993 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 789344 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495848947 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194451746 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4469390 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83563 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 328822 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5897715 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4420728 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10318443 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1753033326 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424140898 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19163621 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60940349 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 68092505 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7152437 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975506877 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 797637 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495888065 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194435860 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3411 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4450354 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83339 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 329381 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5904947 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4426658 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10331605 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753082670 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424162697 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19158197 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590949993 # number of memory reference insts executed -system.cpu.iew.exec_branches 167484534 # Number of branches executed -system.cpu.iew.exec_stores 166809095 # Number of stores executed -system.cpu.iew.exec_rate 1.912307 # Inst execution rate -system.cpu.iew.wb_sent 1749784390 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744940031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325078811 # num instructions producing a value -system.cpu.iew.wb_consumers 1946006295 # num instructions consuming a value +system.cpu.iew.exec_refs 590975772 # number of memory reference insts executed +system.cpu.iew.exec_branches 167493044 # Number of branches executed +system.cpu.iew.exec_stores 166813075 # Number of stores executed +system.cpu.iew.exec_rate 1.907915 # Inst execution rate +system.cpu.iew.wb_sent 1749835931 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744983175 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325071563 # num instructions producing a value +system.cpu.iew.wb_consumers 1945952606 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.903478 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680922 # average fanout of values written-back +system.cpu.iew.wb_rate 1.899100 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680937 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446495753 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446546244 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9924967 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823546371 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856591 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.436968 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9931583 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 825445175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.852320 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.435275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331540397 40.26% 40.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193316161 23.47% 63.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63109500 7.66% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92579702 11.24% 82.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24975285 3.03% 85.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27432624 3.33% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9320772 1.13% 90.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11449898 1.39% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69822032 8.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 333247555 40.37% 40.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193457802 23.44% 63.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63161135 7.65% 71.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92621225 11.22% 82.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24986952 3.03% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27475927 3.33% 89.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9292263 1.13% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11354595 1.38% 91.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69847721 8.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823546371 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825445175 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,228 +559,228 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69822032 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69847721 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729208793 # The number of ROB reads -system.cpu.rob.rob_writes 4012058416 # The number of ROB writes -system.cpu.timesIdled 3349890 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32234996 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2731132399 # The number of ROB reads +system.cpu.rob.rob_writes 4012169962 # The number of ROB writes +system.cpu.timesIdled 3361848 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32461691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.108643 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108643 # CPI: Total CPI of All Threads -system.cpu.ipc 0.902004 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.902004 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716444328 # number of integer regfile reads -system.cpu.int_regfile_writes 1420478428 # number of integer regfile writes -system.cpu.fp_regfile_reads 3628 # number of floating regfile reads -system.cpu.fp_regfile_writes 22 # number of floating regfile writes -system.cpu.cc_regfile_reads 597234249 # number of cc regfile reads -system.cpu.cc_regfile_writes 405441134 # number of cc regfile writes -system.cpu.misc_regfile_reads 964696527 # number of misc regfile reads +system.cpu.cpi 1.111226 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111226 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899907 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899907 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716502748 # number of integer regfile reads +system.cpu.int_regfile_writes 1420506154 # number of integer regfile writes +system.cpu.fp_regfile_reads 3672 # number of floating regfile reads +system.cpu.fp_regfile_writes 20 # number of floating regfile writes +system.cpu.cc_regfile_reads 597266892 # number of cc regfile reads +system.cpu.cc_regfile_writes 405440972 # number of cc regfile writes +system.cpu.misc_regfile_reads 964759802 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698612009 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1899997 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1899996 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 130874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 130874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771776 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 144643 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7660372 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7805015 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311337920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311775616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311775616 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8381696 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4900939314 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 698195949 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1908531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1908530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 139237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 139237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771745 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7677656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7830553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 434176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311361216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311795392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311795392 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8916992 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4909747073 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 207374491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 219630492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3958743651 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3954804981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5318 # number of replacements -system.cpu.icache.tags.tagsinuse 1036.794557 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161872030 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6894 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23480.131999 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5269 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.495304 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161868325 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6841 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23661.500512 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1036.794557 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506247 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506247 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161874097 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161874097 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161874097 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161874097 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161874097 # number of overall hits -system.cpu.icache.overall_hits::total 161874097 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 139755 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 139755 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 139755 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 139755 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 139755 # number of overall misses -system.cpu.icache.overall_misses::total 139755 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 916174482 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 916174482 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 916174482 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 916174482 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 916174482 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 916174482 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162013852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162013852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162013852 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162013852 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162013852 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162013852 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000863 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000863 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000863 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000863 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000863 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000863 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6555.575700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6555.575700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6555.575700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6555.575700 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1833 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.495304 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506101 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506101 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161870260 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161870260 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161870260 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161870260 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161870260 # number of overall hits +system.cpu.icache.overall_hits::total 161870260 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 148071 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 148071 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 148071 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 148071 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 148071 # number of overall misses +system.cpu.icache.overall_misses::total 148071 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 946797737 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 946797737 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 946797737 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 946797737 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 946797737 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 946797737 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162018331 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162018331 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162018331 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162018331 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162018331 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162018331 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6394.214512 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6394.214512 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6394.214512 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6394.214512 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 466 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 166.636364 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 77.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1951 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1951 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1951 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1951 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1951 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1951 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 137804 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 137804 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 137804 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 137804 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 137804 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 137804 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 553553258 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 553553258 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 553553258 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 553553258 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 553553258 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 553553258 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000851 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000851 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000851 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4016.960741 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4016.960741 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1958 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1958 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1958 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1958 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1958 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1958 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 146113 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 146113 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 146113 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 146113 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 146113 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 146113 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 564906008 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 564906008 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 564906008 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 564906008 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 564906008 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 564906008 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000902 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000902 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000902 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3866.226879 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3866.226879 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3866.226879 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3866.226879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3866.226879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3866.226879 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352916 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29674.078168 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3696976 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385280 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.595556 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 199035325000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21118.733135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.036414 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8331.308620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644493 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006837 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.254251 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905581 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3672 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586607 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590279 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2330686 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330686 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1446 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1446 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564906 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564906 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3672 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151513 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2155185 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3672 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151513 # number of overall hits -system.cpu.l2cache.overall_hits::total 2155185 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3168 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175586 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178754 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 129428 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 129428 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206870 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206870 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3168 # number of demand (read+write) misses +system.cpu.l2cache.tags.replacements 352904 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29669.825336 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3696987 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385265 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.595959 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 199212130000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21123.439325 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.720045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8322.665965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644636 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006827 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.253988 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.905451 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586803 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590434 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2330856 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2330856 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1444 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1444 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564904 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564904 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3631 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151707 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2155338 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3631 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151707 # number of overall hits +system.cpu.l2cache.overall_hits::total 2155338 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3154 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175615 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178769 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 137793 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 137793 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206841 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206841 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3154 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 382456 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385624 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses +system.cpu.l2cache.demand_misses::total 385610 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3154 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 382456 # number of overall misses -system.cpu.l2cache.overall_misses::total 385624 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245961000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13200679958 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13446640958 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6462222 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 6462222 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14256875974 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14256875974 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 245961000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27457555932 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27703516932 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 245961000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27457555932 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27703516932 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6840 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762193 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769033 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2330686 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2330686 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130874 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 130874 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771776 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771776 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6840 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533969 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540809 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6840 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533969 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540809 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099641 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101046 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988951 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988951 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268044 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268044 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463158 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150932 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151772 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463158 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150932 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151772 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77639.204545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75180.708929 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75224.280061 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.929088 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.929088 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68917.078233 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68917.078233 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71840.748843 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71840.748843 # average overall miss latency +system.cpu.l2cache.overall_misses::total 385610 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239723500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13195248212 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13434971712 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6538219 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 6538219 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15149801477 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15149801477 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 239723500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28345049689 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28584773189 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 239723500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28345049689 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28584773189 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6785 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769203 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2330856 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2330856 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 139237 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 139237 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6785 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2534163 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540948 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6785 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2534163 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540948 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.464849 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099644 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101045 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989629 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989629 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268017 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268017 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.464849 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150920 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151758 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.464849 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150920 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151758 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76006.182625 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75137.364189 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75152.692648 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.449573 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.449573 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73243.706407 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73243.706407 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76006.182625 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74113.230513 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74128.713438 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76006.182625 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74113.230513 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74128.713438 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,168 +789,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293621 # number of writebacks -system.cpu.l2cache.writebacks::total 293621 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3168 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175586 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178754 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 129428 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 129428 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206870 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206870 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 293579 # number of writebacks +system.cpu.l2cache.writebacks::total 293579 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3154 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175615 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178769 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 137793 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 137793 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206841 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206841 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3154 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 382456 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385624 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385610 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3154 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 382456 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385624 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205953000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10947318958 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11153271958 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1297954472 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1297954472 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11628367526 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11628367526 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205953000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22575686484 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22781639484 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205953000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22575686484 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22781639484 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099641 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101046 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988951 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988951 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268044 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268044 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151772 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151772 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65010.416667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62347.333831 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62394.530797 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10028.390086 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10028.390086 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56210.990119 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56210.990119 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 385610 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200295500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10955219212 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11155514712 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1381780092 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1381780092 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12524720523 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12524720523 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200295500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23479939735 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23680235235 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200295500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23479939735 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23680235235 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099644 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101045 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989629 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989629 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268017 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268017 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151758 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151758 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63505.231452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62382.024383 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62401.840990 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.941129 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.941129 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60552.407516 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60552.407516 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63505.231452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61392.525506 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61409.805853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63505.231452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61392.525506 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61409.805853 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529873 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.353795 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396071280 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2533969 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.304706 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353795 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247337709 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247337709 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148240799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148240799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395578508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395578508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395578508 # number of overall hits -system.cpu.dcache.overall_hits::total 395578508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2867309 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2867309 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 919403 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 919403 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3786712 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3786712 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3786712 # number of overall misses -system.cpu.dcache.overall_misses::total 3786712 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57500595434 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57500595434 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25821603651 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25821603651 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83322199085 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83322199085 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83322199085 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83322199085 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250205018 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250205018 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 2530067 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.247344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 396095422 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534163 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.302267 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 247349433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247349433 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148232494 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148232494 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395581927 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395581927 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395581927 # number of overall hits +system.cpu.dcache.overall_hits::total 395581927 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2875523 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2875523 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 927708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 927708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3803231 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3803231 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3803231 # number of overall misses +system.cpu.dcache.overall_misses::total 3803231 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57896671055 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57896671055 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26926543731 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26926543731 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84823214786 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84823214786 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84823214786 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84823214786 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250224956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250224956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399365220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399365220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399365220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399365220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011460 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009482 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009482 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009482 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009482 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.853782 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.853782 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28085.185333 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28085.185333 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22003.838445 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22003.838445 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7384 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399385158 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399385158 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399385158 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399385158 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011492 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011492 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006220 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006220 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009523 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009523 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009523 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009523 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.309847 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.309847 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.804929 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.804929 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22302.935264 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22302.935264 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6209 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 704 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 638 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.488636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.731975 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330686 # number of writebacks -system.cpu.dcache.writebacks::total 2330686 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1104851 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1104851 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1121870 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1121870 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1121870 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1121870 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762458 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 902384 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 902384 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2664842 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2664842 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2664842 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2664842 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30865724250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30865724250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23705880099 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23705880099 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54571604349 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54571604349 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54571604349 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54571604349 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2330856 # number of writebacks +system.cpu.dcache.writebacks::total 2330856 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1112832 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1112832 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17000 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17000 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1129832 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1129832 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1129832 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1129832 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762691 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762691 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910708 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 910708 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2673399 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2673399 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2673399 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2673399 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862506500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862506500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24793543019 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24793543019 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55656049519 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55656049519 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55656049519 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55656049519 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006050 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006050 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006673 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006673 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17512.884988 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17512.884988 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26270.279725 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26270.279725 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006106 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006106 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006694 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.744584 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.744584 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27224.470433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27224.470433 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index e5b6926d1..0feb1e331 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139916 # Number of seconds simulated -sim_ticks 139916242500 # Number of ticks simulated -final_tick 139916242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139926 # Number of seconds simulated +sim_ticks 139926186500 # Number of ticks simulated +final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80792 # Simulator instruction rate (inst/s) -host_op_rate 80792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28354866 # Simulator tick rate (ticks/s) -host_mem_usage 231004 # Number of bytes of host memory used -host_seconds 4934.47 # Real time elapsed on the host +host_inst_rate 122800 # Simulator instruction rate (inst/s) +host_op_rate 122800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43101138 # Simulator tick rate (ticks/s) +host_mem_usage 261428 # Number of bytes of host memory used +host_seconds 3246.46 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1536462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1815486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3351948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1536462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1536462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1536462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1815486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3351948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7328 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7328 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 468992 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 597 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 451 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 513 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 371 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139916169000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7328 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 1536353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1815357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3351710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1536353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1536353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1536353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1815357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3351710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7328 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7328 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 468992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 468992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 507 # Per bank write bursts +system.physmem.perBankRdBursts::1 643 # Per bank write bursts +system.physmem.perBankRdBursts::2 444 # Per bank write bursts +system.physmem.perBankRdBursts::3 597 # Per bank write bursts +system.physmem.perBankRdBursts::4 448 # Per bank write bursts +system.physmem.perBankRdBursts::5 451 # Per bank write bursts +system.physmem.perBankRdBursts::6 505 # Per bank write bursts +system.physmem.perBankRdBursts::7 513 # Per bank write bursts +system.physmem.perBankRdBursts::8 423 # Per bank write bursts +system.physmem.perBankRdBursts::9 395 # Per bank write bursts +system.physmem.perBankRdBursts::10 336 # Per bank write bursts +system.physmem.perBankRdBursts::11 304 # Per bank write bursts +system.physmem.perBankRdBursts::12 416 # Per bank write bursts +system.physmem.perBankRdBursts::13 534 # Per bank write bursts +system.physmem.perBankRdBursts::14 441 # Per bank write bursts +system.physmem.perBankRdBursts::15 371 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 139926113000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7328 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,98 +152,97 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 702 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 659.145299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 261.737271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1246.496021 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 193 27.49% 27.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 99 14.10% 41.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 67 9.54% 51.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.98% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 35 4.99% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 20 2.85% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 23 3.28% 70.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 21 2.99% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 2.14% 75.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 12 1.71% 77.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 1.28% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.57% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 12 1.71% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.14% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.57% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.71% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 15 2.14% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.71% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 6 0.85% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.14% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.57% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.57% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.57% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.43% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.85% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.85% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.43% 91.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.14% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.43% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.57% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.28% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.28% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.14% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.43% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 3 0.43% 95.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.14% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.14% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.14% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.28% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.28% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.14% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.14% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.14% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.14% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.14% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.14% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.14% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.14% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.14% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.14% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.14% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.14% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation -system.physmem.totQLat 39772250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175041000 # Sum of mem lat for all requests -system.physmem.totBusLat 36640000 # Total cycles spent in databus access -system.physmem.totBankLat 98628750 # Total cycles spent in bank access -system.physmem.avgQLat 5427.44 # Average queueing delay per request -system.physmem.avgBankLat 13459.16 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23886.60 # Average memory access latency -system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation +system.physmem.totQLat 59880500 # Total ticks spent queuing +system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers +system.physmem.totBankLat 101103750 # Total ticks spent accessing banks +system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6626 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6130 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19093363.67 # Average gap between requests -system.membus.throughput 3351948 # Throughput (bytes/s) +system.physmem.avgGap 19094720.66 # Average gap between requests +system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3351710 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution @@ -252,39 +253,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 468992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8796500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68414000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 53489675 # Number of BP lookups +system.cpu.branchPred.lookups 53489673 # Number of BP lookups system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212540 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882350 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263540 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754653 # DTB read hits +system.cpu.dtb.read_hits 94754637 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754674 # DTB read accesses -system.cpu.dtb.write_hits 73521120 # DTB write hits +system.cpu.dtb.read_accesses 94754658 # DTB read accesses +system.cpu.dtb.write_hits 73521124 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521155 # DTB write accesses -system.cpu.dtb.data_hits 168275773 # DTB hits +system.cpu.dtb.write_accesses 73521159 # DTB write accesses +system.cpu.dtb.data_hits 168275761 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275829 # DTB accesses -system.cpu.itb.fetch_hits 48611327 # ITB hits +system.cpu.dtb.data_accesses 168275817 # DTB accesses +system.cpu.itb.fetch_hits 48611324 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655847 # ITB accesses +system.cpu.itb.fetch_accesses 48655844 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -298,18 +299,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279832486 # number of cpu cycles simulated +system.cpu.numCycles 279852374 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230507 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484570 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -320,12 +321,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400467 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7142 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13525828 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306658 # Number of cycles cpu stages are processed. -system.cpu.activity 95.166455 # Percentage of cycles cpu is active +system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed. +system.cpu.activity 95.159695 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -337,72 +338,72 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701925 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701974 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.424654 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701974 # CPI: Total CPI of All Threads +system.cpu.ipc 1.424553 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.424654 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78084810 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747676 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.095874 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107180757 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.698244 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102617259 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215227 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.329040 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181087860 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744626 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.287049 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90364523 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467963 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.707637 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.424553 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.971183 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606795 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.700999 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.971183 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894029 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894029 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606795 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606795 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606795 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606795 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606795 # number of overall hits -system.cpu.icache.overall_hits::total 48606795 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4532 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4532 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4532 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4532 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4532 # number of overall misses -system.cpu.icache.overall_misses::total 4532 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 272220250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 272220250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 272220250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 272220250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 272220250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 272220250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611327 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611327 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611327 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611327 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611327 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611327 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits +system.cpu.icache.overall_hits::total 48606790 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses +system.cpu.icache.overall_misses::total 4534 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60066.251103 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60066.251103 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60066.251103 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60066.251103 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60066.251103 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -411,38 +412,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 629 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 629 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 629 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 629 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 236384250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 236384250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 236384250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 236384250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 236384250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 236384250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60564.757879 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60564.757879 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60564.757879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60564.757879 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3981353 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -458,23 +459,23 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6540750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6779999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.944649 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.550028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.807922 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.586699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.119230 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -499,17 +500,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 226995250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59463500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 286458750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214640250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214640250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 226995250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 274103750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 501099000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 226995250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 274103750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 501099000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -534,17 +535,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67578.222685 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72164.441748 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68481.651924 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68248.092210 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68248.092210 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68381.413755 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67578.222685 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69061.161502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68381.413755 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,17 +565,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 184726250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49135000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 233861250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175601750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175601750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184726250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 224736750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 409463000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184726250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 224736750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 409463000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -586,51 +587,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54994.417982 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59629.854369 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55907.542434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55835.214626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55835.214626 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54994.417982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56623.015873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55876.501092 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.967259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168254256 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40523.664740 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.967259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501075 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501075 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254256 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254256 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254256 # number of overall hits -system.cpu.dcache.overall_hits::total 168254256 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits +system.cpu.dcache.overall_hits::total 168254255 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19654 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20962 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20962 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20962 # number of overall misses -system.cpu.dcache.overall_misses::total 20962 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 85220999 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 85220999 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1076127000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1076127000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1161347999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1161347999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1161347999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1161347999 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses +system.cpu.dcache.overall_misses::total 20963 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -647,19 +648,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65153.668960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65153.668960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54753.587056 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54753.587056 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55402.537878 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55402.537878 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55402.537878 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 596 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.743289 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -667,12 +668,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16810 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16810 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16810 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16810 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -681,14 +682,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61946751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61946751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218347750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218347750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 280294501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 280294501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 280294501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 280294501 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -697,14 +698,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65207.106316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65207.106316 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68191.052467 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68191.052467 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67508.309489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67508.309489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index e492ac5d0..c079ee28b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077522 # Number of seconds simulated -sim_ticks 77521581000 # Number of ticks simulated -final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077516 # Number of seconds simulated +sim_ticks 77516381000 # Number of ticks simulated +final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201802 # Simulator instruction rate (inst/s) -host_op_rate 201802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41653613 # Simulator tick rate (ticks/s) -host_mem_usage 236024 # Number of bytes of host memory used -host_seconds 1861.10 # Real time elapsed on the host +host_inst_rate 185827 # Simulator instruction rate (inst/s) +host_op_rate 185827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38353496 # Simulator tick rate (ticks/s) +host_mem_usage 262456 # Number of bytes of host memory used +host_seconds 2021.10 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 476288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2850716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3293225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6143941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2850716 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2850716 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2850716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3293225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6143941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7442 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 476288 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 527 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 436 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 542 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 379 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77521491500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7442 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory +system.physmem.bytes_read::total 476608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7447 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2853384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3295097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6148481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2853384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2853384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2853384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3295097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6148481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7447 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7447 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 476608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 476608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 524 # Per bank write bursts +system.physmem.perBankRdBursts::1 653 # Per bank write bursts +system.physmem.perBankRdBursts::2 449 # Per bank write bursts +system.physmem.perBankRdBursts::3 600 # Per bank write bursts +system.physmem.perBankRdBursts::4 447 # Per bank write bursts +system.physmem.perBankRdBursts::5 455 # Per bank write bursts +system.physmem.perBankRdBursts::6 515 # Per bank write bursts +system.physmem.perBankRdBursts::7 524 # Per bank write bursts +system.physmem.perBankRdBursts::8 439 # Per bank write bursts +system.physmem.perBankRdBursts::9 407 # Per bank write bursts +system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::11 306 # Per bank write bursts +system.physmem.perBankRdBursts::12 414 # Per bank write bursts +system.physmem.perBankRdBursts::13 542 # Per bank write bursts +system.physmem.perBankRdBursts::14 453 # Per bank write bursts +system.physmem.perBankRdBursts::15 379 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 77516291500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7447 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,138 +152,133 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 756 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 621.460317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 241.668493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1200.727367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 238 31.48% 31.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 108 14.29% 45.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 62 8.20% 53.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 57 7.54% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 33 4.37% 65.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 22 2.91% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 21 2.78% 71.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 18 2.38% 73.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 1.72% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 16 2.12% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 0.79% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.59% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 9 1.19% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.19% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.66% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.79% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 17 2.25% 86.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.40% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 7 0.93% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 4 0.53% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.40% 90.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.79% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 7 0.93% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.40% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.40% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.26% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.13% 94.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.13% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 3 0.40% 95.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.26% 96.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.13% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.26% 97.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.13% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 7 0.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 756 # Bytes accessed per row activation -system.physmem.totQLat 42048500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 179991000 # Sum of mem lat for all requests -system.physmem.totBusLat 37210000 # Total cycles spent in databus access -system.physmem.totBankLat 100732500 # Total cycles spent in bank access -system.physmem.avgQLat 5650.16 # Average queueing delay per request -system.physmem.avgBankLat 13535.68 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24185.84 # Average memory access latency -system.physmem.avgRdBW 6.14 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.14 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.618557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.969320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 801.678722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 417 35.82% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 184 15.81% 51.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 111 9.54% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 97 8.33% 69.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 49 4.21% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 38 3.26% 76.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 28 2.41% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 28 2.41% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 22 1.89% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 22 1.89% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 9 0.77% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.12% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 15 1.29% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 15 1.29% 90.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.52% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.60% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 16 1.37% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.26% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.43% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.17% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.26% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 11 0.95% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.34% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 6 0.52% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.26% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.34% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.26% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 3 0.26% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.26% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.26% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.17% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 5 0.43% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.09% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.09% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 2 0.17% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.09% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.09% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.09% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.17% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.17% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.09% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 1 0.09% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.09% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.17% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.09% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.09% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.09% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.09% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.09% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.09% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation +system.physmem.totQLat 59913750 # Total ticks spent queuing +system.physmem.totMemAccLat 199861250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers +system.physmem.totBankLat 102712500 # Total ticks spent accessing banks +system.physmem.avgQLat 8045.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26837.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6686 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6283 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10416755.11 # Average gap between requests -system.membus.throughput 6143941 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4310 # Transaction distribution -system.membus.trans_dist::ReadResp 4310 # Transaction distribution -system.membus.trans_dist::ReadExReq 3132 # Transaction distribution -system.membus.trans_dist::ReadExResp 3132 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14884 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14884 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476288 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476288 # Total data (bytes) +system.physmem.avgGap 10409062.91 # Average gap between requests +system.physmem.pageHitRate 84.37 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.56 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6148481 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4317 # Transaction distribution +system.membus.trans_dist::ReadResp 4317 # Transaction distribution +system.membus.trans_dist::ReadExReq 3130 # Transaction distribution +system.membus.trans_dist::ReadExResp 3130 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14894 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 476608 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9304000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69668500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69563000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50329141 # Number of BP lookups -system.cpu.branchPred.condPredicted 29286929 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1209855 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26570475 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23288927 # Number of BTB hits +system.cpu.branchPred.lookups 50307165 # Number of BP lookups +system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26317362 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.649645 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9008918 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1078 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.414014 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101805775 # DTB read hits -system.cpu.dtb.read_misses 78244 # DTB read misses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 101884019 # DTB read accesses -system.cpu.dtb.write_hits 78424815 # DTB write hits -system.cpu.dtb.write_misses 1501 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78426316 # DTB write accesses -system.cpu.dtb.data_hits 180230590 # DTB hits -system.cpu.dtb.data_misses 79745 # DTB misses -system.cpu.dtb.data_acv 48606 # DTB access violations -system.cpu.dtb.data_accesses 180310335 # DTB accesses -system.cpu.itb.fetch_hits 50278510 # ITB hits -system.cpu.itb.fetch_misses 355 # ITB misses +system.cpu.dtb.read_hits 101828804 # DTB read hits +system.cpu.dtb.read_misses 77910 # DTB read misses +system.cpu.dtb.read_acv 48604 # DTB read access violations +system.cpu.dtb.read_accesses 101906714 # DTB read accesses +system.cpu.dtb.write_hits 78465960 # DTB write hits +system.cpu.dtb.write_misses 1494 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 78467454 # DTB write accesses +system.cpu.dtb.data_hits 180294764 # DTB hits +system.cpu.dtb.data_misses 79404 # DTB misses +system.cpu.dtb.data_acv 48608 # DTB access violations +system.cpu.dtb.data_accesses 180374168 # DTB accesses +system.cpu.itb.fetch_hits 50297233 # ITB hits +system.cpu.itb.fetch_misses 369 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50278865 # ITB accesses +system.cpu.itb.fetch_accesses 50297602 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,139 +292,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 155043164 # number of cpu cycles simulated +system.cpu.numCycles 155032764 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51171798 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449189873 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50329141 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32297845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78873322 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6177793 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19775166 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 51194246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449183514 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50307165 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78871438 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6172162 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19742012 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10164 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50278510 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 413807 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154759425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.902504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 412893 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75886103 49.03% 49.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4289159 2.77% 51.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6884479 4.45% 56.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5373987 3.47% 59.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11775541 7.61% 67.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7819980 5.05% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5600753 3.62% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1832171 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35297252 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75867710 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35290903 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154759425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324614 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897192 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56546720 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15105326 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74238970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3943829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4924580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9495837 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4282 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445245835 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12211 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4924580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59688043 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4892244 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 416020 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75141817 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9696721 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440741300 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25268 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 413955402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 165462719 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897346 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56553427 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3941388 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4916501 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9487391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4280 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445247205 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4916501 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59699524 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9687111 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440708166 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 170 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18989 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8005915 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287519835 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 579387338 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 414037453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 165349884 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 265 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27780890 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104697675 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80623147 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8951892 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6419862 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408420930 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401925039 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 976126 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32712161 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15467708 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154759425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597096 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996071 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27987506 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36934 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 290 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27862892 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104720393 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80633883 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8938676 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401961013 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 974296 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15321619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154739148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597669 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28451061 18.38% 18.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25861408 16.71% 35.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25614965 16.55% 51.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24252162 15.67% 67.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21259746 13.74% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15502795 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8516760 5.50% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3980528 2.57% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1320000 0.85% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28425453 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25580332 16.53% 51.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21279906 13.75% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15505584 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154759425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154739148 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34116 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 59668 0.50% 0.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5432 0.05% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5299 0.04% 0.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1955339 16.54% 17.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1744150 14.75% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5075259 42.92% 75.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2944520 24.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57850 0.49% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5381 0.05% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1948507 16.46% 17.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748153 14.77% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5077907 42.90% 74.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155814394 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126224 0.53% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32839124 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7506811 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2794214 0.70% 50.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556558 4.12% 54.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1581320 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155836210 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7503461 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2792900 0.69% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16557877 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1579224 0.39% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued @@ -449,84 +446,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103393269 25.72% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79279544 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103415840 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401925039 # Type of FU issued -system.cpu.iq.rate 2.592343 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11823783 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029418 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634356878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260386455 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234772610 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 337052534 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180795959 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161415506 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241485172 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172230069 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15009534 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401961013 # Type of FU issued +system.cpu.iq.rate 2.592749 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11837270 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634505765 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234812476 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241576218 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9943188 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49084 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7102418 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9965906 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 111384 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48996 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7113154 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260799 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3689 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4924580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2516499 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372884 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 433248692 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 121349 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104697675 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80623147 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 81 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49084 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 956530 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 406825 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1363355 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398354690 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101932663 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3570349 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4916501 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130314 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48996 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 956631 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 408580 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3567783 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24827504 # number of nop insts executed -system.cpu.iew.exec_refs 180359006 # number of memory reference insts executed -system.cpu.iew.exec_branches 46573877 # Number of branches executed -system.cpu.iew.exec_stores 78426343 # Number of stores executed -system.cpu.iew.exec_rate 2.569315 # Inst execution rate -system.cpu.iew.wb_sent 396825960 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396188116 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193569295 # num instructions producing a value -system.cpu.iew.wb_consumers 271188688 # num instructions consuming a value +system.cpu.iew.exec_nop 24803859 # number of nop insts executed +system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed +system.cpu.iew.exec_branches 46575028 # Number of branches executed +system.cpu.iew.exec_stores 78467483 # Number of stores executed +system.cpu.iew.exec_rate 2.569736 # Inst execution rate +system.cpu.iew.wb_sent 396861812 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396231790 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193564450 # num instructions producing a value +system.cpu.iew.wb_consumers 271143007 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.555341 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713781 # average fanout of values written-back +system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34614887 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1205659 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149834845 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.660693 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.995613 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55453685 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22592497 15.08% 52.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13053957 8.71% 60.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11447163 7.64% 68.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8190236 5.47% 73.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5440968 3.63% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5148789 3.44% 80.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3296235 2.20% 83.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25211315 16.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55444792 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22572343 15.07% 52.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13039784 8.70% 60.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5171862 3.45% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3280269 2.19% 83.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149834845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149822647 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,212 +534,212 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25211315 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557900023 # The number of ROB reads -system.cpu.rob.rob_writes 871491746 # The number of ROB writes -system.cpu.timesIdled 3551 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 283739 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557859409 # The number of ROB reads +system.cpu.rob.rob_writes 871404727 # The number of ROB writes +system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 293616 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.412816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.412816 # CPI: Total CPI of All Threads -system.cpu.ipc 2.422389 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.422389 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398140602 # number of integer regfile reads -system.cpu.int_regfile_writes 170166273 # number of integer regfile writes -system.cpu.fp_regfile_reads 156587084 # number of floating regfile reads -system.cpu.fp_regfile_writes 104079306 # number of floating regfile writes +system.cpu.cpi 0.412788 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412788 # CPI: Total CPI of All Threads +system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398219851 # number of integer regfile reads +system.cpu.int_regfile_writes 170183529 # number of integer regfile writes +system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads +system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7370748 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 571392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 571392 # Total data (bytes) +system.cpu.toL2Bus.throughput 7356381 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17161 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 570240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 570240 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5130000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5114000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6844000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6775000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6767250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6675000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2147 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.618681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50272888 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4074 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12339.933235 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2141 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50291613 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12359.698452 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.618681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894345 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894345 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50272888 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50272888 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50272888 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50272888 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50272888 # number of overall hits -system.cpu.icache.overall_hits::total 50272888 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5622 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5622 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5622 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5622 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5622 # number of overall misses -system.cpu.icache.overall_misses::total 5622 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 322487500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 322487500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 322487500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 322487500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 322487500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 322487500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50278510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50278510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50278510 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50278510 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50278510 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50278510 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50291613 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50291613 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50291613 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50291613 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50291613 # number of overall hits +system.cpu.icache.overall_hits::total 50291613 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5620 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5620 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5620 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5620 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5620 # number of overall misses +system.cpu.icache.overall_misses::total 5620 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 330576500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 330576500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 330576500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 330576500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 330576500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 330576500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50297233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50297233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50297233 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50297233 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50297233 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50297233 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57361.704020 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 57361.704020 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 57361.704020 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 57361.704020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 57361.704020 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 57361.704020 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 272 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.441281 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58821.441281 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 892 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1548 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1548 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1548 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1548 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1548 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1548 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4074 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4074 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4074 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4074 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4074 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4074 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242677000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242677000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242677000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242677000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242677000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242677000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1551 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1551 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1551 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1551 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1551 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1551 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4069 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4069 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4069 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4069 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249127500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249127500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249127500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249127500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249127500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249127500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59567.255768 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59567.255768 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59567.255768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59567.255768 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.731138 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.731138 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4008.519135 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 851 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4844 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.175681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4006.698259 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 830 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4855 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.170958 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.365398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2979.019245 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 658.134493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011333 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090912 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122330 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 621 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 372.314002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2972.989124 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 661.395133 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011362 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090728 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020184 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.122275 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 613 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 131 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 752 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 666 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 666 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 68 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 68 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 199 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 820 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 199 # number of overall hits -system.cpu.l2cache.overall_hits::total 820 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3453 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4310 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3453 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3989 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7442 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3453 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses -system.cpu.l2cache.overall_misses::total 7442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232383750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 297515750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214217750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214217750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 232383750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 279349750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 511733500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 232383750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 279349750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 511733500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4074 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 988 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5062 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 666 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 666 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3200 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3200 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4074 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4188 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8262 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4074 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4188 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8262 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.847570 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867409 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.851442 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.978750 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.978750 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.847570 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.952483 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.900750 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.847570 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.952483 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.900750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67299.087750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69029.176334 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68396.471903 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68396.471903 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67299.087750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70030.020055 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68762.899758 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67299.087750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70030.020055 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68762.899758 # average overall miss latency +system.cpu.l2cache.ReadReq_hits::total 744 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 659 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 659 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 613 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 191 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 804 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 613 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 191 # number of overall hits +system.cpu.l2cache.overall_hits::total 804 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3456 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 861 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4317 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3456 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3991 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7447 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3456 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3991 # number of overall misses +system.cpu.l2cache.overall_misses::total 7447 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238916500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 66414500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 305331000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 225828500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 225828500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238916500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 292243000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 531159500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238916500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 292243000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 531159500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4069 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 659 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 659 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3190 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3190 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4069 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4182 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8251 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4069 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4182 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8251 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.849349 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867944 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.852993 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981191 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981191 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.954328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.902557 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.954328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.902557 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.931713 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77136.469222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.588603 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72149.680511 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72149.680511 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71325.298778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71325.298778 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,162 +748,162 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3453 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 857 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4310 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3453 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7442 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 188417250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 242915750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 175604250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 175604250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 188417250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 230102750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 418520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 188417250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 230102750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 418520000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867409 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.851442 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978750 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978750 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900750 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847570 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.952483 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54566.246742 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63592.182030 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56360.962877 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56067.768199 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56067.768199 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54566.246742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57684.319378 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56237.570546 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3456 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 861 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4317 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3991 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3991 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7447 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195042500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55799500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250842000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 187339500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 187339500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195042500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 243139000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 438181500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195042500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 243139000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 438181500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.849349 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867944 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852993 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981191 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981191 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902557 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902557 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56435.908565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64807.781649 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58105.628909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59852.875399 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59852.875399 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56435.908565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60921.824104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58840.002686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56435.908565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60921.824104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58840.002686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 788 # number of replacements -system.cpu.dcache.tags.tagsinuse 3294.798817 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 160031202 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4188 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38211.843840 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 780 # number of replacements +system.cpu.dcache.tags.tagsinuse 3295.992263 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 160011153 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38261.873027 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3294.798817 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804394 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86530434 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86530434 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500763 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500763 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 160031197 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 160031197 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 160031197 # number of overall hits -system.cpu.dcache.overall_hits::total 160031197 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1798 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1798 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19966 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19966 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21764 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21764 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21764 # number of overall misses -system.cpu.dcache.overall_misses::total 21764 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114434250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114434250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1039316587 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1039316587 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1153750837 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1153750837 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1153750837 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1153750837 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86532232 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86532232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 3295.992263 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804686 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804686 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86510267 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86510267 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500882 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500882 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 160011149 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 160011149 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 160011149 # number of overall hits +system.cpu.dcache.overall_hits::total 160011149 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1786 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1786 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19847 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19847 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21633 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21633 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21633 # number of overall misses +system.cpu.dcache.overall_misses::total 21633 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114228250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114228250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1085833087 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1085833087 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1200061337 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1200061337 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1200061337 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1200061337 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86512053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86512053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 160052961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 160052961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 160052961 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 160052961 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 160032782 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 160032782 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 160032782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 160032782 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000272 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000272 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63645.300334 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63645.300334 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52054.321697 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52054.321697 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53011.892897 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53011.892897 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53011.892897 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 38531 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63957.586786 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63957.586786 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54710.187283 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54710.187283 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55473.643831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55473.643831 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 40366 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 654 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 653 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.915902 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.816233 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 666 # number of writebacks -system.cpu.dcache.writebacks::total 666 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16766 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16766 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17576 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17576 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17576 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17576 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4188 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4188 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4188 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4188 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67480500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67480500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218199250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 218199250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285679750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 285679750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285679750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 285679750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 659 # number of writebacks +system.cpu.dcache.writebacks::total 659 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16657 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16657 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17451 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17451 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17451 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17451 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 992 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 992 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 68767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 68767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 229720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 229720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298487000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298487000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68300.101215 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68300.101215 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68187.265625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68187.265625 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68213.884909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68213.884909 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69321.572581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69321.572581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72012.539185 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72012.539185 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 8bc1d638d..93aa60ef6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068375 # Number of seconds simulated -sim_ticks 68375005500 # Number of ticks simulated -final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068515 # Number of seconds simulated +sim_ticks 68515366500 # Number of ticks simulated +final_tick 68515366500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143200 # Simulator instruction rate (inst/s) -host_op_rate 183074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35860683 # Simulator tick rate (ticks/s) -host_mem_usage 256516 # Number of bytes of host memory used -host_seconds 1906.68 # Real time elapsed on the host +host_inst_rate 128186 # Simulator instruction rate (inst/s) +host_op_rate 163879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32166693 # Simulator tick rate (ticks/s) +host_mem_usage 283052 # Number of bytes of host memory used +host_seconds 2130.01 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 194304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory system.physmem.bytes_read::total 466432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3034 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 194304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2839868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3981806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6821674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2839868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2839868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7288 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 7288 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 466432 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 353 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 506 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68374814000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7288 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 2835919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3971781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6807699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2835919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2835919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2835919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3971781 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6807699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7289 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7289 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 466496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 466496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 607 # Per bank write bursts +system.physmem.perBankRdBursts::1 801 # Per bank write bursts +system.physmem.perBankRdBursts::2 608 # Per bank write bursts +system.physmem.perBankRdBursts::3 526 # Per bank write bursts +system.physmem.perBankRdBursts::4 443 # Per bank write bursts +system.physmem.perBankRdBursts::5 353 # Per bank write bursts +system.physmem.perBankRdBursts::6 161 # Per bank write bursts +system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::8 207 # Per bank write bursts +system.physmem.perBankRdBursts::9 294 # Per bank write bursts +system.physmem.perBankRdBursts::10 325 # Per bank write bursts +system.physmem.perBankRdBursts::11 416 # Per bank write bursts +system.physmem.perBankRdBursts::12 529 # Per bank write bursts +system.physmem.perBankRdBursts::13 687 # Per bank write bursts +system.physmem.perBankRdBursts::14 611 # Per bank write bursts +system.physmem.perBankRdBursts::15 504 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 68515346000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7289 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,119 +152,120 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 639.554318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.565124 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1324.415379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 223 31.06% 31.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 101 14.07% 45.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 63 8.77% 53.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 56 7.80% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 31 4.32% 66.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 32 4.46% 70.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 2.23% 72.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 24 3.34% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.25% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 16 2.23% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 1.25% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 12 1.67% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.70% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 9 1.25% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 0.97% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.84% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.56% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.42% 87.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.70% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.42% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.42% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.56% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 5 0.70% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.56% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.42% 91.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.42% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.14% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 2 0.28% 94.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.14% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.14% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.14% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.14% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.14% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 718 # Bytes accessed per row activation -system.physmem.totQLat 36604250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 168483000 # Sum of mem lat for all requests -system.physmem.totBusLat 36440000 # Total cycles spent in databus access -system.physmem.totBankLat 95438750 # Total cycles spent in bank access -system.physmem.avgQLat 5022.54 # Average queueing delay per request -system.physmem.avgBankLat 13095.33 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23117.86 # Average memory access latency -system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 1271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 365.973249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.155512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 760.469459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 520 40.91% 40.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 218 17.15% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 133 10.46% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 73 5.74% 74.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 41 3.23% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 37 2.91% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 29 2.28% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 36 2.83% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 1.18% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 25 1.97% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 5 0.39% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 14 1.10% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 4 0.31% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 0.63% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.39% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 8 0.63% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 8 0.63% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 6 0.47% 93.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 7 0.55% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.16% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 5 0.39% 94.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 5 0.39% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.16% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.24% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.24% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.24% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 4 0.31% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.24% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.16% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.24% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1271 # Bytes accessed per row activation +system.physmem.totQLat 60705750 # Total ticks spent queuing +system.physmem.totMemAccLat 196384500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36445000 # Total ticks spent in databus transfers +system.physmem.totBankLat 99233750 # Total ticks spent accessing banks +system.physmem.avgQLat 8328.41 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13614.18 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26942.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6570 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9381835.07 # Average gap between requests -system.membus.throughput 6821674 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4467 # Transaction distribution -system.membus.trans_dist::ReadResp 4467 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 2821 # Transaction distribution -system.membus.trans_dist::ReadExResp 2821 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14586 # Packet count per connected master and slave (bytes) +system.physmem.avgGap 9399827.96 # Average gap between requests +system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.15 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6807699 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4464 # Transaction distribution +system.membus.trans_dist::ReadResp 4463 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 2825 # Transaction distribution +system.membus.trans_dist::ReadExResp 2825 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14581 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 466432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8930000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68010245 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67824498 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35388733 # Number of BP lookups -system.cpu.branchPred.condPredicted 21200896 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1644934 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19122518 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16795427 # Number of BTB hits +system.cpu.branchPred.lookups 35429100 # Number of BP lookups +system.cpu.branchPred.condPredicted 21225812 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1661684 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19625450 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16825398 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.830625 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6785564 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8441 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.732546 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6780528 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8438 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -306,100 +309,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136750012 # number of cpu cycles simulated +system.cpu.numCycles 137030734 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38949353 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317676023 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35388733 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23580991 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70834954 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6803690 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21493719 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1383 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37560816 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 509146 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136426737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.984407 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 39012994 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 318080298 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35429100 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23605926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70957862 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6891670 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21493708 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1614 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37614130 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 516506 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136684696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983709 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454255 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66221739 48.54% 48.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6780898 4.97% 53.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5694782 4.17% 57.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6088849 4.46% 62.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4909575 3.60% 65.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4088004 3.00% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3182942 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4139594 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35320354 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66359879 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6789497 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5708838 4.18% 57.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6107274 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4922167 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4085695 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3186230 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4137086 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35388030 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136426737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258784 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.323042 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45449120 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16657240 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66693516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2548377 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5078484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7335953 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69077 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401163284 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 211870 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5078484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50979253 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1928009 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 329001 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63651330 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14460660 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393604020 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1657735 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10191603 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1572902779 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200313916 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136684696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258549 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.321233 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45532866 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16645865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66825856 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2530463 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5149646 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7344267 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69062 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401846627 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213953 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5149646 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51082336 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1907734 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332489 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63745566 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14466925 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394259426 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1660076 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10182958 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1156 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432806895 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2333828888 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575589736 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200458039 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11830 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36438205 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103461367 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91301104 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4273842 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5281559 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384115412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 48240702 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36507596 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103616420 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91395607 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4296163 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5310753 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384620101 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373986631 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1200950 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34324808 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 86133615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 374263749 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1212133 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34826495 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 87778881 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136426737 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.741300 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023490 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 136684696 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738154 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24929928 18.27% 18.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19932793 14.61% 32.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20578448 15.08% 47.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18152288 13.31% 61.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24038629 17.62% 78.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15699021 11.51% 90.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8799073 6.45% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3376437 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 920120 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25139035 18.39% 18.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19926957 14.58% 32.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20565636 15.05% 48.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18170176 13.29% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24039516 17.59% 78.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15735356 11.51% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814568 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3374876 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 918576 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136426737 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136684696 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8934 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8700 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4687 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -418,127 +421,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46301 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46352 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7704 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 463 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7624 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 437 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190616 1.07% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 3949 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241166 1.36% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9286471 52.35% 55.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7950501 44.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190912 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4399 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241386 1.36% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9273710 52.31% 55.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7950548 44.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126356667 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175742 0.58% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6779199 1.81% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8471128 2.27% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3427474 0.92% 39.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595849 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20859409 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172834 1.92% 47.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127502 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126477598 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175809 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6782032 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8476848 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430270 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595622 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20869694 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7174273 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130259 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101548323 27.15% 76.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88297215 23.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101673859 27.17% 76.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88302195 23.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373986631 # Type of FU issued -system.cpu.iq.rate 2.734820 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17740799 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047437 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653979183 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288208067 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249975124 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249362565 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130269118 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118046236 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263130568 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128596862 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11091317 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374263749 # Type of FU issued +system.cpu.iq.rate 2.731239 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17728757 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047370 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654715892 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289089659 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250133425 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249437192 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130393861 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118075733 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263363212 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128629294 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11082647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8812619 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 109039 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14268 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8925521 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8967672 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 108753 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14263 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9020024 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 177200 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1779 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 174668 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1902 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5078484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 284505 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35417 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384139745 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871852 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103461367 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91301104 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 5149646 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 272927 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35696 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384644450 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871710 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103616420 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91395607 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 311 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 371 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14268 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1284870 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 366093 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1650963 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370046005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100262370 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3940626 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 342 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14263 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1301323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 370771 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1672094 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370296137 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100380791 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3967612 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1545 # number of nop insts executed -system.cpu.iew.exec_refs 187486507 # number of memory reference insts executed -system.cpu.iew.exec_branches 32007235 # Number of branches executed -system.cpu.iew.exec_stores 87224137 # Number of stores executed -system.cpu.iew.exec_rate 2.706003 # Inst execution rate -system.cpu.iew.wb_sent 368676629 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368021360 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182960102 # num instructions producing a value -system.cpu.iew.wb_consumers 363631500 # num instructions consuming a value +system.cpu.iew.exec_nop 1561 # number of nop insts executed +system.cpu.iew.exec_refs 187597519 # number of memory reference insts executed +system.cpu.iew.exec_branches 32011770 # Number of branches executed +system.cpu.iew.exec_stores 87216728 # Number of stores executed +system.cpu.iew.exec_rate 2.702285 # Inst execution rate +system.cpu.iew.wb_sent 368879898 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368209158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183085663 # num instructions producing a value +system.cpu.iew.wb_consumers 363859128 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.691198 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503147 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687055 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503177 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35074746 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35579507 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1576251 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131348253 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.657554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659541 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1592984 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131535050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.653780 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659242 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34568937 26.32% 26.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28443468 21.66% 47.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13309150 10.13% 58.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11454276 8.72% 66.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13766870 10.48% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7405227 5.64% 82.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3876233 2.95% 85.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3903284 2.97% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14620808 11.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34731076 26.40% 26.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28455457 21.63% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13342482 10.14% 58.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11433888 8.69% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13770355 10.47% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7412668 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3873056 2.94% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3888664 2.96% 88.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14627404 11.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131348253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131535050 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -549,220 +552,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14620808 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14627404 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 500864729 # The number of ROB reads -system.cpu.rob.rob_writes 773362160 # The number of ROB writes -system.cpu.timesIdled 6666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 323275 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501549691 # The number of ROB reads +system.cpu.rob.rob_writes 774443009 # The number of ROB writes +system.cpu.timesIdled 6642 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 346038 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.500848 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500848 # CPI: Total CPI of All Threads -system.cpu.ipc 1.996612 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.996612 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1768925077 # number of integer regfile reads -system.cpu.int_regfile_writes 232843327 # number of integer regfile writes -system.cpu.fp_regfile_reads 188113453 # number of floating regfile reads -system.cpu.fp_regfile_writes 132483580 # number of floating regfile writes -system.cpu.misc_regfile_reads 566770577 # number of misc regfile reads +system.cpu.cpi 0.501877 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501877 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1770065591 # number of integer regfile reads +system.cpu.int_regfile_writes 233053939 # number of integer regfile writes +system.cpu.fp_regfile_reads 188169392 # number of floating regfile reads +system.cpu.fp_regfile_writes 132536105 # number of floating regfile writes +system.cpu.misc_regfile_reads 566956802 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20110273 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17610 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17610 # Transaction distribution +system.cpu.toL2Bus.throughput 20102702 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17643 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17642 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 42006 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1015808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1374656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1374656 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 384 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11782000 # Layer occupancy (ticks) +system.cpu.toL2Bus.tot_pkt_size::total 1377088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1377088 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11799000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24379238 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24347988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7509966 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7401462 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13946 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.498389 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37543488 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2370.768376 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13986 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.638823 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37596770 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15875 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2368.300472 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.498389 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902587 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902587 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37543488 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37543488 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37543488 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37543488 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37543488 # number of overall hits -system.cpu.icache.overall_hits::total 37543488 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17326 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17326 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17326 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17326 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17326 # number of overall misses -system.cpu.icache.overall_misses::total 17326 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 439962484 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 439962484 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 439962484 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 439962484 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 439962484 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 439962484 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37560814 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37560814 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37560814 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37560814 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37560814 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37560814 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.638823 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902656 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902656 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37596770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37596770 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37596770 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37596770 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37596770 # number of overall hits +system.cpu.icache.overall_hits::total 37596770 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17358 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17358 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17358 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17358 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17358 # number of overall misses +system.cpu.icache.overall_misses::total 17358 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 450239984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 450239984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 450239984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 450239984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 450239984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 450239984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37614128 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37614128 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37614128 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37614128 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37614128 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37614128 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25393.194275 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25393.194275 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25393.194275 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25393.194275 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25393.194275 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 913 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25938.471252 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25938.471252 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25938.471252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25938.471252 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2006 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 87.217391 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15840 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15840 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15840 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15840 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15840 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15840 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 349391259 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 349391259 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 349391259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 349391259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 349391259 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 349391259 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1481 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1481 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1481 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1481 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1481 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1481 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15877 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15877 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15877 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15877 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15877 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15877 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359424009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359424009 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359424009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359424009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359424009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359424009 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22057.528977 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22057.528977 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22057.528977 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22057.528977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22057.528977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22057.528977 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22638.030421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22638.030421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3937.726706 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13182 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5389 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.446094 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3939.771440 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13217 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5387 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.453499 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 375.051576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2781.709770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 780.965360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011446 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084891 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023833 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120170 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12788 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13086 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 378.229398 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.621740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 774.920301 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085041 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.023649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.120232 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12824 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13123 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1037 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1037 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12788 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 315 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13103 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12788 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 315 # number of overall hits -system.cpu.l2cache.overall_hits::total 13103 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3046 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1472 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4518 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2821 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2821 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4293 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7339 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3046 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4293 # number of overall misses -system.cpu.l2cache.overall_misses::total 7339 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 205637750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 101578250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 307216000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 188534250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 188534250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 205637750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 290112500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 495750250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 205637750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 290112500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 495750250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15834 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1770 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits::cpu.inst 12824 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 316 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13140 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12824 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 316 # number of overall hits +system.cpu.l2cache.overall_hits::total 13140 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3049 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1467 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4516 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2825 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2825 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3049 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4292 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7341 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3049 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4292 # number of overall misses +system.cpu.l2cache.overall_misses::total 7341 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215269250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 108631000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 323900250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 199625500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 199625500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 215269250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 308256500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 523525750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 215269250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 308256500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 523525750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15873 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1766 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17639 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1037 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2838 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2838 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15834 # number of demand (read+write) accesses +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2842 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2842 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15873 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20442 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15834 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20481 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15873 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20442 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192371 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.831638 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.256646 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 20481 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192087 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830691 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.256024 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994010 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994010 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192371 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931641 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359016 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192371 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931641 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.359016 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67510.751806 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69006.963315 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67998.229305 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66832.417582 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66832.417582 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67510.751806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67578.034009 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67550.109007 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67510.751806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67578.034009 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67550.109007 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994018 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994018 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192087 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931424 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.358430 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192087 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931424 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.358430 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70603.230567 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74049.761418 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71722.818866 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70663.893805 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70663.893805 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70603.230567 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71315.318077 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70603.230567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71315.318077 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,176 +775,176 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3034 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1433 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4467 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2821 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2821 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3034 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4254 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7288 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3034 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4254 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7288 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 166700500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 81208500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 247909000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 51005 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 51005 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 153520750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 153520750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 166700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 234729250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 401429750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 166700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 234729250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 401429750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809605 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253749 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3037 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4464 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2825 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2825 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3037 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4252 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3037 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4252 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7289 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176465000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88132000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264597000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 164645000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164645000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176465000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252777000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 429242000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176465000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252777000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 429242000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808041 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253076 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994010 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994010 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356521 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191613 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356521 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54944.133158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56670.272156 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55497.873293 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10201 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10201 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54420.684155 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54420.684155 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54944.133158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55178.479079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55080.920692 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355891 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355891 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58105.037866 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61760.336370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59273.521505 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.415929 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.415929 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1414 # number of replacements -system.cpu.dcache.tags.tagsinuse 3101.863625 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170862922 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3101.535581 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170993874 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37079.627170 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37108.045573 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3101.863625 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757291 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757291 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88809743 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88809743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031242 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11022 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11022 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3101.535581 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757211 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757211 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88940583 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88940583 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11003 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11003 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170840985 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170840985 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170840985 # number of overall hits -system.cpu.dcache.overall_hits::total 170840985 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3962 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3962 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21423 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21423 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170971964 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170971964 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170971964 # number of overall hits +system.cpu.dcache.overall_hits::total 170971964 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3947 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3947 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25385 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25385 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25385 # number of overall misses -system.cpu.dcache.overall_misses::total 25385 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 221925207 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 221925207 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1196433403 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1196433403 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 157000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1418358610 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1418358610 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1418358610 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1418358610 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88813705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88813705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25231 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25231 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25231 # number of overall misses +system.cpu.dcache.overall_misses::total 25231 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 233964205 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 233964205 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1493575344 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1493575344 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1493575344 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1493575344 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88944530 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88944530 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11024 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11005 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11005 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170866370 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170866370 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170866370 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170866370 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56013.429329 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56013.429329 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55848.079307 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55848.079307 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55873.886547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55873.886547 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25209 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1225 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 407 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 170997195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170997195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170997195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170997195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59276.464403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59276.464403 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59181.128500 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59181.128500 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59196.042329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59196.042329 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28298 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 410 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.938575 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 102.083333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.019512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks system.cpu.dcache.writebacks::total 1037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2191 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2191 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18581 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18581 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2179 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2179 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20772 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20772 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20772 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20772 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20621 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20621 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20621 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20621 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1768 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1768 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4613 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4613 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4613 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4613 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106433039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 106433039 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191658495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 191658495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298091534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298091534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298091534 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298091534 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4610 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4610 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4610 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4610 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 113556540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 113556540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 202620998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 202620998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316177538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 316177538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316177538 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 316177538 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -950,14 +953,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60097.706945 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60097.706945 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67437.894089 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67437.894089 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64228.812217 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64228.812217 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71295.213934 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71295.213934 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 580dd6a6a..23516d587 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631883 # Number of seconds simulated -sim_ticks 631883288500 # Number of ticks simulated -final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.631518 # Number of seconds simulated +sim_ticks 631518097500 # Number of ticks simulated +final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151695 # Simulator instruction rate (inst/s) -host_op_rate 151695 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52578725 # Simulator tick rate (ticks/s) -host_mem_usage 240040 # Number of bytes of host memory used -host_seconds 12017.85 # Real time elapsed on the host +host_inst_rate 141288 # Simulator instruction rate (inst/s) +host_op_rate 141288 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48943367 # Simulator tick rate (ticks/s) +host_mem_usage 266484 # Number of bytes of host memory used +host_seconds 12903.04 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295168 # Number of bytes read from this memory -system.physmem.bytes_read::total 30471232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295488 # Number of bytes read from this memory +system.physmem.bytes_read::total 30471616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176128 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473362 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476113 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473367 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476119 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 278634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47944246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48222880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 278634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 278634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6776745 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6776745 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6776745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476114 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 66908 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 476114 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 66908 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30471232 # Total number of bytes read from memory -system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29915 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29583 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29509 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29637 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4099 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4335 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4247 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4100 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4157 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 631883258500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476114 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66908 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 408378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 278896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47972478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48251374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 278896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 278896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6780664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6780664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6780664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 278896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47972478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55032038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476119 # Number of read requests accepted +system.physmem.writeReqs 66908 # Number of write requests accepted +system.physmem.readBursts 476119 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30465984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.bytesWritten 4281664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30471616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29449 # Per bank write bursts +system.physmem.perBankRdBursts::1 29798 # Per bank write bursts +system.physmem.perBankRdBursts::2 29850 # Per bank write bursts +system.physmem.perBankRdBursts::3 29793 # Per bank write bursts +system.physmem.perBankRdBursts::4 29695 # Per bank write bursts +system.physmem.perBankRdBursts::5 29771 # Per bank write bursts +system.physmem.perBankRdBursts::6 29867 # Per bank write bursts +system.physmem.perBankRdBursts::7 29856 # Per bank write bursts +system.physmem.perBankRdBursts::8 29771 # Per bank write bursts +system.physmem.perBankRdBursts::9 29894 # Per bank write bursts +system.physmem.perBankRdBursts::10 29844 # Per bank write bursts +system.physmem.perBankRdBursts::11 29915 # Per bank write bursts +system.physmem.perBankRdBursts::12 29793 # Per bank write bursts +system.physmem.perBankRdBursts::13 29587 # Per bank write bursts +system.physmem.perBankRdBursts::14 29511 # Per bank write bursts +system.physmem.perBankRdBursts::15 29637 # Per bank write bursts +system.physmem.perBankWrBursts::0 4125 # Per bank write bursts +system.physmem.perBankWrBursts::1 4164 # Per bank write bursts +system.physmem.perBankWrBursts::2 4223 # Per bank write bursts +system.physmem.perBankWrBursts::3 4160 # Per bank write bursts +system.physmem.perBankWrBursts::4 4142 # Per bank write bursts +system.physmem.perBankWrBursts::5 4099 # Per bank write bursts +system.physmem.perBankWrBursts::6 4262 # Per bank write bursts +system.physmem.perBankWrBursts::7 4226 # Per bank write bursts +system.physmem.perBankWrBursts::8 4233 # Per bank write bursts +system.physmem.perBankWrBursts::9 4334 # Per bank write bursts +system.physmem.perBankWrBursts::10 4241 # Per bank write bursts +system.physmem.perBankWrBursts::11 4241 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4100 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4157 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 631518039500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 476119 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66908 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 429 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,29 +127,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -157,151 +159,190 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 166584 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 208.562071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.103843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 536.299000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 52740 31.66% 31.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 42613 25.58% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39946 23.98% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 25368 15.23% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 277 0.17% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 122 0.07% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 95 0.06% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 87 0.05% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 83 0.05% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 94 0.06% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 111 0.07% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 115 0.07% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 83 0.05% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 90 0.05% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 77 0.05% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 81 0.05% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 76 0.05% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 74 0.04% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 77 0.05% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 82 0.05% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3443 2.07% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 36 0.02% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 586 0.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 166584 # Bytes accessed per row activation -system.physmem.totQLat 1351239750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14292404750 # Sum of mem lat for all requests -system.physmem.totBusLat 2380120000 # Total cycles spent in databus access -system.physmem.totBankLat 10561045000 # Total cycles spent in bank access -system.physmem.avgQLat 2838.60 # Average queueing delay per request -system.physmem.avgBankLat 22185.95 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30024.55 # Average memory access latency -system.physmem.avgRdBW 48.22 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.22 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.78 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 182335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 190.554573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 126.681752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 408.631079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 68422 37.53% 37.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 48844 26.79% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 37964 20.82% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 20159 11.06% 96.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 264 0.14% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 246 0.13% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 141 0.08% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 184 0.10% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 113 0.06% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 137 0.08% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 96 0.05% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 186 0.10% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 81 0.04% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 159 0.09% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 151 0.08% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 133 0.07% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 108 0.06% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 148 0.08% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 143 0.08% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 80 0.04% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 131 0.07% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 1760 0.97% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 1531 0.84% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 10 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 19 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 18 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 8 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 14 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 14 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 13 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 14 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 6 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 10 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 10 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 20 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 12 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 11 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 18 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 13 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 12 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 17 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 12 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 11 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 14 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 18 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 12 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 10 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 14 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 17 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 14 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 13 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 12 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 9 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 8 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 11 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 18 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 9 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 16 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 12 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 17 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 14 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 15 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 5 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 16 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 14 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 17 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 13 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 15 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 11 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 18 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 12 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 8 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 9 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 12 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 6 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 11 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 11 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 15 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 12 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 12 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 11 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 16 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 12 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 11 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 13 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 16 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 12 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 12 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 17 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 10 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 11 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 22 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 11 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 8 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 12 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 26 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 26 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336 39 0.02% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400 37 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464 7 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528 7 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592 6 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656 3 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720 7 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784 8 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848 54 0.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 182335 # Bytes accessed per row activation +system.physmem.totQLat 2888041500 # Total ticks spent queuing +system.physmem.totMemAccLat 14116019000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2380155000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8847822500 # Total ticks spent accessing banks +system.physmem.avgQLat 6066.92 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18586.65 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29653.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.78 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 11.01 # Average write queue length over time -system.physmem.readRowHits 326147 # Number of row buffer hits during reads -system.physmem.writeRowHits 50200 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes -system.physmem.avgGap 1163642.10 # Average gap between requests -system.membus.throughput 54999625 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409258 # Transaction distribution -system.membus.trans_dist::ReadResp 409257 # Transaction distribution +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.28 # Average write queue length when enqueuing +system.physmem.readRowHits 310714 # Number of row buffer hits during reads +system.physmem.writeRowHits 49883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 65.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes +system.physmem.avgGap 1162958.82 # Average gap between requests +system.physmem.pageHitRate 66.42 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 25.73 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55031937 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409266 # Transaction distribution +system.membus.trans_dist::ReadResp 409265 # Transaction distribution system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66856 # Transaction distribution -system.membus.trans_dist::ReadExResp 66856 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019135 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019135 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753344 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34753344 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34753344 # Total data (bytes) +system.membus.trans_dist::ReadExReq 66853 # Transaction distribution +system.membus.trans_dist::ReadExResp 66853 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019145 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019145 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34753664 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34753664 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1230653000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4527448500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4488013000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 388901077 # Number of BP lookups -system.cpu.branchPred.condPredicted 255997466 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25785874 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 315302493 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258353491 # Number of BTB hits +system.cpu.branchPred.lookups 388926557 # Number of BP lookups +system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25808786 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 317451636 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258383726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.938296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57247417 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6895 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.393100 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57269217 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6785 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522159380 # DTB read hits -system.cpu.dtb.read_misses 590851 # DTB read misses +system.cpu.dtb.read_hits 522276153 # DTB read hits +system.cpu.dtb.read_misses 591029 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522750231 # DTB read accesses -system.cpu.dtb.write_hits 283002528 # DTB write hits -system.cpu.dtb.write_misses 50162 # DTB write misses +system.cpu.dtb.read_accesses 522867182 # DTB read accesses +system.cpu.dtb.write_hits 283024283 # DTB write hits +system.cpu.dtb.write_misses 50282 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283052690 # DTB write accesses -system.cpu.dtb.data_hits 805161908 # DTB hits -system.cpu.dtb.data_misses 641013 # DTB misses +system.cpu.dtb.write_accesses 283074565 # DTB write accesses +system.cpu.dtb.data_hits 805300436 # DTB hits +system.cpu.dtb.data_misses 641311 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 805802921 # DTB accesses -system.cpu.itb.fetch_hits 394748041 # ITB hits -system.cpu.itb.fetch_misses 630 # ITB misses +system.cpu.dtb.data_accesses 805941747 # DTB accesses +system.cpu.itb.fetch_hits 394923337 # ITB hits +system.cpu.itb.fetch_misses 673 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394748671 # ITB accesses +system.cpu.itb.fetch_accesses 394924010 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -315,98 +356,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1263766578 # number of cpu cycles simulated +system.cpu.numCycles 1263036196 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 409917284 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3274493634 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388901077 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315600908 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630100236 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157853545 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75868728 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6965 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394748041 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11243258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1247472116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.624903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.139302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 410109211 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3275361916 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388926557 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315652943 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630278695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157942219 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 76359250 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7183 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394923337 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11250821 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1248398015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.623652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.139094 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 617371880 49.49% 49.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57447684 4.61% 54.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43286408 3.47% 57.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71838123 5.76% 63.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129156368 10.35% 73.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46178870 3.70% 77.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41219816 3.30% 80.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7663689 0.61% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233309278 18.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 618119320 49.51% 49.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57470502 4.60% 54.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43321703 3.47% 57.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71848580 5.76% 63.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129169735 10.35% 73.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46220345 3.70% 77.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41223037 3.30% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7614963 0.61% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233409830 18.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1247472116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307732 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.591059 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438201536 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62209215 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606414230 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9080438 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131566697 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31709739 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12402 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3193700667 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46294 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131566697 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467502237 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27351671 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28189 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 585846018 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35177304 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3094945067 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15191 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3493818421 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85375087 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1248398015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307930 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.593245 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438388188 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62722157 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 606598506 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9057712 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131631452 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31714965 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12425 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3194311917 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46335 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131631452 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467678490 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27888697 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27235 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586017174 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35154967 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3095577928 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15278 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28853292 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2054701915 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3579840201 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3494452831 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 85387369 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109722880 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 743716097 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351305913 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69009362 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8819654 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2623113984 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 93 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2159995607 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17916537 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 800006156 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726205656 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 54 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1247472116 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.731498 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 669732845 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4230 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109697167 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 743928173 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351370571 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69056444 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8824928 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2623617017 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2160251370 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17943532 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 800506396 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 726504541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1248398015 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.730419 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 450995748 36.15% 36.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196797874 15.78% 51.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251286832 20.14% 72.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120757727 9.68% 81.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104717605 8.39% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79196335 6.35% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24309118 1.95% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17642931 1.41% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767946 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 451794383 36.19% 36.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196881070 15.77% 51.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251357257 20.13% 72.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120660417 9.67% 81.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104720930 8.39% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79314006 6.35% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24236778 1.94% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17665275 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1767899 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1247472116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1248398015 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146304 3.11% 3.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146213 3.11% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available @@ -435,16 +476,16 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25641829 69.66% 72.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10023004 27.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25664248 69.68% 72.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10022787 27.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234267096 57.14% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17095 0.00% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234386708 57.14% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17098 0.00% 57.14% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851364 1.29% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851280 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued @@ -469,84 +510,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589311123 27.28% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293086828 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589426190 27.29% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293107997 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2159995607 # Type of FU issued -system.cpu.iq.rate 1.709173 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36811137 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017042 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5471089482 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3335131409 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1989836434 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101522 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88062076 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73609987 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2119354134 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449858 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62153092 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2160251370 # Type of FU issued +system.cpu.iq.rate 1.710364 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36833248 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017050 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5472576315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3336085104 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1990052080 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101220 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88112403 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73609796 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2119632114 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449752 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62130294 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 232646071 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31940 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 75814 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140511017 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 232858147 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12904 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76517 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140575675 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4421 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2886 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4420 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2986 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131566697 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13318869 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540046 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2986589244 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 731786 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 743716097 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351305913 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 93 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 134266 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1522 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 75814 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25780444 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 27789 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25808233 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2065907774 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522750367 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94087833 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131631452 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13854870 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540713 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2987064962 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 734569 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 743928173 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351370571 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 134613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1496 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76517 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25801220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 30372 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25831592 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2066130188 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 522867337 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94121182 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363475167 # number of nop insts executed -system.cpu.iew.exec_refs 805803501 # number of memory reference insts executed -system.cpu.iew.exec_branches 277598296 # Number of branches executed -system.cpu.iew.exec_stores 283053134 # Number of stores executed -system.cpu.iew.exec_rate 1.634723 # Inst execution rate -system.cpu.iew.wb_sent 2065776472 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063446421 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180901001 # num instructions producing a value -system.cpu.iew.wb_consumers 1753223374 # num instructions consuming a value +system.cpu.iew.exec_nop 363447857 # number of nop insts executed +system.cpu.iew.exec_refs 805942372 # number of memory reference insts executed +system.cpu.iew.exec_branches 277625839 # Number of branches executed +system.cpu.iew.exec_stores 283075035 # Number of stores executed +system.cpu.iew.exec_rate 1.635844 # Inst execution rate +system.cpu.iew.wb_sent 2066015512 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2063661876 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180966909 # num instructions producing a value +system.cpu.iew.wb_consumers 1753315236 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.632775 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673560 # average fanout of values written-back +system.cpu.iew.wb_rate 1.633890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673562 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 960640976 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 961121272 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25773841 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1115905419 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.800321 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.507651 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25796748 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1116766563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.798932 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.506928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 496848865 44.52% 44.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228666687 20.49% 65.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119877587 10.74% 75.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58838951 5.27% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50501288 4.53% 85.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24162159 2.17% 87.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19119877 1.71% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16606359 1.49% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101283646 9.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 497624739 44.56% 44.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228755329 20.48% 65.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119853189 10.73% 75.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58815833 5.27% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50567042 4.53% 85.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24161277 2.16% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19140455 1.71% 89.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16628477 1.49% 90.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101220222 9.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1115905419 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1116766563 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -557,212 +598,212 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101283646 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101220222 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3978613943 # The number of ROB reads -system.cpu.rob.rob_writes 6070825883 # The number of ROB writes -system.cpu.timesIdled 341889 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16294462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3980018807 # The number of ROB reads +system.cpu.rob.rob_writes 6071851296 # The number of ROB writes +system.cpu.timesIdled 346634 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14638181 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.693218 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.693218 # CPI: Total CPI of All Threads -system.cpu.ipc 1.442548 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.442548 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2627733458 # number of integer regfile reads -system.cpu.int_regfile_writes 1496469824 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811377 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661114 # number of floating regfile writes +system.cpu.cpi 0.692817 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.692817 # CPI: Total CPI of All Threads +system.cpu.ipc 1.443382 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.443382 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2627972093 # number of integer regfile reads +system.cpu.int_regfile_writes 1496658984 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811105 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661052 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 165896459 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470294 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71645 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71645 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20089 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159776 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3179865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104184384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104827200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104827200 # Total data (bytes) +system.cpu.toL2Bus.throughput 165988542 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470276 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 71640 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3179804 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 641536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104183232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 104824768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104824768 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914949000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 914915000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15605000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 15531000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2398320750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2359590250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8334 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.074457 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 394735107 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10044 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39300.588112 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 8311 # number of replacements +system.cpu.icache.tags.tagsinuse 1658.001589 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 394910394 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10024 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39396.487829 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1655.074457 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.808142 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.808142 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 394735107 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394735107 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394735107 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394735107 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394735107 # number of overall hits -system.cpu.icache.overall_hits::total 394735107 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12934 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12934 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12934 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12934 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12934 # number of overall misses -system.cpu.icache.overall_misses::total 12934 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 381722499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 381722499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 381722499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 381722499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 381722499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 381722499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394748041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394748041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394748041 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394748041 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394748041 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394748041 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394910394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394910394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394910394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394910394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394910394 # number of overall hits +system.cpu.icache.overall_hits::total 394910394 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12943 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12943 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12943 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12943 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12943 # number of overall misses +system.cpu.icache.overall_misses::total 12943 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 383675499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 383675499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 383675499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 383675499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 383675499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 383675499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394923337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394923337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394923337 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394923337 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394923337 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394923337 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29513.104917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29513.104917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29513.104917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29513.104917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29513.104917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 646 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29643.475160 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29643.475160 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29643.475160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29643.475160 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.692308 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 54.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2889 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2889 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2889 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2889 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2889 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2889 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10045 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10045 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10045 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10045 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10045 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10045 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 280085749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 280085749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 280085749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 280085749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 280085749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 280085749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2918 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2918 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2918 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2918 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2918 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2918 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10025 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10025 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10025 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10025 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10025 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10025 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281680749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281680749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281680749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281680749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281680749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281680749 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27883.100946 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27883.100946 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27883.100946 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27883.100946 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.830324 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.830324 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 443335 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32690.569488 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1090072 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 476070 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.289731 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 443340 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32689.012035 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1090033 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 476076 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.289620 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1328.456107 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.162790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31326.950592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.956023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997637 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7293 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1053744 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1061037 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 95986 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95986 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4789 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4789 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7293 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1058533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065826 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7293 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1058533 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065826 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1332.840421 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.208896 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31320.962718 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.040675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001074 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.955840 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997589 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7273 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1053738 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1061011 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 95971 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 95971 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4787 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4787 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7273 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1058525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065798 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7273 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1058525 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065798 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2752 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406506 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409258 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66856 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66856 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406514 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 409266 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66853 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66853 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2752 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 473362 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476114 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 473367 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 476119 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2752 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 473362 # number of overall misses -system.cpu.l2cache.overall_misses::total 476114 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197100250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29768533500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29965633750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5039202250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5039202250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 197100250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 34807735750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35004836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 197100250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 34807735750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35004836000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10045 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1460250 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1470295 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 95986 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 95986 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 71645 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71645 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10045 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1531895 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1541940 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10045 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1531895 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1541940 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.273967 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278381 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.278351 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933157 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.933157 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.273967 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.309004 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.308776 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.273967 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.309004 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.308776 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71620.730378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73230.243834 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73219.420879 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75373.971670 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75373.971670 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71620.730378 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73533.016486 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73521.963227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71620.730378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73533.016486 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73521.963227 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 473367 # number of overall misses +system.cpu.l2cache.overall_misses::total 476119 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198914750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29323124000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29522038750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5227072250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5227072250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198914750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 34550196250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34749111000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198914750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 34550196250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34749111000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10025 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460252 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1470277 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 95971 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 95971 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71640 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71640 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10025 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1531892 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1541917 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10025 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1531892 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1541917 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.274514 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278386 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278360 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933180 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933180 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274514 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309008 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308784 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274514 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309008 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308784 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72280.069041 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72133.122106 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.110212 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78187.549549 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78187.549549 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72280.069041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72984.088012 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72280.069041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72984.088012 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,161 +815,177 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks system.cpu.l2cache.writebacks::total 66908 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2752 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406506 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409258 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406514 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409266 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66853 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66853 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2752 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 473362 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476114 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473367 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476119 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2752 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473362 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476114 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 162299250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24552049500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24714348750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4233681750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4233681750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 162299250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28785731250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28948030500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 162299250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28785731250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28948030500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278351 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933157 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933157 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308776 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.273967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308776 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58975.018169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60397.754277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60388.187280 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63325.382165 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63325.382165 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58975.018169 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58975.018169 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.242242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60800.628631 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 473367 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476119 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164199250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24183867000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24348066250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4422430250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4422430250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164199250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28606297250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28770496500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164199250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28606297250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28770496500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278386 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278360 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308784 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308784 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59665.425145 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59490.858863 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.032688 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66151.560139 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66151.560139 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59665.425145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.112760 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59665.425145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.112760 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1527799 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.613876 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 667806397 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1531895 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 435.934837 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 399882250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.613876 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999662 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 458073360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458073360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733012 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667806372 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667806372 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 667806372 # number of overall hits -system.cpu.dcache.overall_hits::total 667806372 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925786 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925786 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061884 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061884 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2987670 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987670 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987670 # number of overall misses -system.cpu.dcache.overall_misses::total 2987670 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76327323000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76327323000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 44999711104 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 44999711104 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121327034104 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121327034104 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121327034104 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121327034104 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 459999146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 459999146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 1527796 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.588575 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 667945835 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531892 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 436.026714 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 408904250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.588575 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999655 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999655 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458212871 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458212871 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209732941 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209732941 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 667945812 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 667945812 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 667945812 # number of overall hits +system.cpu.dcache.overall_hits::total 667945812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925756 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925756 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061955 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061955 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2987711 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987711 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987711 # number of overall misses +system.cpu.dcache.overall_misses::total 2987711 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391156750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77391156750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191877602 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 46191877602 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 123583034352 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 123583034352 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 123583034352 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 123583034352 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460138627 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460138627 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 25 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 25 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 670794042 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 670794042 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 670794042 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 670794042 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004186 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004186 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 670933523 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 670933523 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 670933523 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 670933523 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004185 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004185 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004454 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004454 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004454 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004454 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39634.374224 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39634.374224 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42377.238101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42377.238101 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40609.248714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40609.248714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18768 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.041667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004453 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004453 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004453 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004453 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.415618 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.415618 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.019744 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.019744 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41363.784634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41363.784634 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17901 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 132 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 338 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.086455 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.961538 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95986 # number of writebacks -system.cpu.dcache.writebacks::total 95986 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465536 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465536 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990239 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990239 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455775 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455775 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455775 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455775 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460250 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460250 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71645 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71645 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531895 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531895 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531895 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531895 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41766827000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41766827000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5159100250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5159100250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46925927250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46925927250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46925927250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46925927250 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks +system.cpu.dcache.writebacks::total 95971 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465505 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465505 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990315 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990315 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455820 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455820 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455820 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455820 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460251 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460251 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71640 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71640 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531891 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531891 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531891 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531891 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41321289000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41321289000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5347166250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5347166250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 76000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 76000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46668455250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46668455250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46668455250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46668455250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28602.518062 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28602.518062 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72009.215577 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72009.215577 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28297.387915 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28297.387915 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74639.394891 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74639.394891 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 76000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 76000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index d3db51b2e..2fb0bf01c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.640648 # Number of seconds simulated -sim_ticks 640648369500 # Number of ticks simulated -final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.633885 # Number of seconds simulated +sim_ticks 633884897500 # Number of ticks simulated +final_tick 633884897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92518 # Simulator instruction rate (inst/s) -host_op_rate 125998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42814979 # Simulator tick rate (ticks/s) -host_mem_usage 256100 # Number of bytes of host memory used -host_seconds 14963.18 # Real time elapsed on the host +host_inst_rate 87779 # Simulator instruction rate (inst/s) +host_op_rate 119542 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40192628 # Simulator tick rate (ticks/s) +host_mem_usage 283676 # Number of bytes of host memory used +host_seconds 15771.17 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory -system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242944 # Number of bytes read from this memory +system.physmem.bytes_read::total 30398080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472546 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474970 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30399488 # Total number of bytes read from memory -system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 640648293500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474992 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66098 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 244738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47710466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47955205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 244738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 244738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6673565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6673565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6673565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 244738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47710466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54628770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474970 # Number of read requests accepted +system.physmem.writeReqs 66098 # Number of write requests accepted +system.physmem.readBursts 474970 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30392000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue +system.physmem.bytesWritten 4230080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30398080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4324 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29875 # Per bank write bursts +system.physmem.perBankRdBursts::1 29673 # Per bank write bursts +system.physmem.perBankRdBursts::2 29745 # Per bank write bursts +system.physmem.perBankRdBursts::3 29707 # Per bank write bursts +system.physmem.perBankRdBursts::4 29817 # Per bank write bursts +system.physmem.perBankRdBursts::5 29835 # Per bank write bursts +system.physmem.perBankRdBursts::6 29655 # Per bank write bursts +system.physmem.perBankRdBursts::7 29450 # Per bank write bursts +system.physmem.perBankRdBursts::8 29485 # Per bank write bursts +system.physmem.perBankRdBursts::9 29492 # Per bank write bursts +system.physmem.perBankRdBursts::10 29547 # Per bank write bursts +system.physmem.perBankRdBursts::11 29655 # Per bank write bursts +system.physmem.perBankRdBursts::12 29700 # Per bank write bursts +system.physmem.perBankRdBursts::13 29805 # Per bank write bursts +system.physmem.perBankRdBursts::14 29629 # Per bank write bursts +system.physmem.perBankRdBursts::15 29805 # Per bank write bursts +system.physmem.perBankWrBursts::0 4174 # Per bank write bursts +system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.perBankWrBursts::2 4138 # Per bank write bursts +system.physmem.perBankWrBursts::3 4148 # Per bank write bursts +system.physmem.perBankWrBursts::4 4226 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4094 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 633884833500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 474970 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66098 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -125,29 +127,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -157,113 +159,161 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation -system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests -system.physmem.totBusLat 2374200000 # Total cycles spent in databus access -system.physmem.totBankLat 10704210000 # Total cycles spent in bank access -system.physmem.avgQLat 3976.96 # Average queueing delay per request -system.physmem.avgBankLat 22542.77 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31519.74 # Average memory access latency -system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.42 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 17.45 # Average write queue length over time -system.physmem.readRowHits 318007 # Number of row buffer hits during reads -system.physmem.writeRowHits 49644 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes -system.physmem.avgGap 1183995.81 # Average gap between requests -system.membus.throughput 54054139 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408917 # Transaction distribution -system.membus.trans_dist::ReadResp 408916 # Transaction distribution +system.physmem.bytesPerActivate::samples 190556 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.682403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 122.345891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 377.529861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 76623 40.21% 40.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 50018 26.25% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 37571 19.72% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 19599 10.29% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 202 0.11% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 233 0.12% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 93 0.05% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 219 0.11% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 79 0.04% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 59 0.03% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 225 0.12% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 74 0.04% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 178 0.09% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 61 0.03% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 176 0.09% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 47 0.02% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 188 0.10% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 71 0.04% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 186 0.10% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 71 0.04% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 3176 1.67% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 17 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 14 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 12 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 11 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 7 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 10 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 16 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 14 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 23 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 18 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 9 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 13 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 10 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 12 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 24 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 8 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 18 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 22 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 22 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 14 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 11 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 10 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 8 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 14 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 4 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 19 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 19 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 21 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 17 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 18 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 12 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 19 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 10 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 12 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 10 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 12 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 16 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 16 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 16 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 31 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 17 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 10 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 9 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 11 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 6 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 17 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 16 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 14 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 19 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 17 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 16 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 3 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 13 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 6 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 7 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 7 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 10 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 14 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 20 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 16 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 12 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 34 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 69 0.04% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 58 0.03% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 59 0.03% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 190556 # Bytes accessed per row activation +system.physmem.totQLat 3723849000 # Total ticks spent queuing +system.physmem.totMemAccLat 15162897750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2374375000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9064673750 # Total ticks spent accessing banks +system.physmem.avgQLat 7841.75 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 19088.55 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31930.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 47.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 47.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.67 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.43 # Data bus utilization in percentage +system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.41 # Average write queue length when enqueuing +system.physmem.readRowHits 301072 # Number of row buffer hits during reads +system.physmem.writeRowHits 49342 # Number of row buffer hits during writes +system.physmem.readRowHitRate 63.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.65 # Row buffer hit rate for writes +system.physmem.avgGap 1171543.75 # Average gap between requests +system.physmem.pageHitRate 64.77 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 24.91 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54628770 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408895 # Transaction distribution +system.membus.trans_dist::ReadResp 408895 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4324 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4324 # Transaction distribution system.membus.trans_dist::ReadExReq 66075 # Transaction distribution system.membus.trans_dist::ReadExResp 66075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34629696 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024686 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628352 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34628352 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34628352 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1216897000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4442648676 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 451070712 # Number of BP lookups -system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups -system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits +system.cpu.branchPred.lookups 445875274 # Number of BP lookups +system.cpu.branchPred.condPredicted 355714891 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 31013117 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262160312 # Number of BTB lookups +system.cpu.branchPred.BTBHits 234316871 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.379231 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52540791 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2805997 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -307,100 +357,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1281296740 # number of cpu cycles simulated +system.cpu.numCycles 1267769796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed -system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 359604051 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2297734506 # Number of instructions fetch has processed +system.cpu.fetch.Branches 445875274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 286857662 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 606667357 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 159378109 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 130943287 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11360 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 340050056 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11891209 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1225539818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.573745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.170795 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 618917347 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42971146 3.51% 54.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 97897325 7.99% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 56071890 4.58% 66.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 75061628 6.12% 72.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45063261 3.68% 76.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31435951 2.57% 78.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31903606 2.60% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226217664 18.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12321480350 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90240197 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1225539818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.351701 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.812423 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 410024939 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 104223819 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 567090713 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15899066 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 128301281 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 47087821 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11947 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3044373258 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 26488 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 128301281 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 445072814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37752394 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 469546 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 545867989 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68075794 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2962731385 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4402501 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 53439360 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 9 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2946792223 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14100168268 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12232464769 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 87261724 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 953652133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20387 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17854 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 175792199 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 972804227 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 491413736 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36509550 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 42116928 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2808310459 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27673 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2443543142 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13552705 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 910455744 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2345608138 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6289 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1225539818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.993850 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.871016 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 386142313 31.51% 31.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183212489 14.95% 46.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204921233 16.72% 63.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 171581285 14.00% 77.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 134431508 10.97% 88.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92278264 7.53% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37194117 3.03% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12766594 1.04% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3012015 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1225539818 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 692354 0.79% 0.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24381 0.03% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available @@ -428,118 +478,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55108221 62.64% 63.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 32145057 36.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1110380096 45.44% 45.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223911 0.46% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502670 0.23% 46.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23408416 0.96% 47.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 840781219 34.41% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 443995061 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued -system.cpu.iq.rate 1.917842 # Inst issue rate -system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2443543142 # Type of FU issued +system.cpu.iq.rate 1.927434 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87970013 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6090822143 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3633185531 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2257760958 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 123326677 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 85675338 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56498576 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2467787139 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63726016 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 85165626 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341417046 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1428012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 214418439 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 322 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 128301281 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16032166 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1560767 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2808350603 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 961806 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 972804227 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 491413736 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 17687 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1557116 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1428012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32911757 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1861954 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 34773711 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2367002070 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794874980 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 76541072 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12463 # number of nop insts executed -system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed -system.cpu.iew.exec_branches 324680497 # Number of branches executed -system.cpu.iew.exec_stores 426903851 # Number of stores executed -system.cpu.iew.exec_rate 1.856653 # Inst execution rate -system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1354756756 # num instructions producing a value -system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value +system.cpu.iew.exec_nop 12471 # number of nop insts executed +system.cpu.iew.exec_refs 1219940656 # number of memory reference insts executed +system.cpu.iew.exec_branches 321608336 # Number of branches executed +system.cpu.iew.exec_stores 425065676 # Number of stores executed +system.cpu.iew.exec_rate 1.867060 # Inst execution rate +system.cpu.iew.wb_sent 2340031230 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2314259534 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1351078205 # num instructions producing a value +system.cpu.iew.wb_consumers 2527156960 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back +system.cpu.iew.wb_rate 1.825457 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534624 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 923014366 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 31001379 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1097238537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.718256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.389874 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 455331878 41.50% 41.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 289999556 26.43% 67.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95581485 8.71% 76.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70096070 6.39% 83.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46571745 4.24% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22195585 2.02% 89.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15856765 1.45% 90.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11363497 1.04% 91.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90241956 8.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1097238537 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -550,222 +600,222 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90241956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3844759887 # The number of ROB reads -system.cpu.rob.rob_writes 5783698867 # The number of ROB writes -system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3815328960 # The number of ROB reads +system.cpu.rob.rob_writes 5745013824 # The number of ROB writes +system.cpu.timesIdled 352945 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42229978 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads -system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads -system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads -system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes -system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads +system.cpu.cpi 0.915773 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.915773 # CPI: Total CPI of All Threads +system.cpu.ipc 1.091973 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.091973 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11799440532 # number of integer regfile reads +system.cpu.int_regfile_writes 2227507770 # number of integer regfile writes +system.cpu.fp_regfile_reads 68853045 # number of floating regfile reads +system.cpu.fp_regfile_writes 49554235 # number of floating regfile writes +system.cpu.misc_regfile_reads 1367872939 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 167773046 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1492868 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1492867 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96315 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52441 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3231415 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1539648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104532224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106071872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106071872 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 276928 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929329999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 42995247 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2368559798 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 22329 # number of replacements -system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 22373 # number of replacements +system.cpu.icache.tags.tagsinuse 1644.727747 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 340012575 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24056 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14134.210800 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits -system.cpu.icache.overall_hits::total 345973619 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30537 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30537 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30537 # number of overall misses -system.cpu.icache.overall_misses::total 30537 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 527751245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 527751245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 527751245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 527751245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 527751245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 527751245 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 346004156 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 346004156 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 346004156 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 346004156 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 346004156 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 346004156 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17282.354030 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17282.354030 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1734 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1644.727747 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.803090 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.803090 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 340019150 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 340019150 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 340019150 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 340019150 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 340019150 # number of overall hits +system.cpu.icache.overall_hits::total 340019150 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 30904 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 30904 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 30904 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 30904 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 30904 # number of overall misses +system.cpu.icache.overall_misses::total 30904 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 530577244 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 530577244 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 530577244 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 530577244 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 530577244 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 530577244 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 340050054 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 340050054 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 340050054 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 340050054 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 340050054 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 340050054 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000091 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000091 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17168.562128 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17168.562128 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17168.562128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17168.562128 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1738 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.187500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.064516 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2162 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2162 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2162 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2162 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2162 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2162 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28375 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28375 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28375 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28375 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28375 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28375 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 422292499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 422292499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 422292499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 422292499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 422292499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 422292499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2520 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2520 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2520 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2520 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2520 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2520 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28384 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28384 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28384 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28384 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28384 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28384 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424232750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 424232750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424232750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 424232750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424232750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 424232750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000083 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000083 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000083 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14946.193278 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14946.193278 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442208 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32680.533022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1109569 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474957 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.336146 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 442189 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32678.484609 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1109448 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474936 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.335995 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1291.826262 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.114345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.039423 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001529 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.956378 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997331 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1057872 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1079450 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96304 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96304 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6444 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6444 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21578 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1064316 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1085894 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21578 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1064316 # number of overall hits -system.cpu.l2cache.overall_hits::total 1085894 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2434 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406511 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408945 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4361 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4361 # number of UpgradeReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 1308.214481 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.900676 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31321.369452 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.039924 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001492 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.955852 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997268 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 21631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1057987 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1079618 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96315 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96315 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 6443 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6443 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 21631 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1064430 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1086061 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 21631 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1064430 # number of overall hits +system.cpu.l2cache.overall_hits::total 1086061 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 408923 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4324 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4324 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2434 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 472586 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475020 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2434 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 472586 # number of overall misses -system.cpu.l2cache.overall_misses::total 475020 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 173732500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30711118250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30884850750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4593677250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4593677250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 173732500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35304795500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35478528000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 173732500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35304795500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35478528000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 24012 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1464383 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1488395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 96304 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96304 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4364 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4364 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72519 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 24012 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1536902 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1560914 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24012 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1536902 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1560914 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101366 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277599 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.274756 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911141 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911141 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101366 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307493 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.304322 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101366 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307493 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.304322 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71377.362366 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75548.062045 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75523.238455 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69522.167991 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69522.167991 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74688.493116 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71377.362366 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74705.546715 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74688.493116 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 472572 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2426 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 472572 # number of overall misses +system.cpu.l2cache.overall_misses::total 474998 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175176750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30663807500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30838984250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756616500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4756616500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 175176750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35420424000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35595600750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 175176750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35420424000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35595600750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 24057 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1464484 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1488541 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 96315 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 96315 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4328 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4328 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72518 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72518 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 24057 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1537002 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1561059 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24057 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1537002 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1561059 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100844 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277570 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.274714 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999076 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999076 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911153 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911153 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100844 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.307463 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.304279 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100844 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.307463 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.304279 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72208.058533 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75434.277498 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75415.137446 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71988.142263 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71988.142263 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74938.422372 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74938.422372 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,184 +835,184 @@ system.cpu.l2cache.demand_mshr_hits::total 28 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2432 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406485 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408917 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4361 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4361 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406471 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 408895 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4324 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4324 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2432 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 472560 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 474992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2432 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 472560 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 474992 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 142964000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25574268250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25717232250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43614361 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43614361 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3760538250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3760538250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142964000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29334806500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29477770500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142964000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29334806500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29477770500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277581 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274737 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911141 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911141 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304304 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101283 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307476 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304304 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58784.539474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62915.650639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62891.081197 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 472546 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474970 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 472546 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 474970 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 144597750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25603608250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25748206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43244324 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43244324 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924227000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924227000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144597750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29527835250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29672433000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144597750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29527835250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29672433000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999076 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999076 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911153 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911153 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304261 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304261 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59652.537129 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62989.999902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62970.214847 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56913.178207 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.495649 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.495649 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1532805 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.435174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 972917364 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1536901 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 633.038409 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 392115250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.435174 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999618 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999618 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 696790485 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 696790485 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276093216 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276093216 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1532905 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.387385 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 971436889 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1537001 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 632.033999 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 400661250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.387385 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999606 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999606 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 695310256 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 695310256 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276092959 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276092959 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 972883701 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 972883701 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 972883701 # number of overall hits -system.cpu.dcache.overall_hits::total 972883701 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953888 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953888 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 842462 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 842462 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 971403215 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 971403215 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 971403215 # number of overall hits +system.cpu.dcache.overall_hits::total 971403215 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1954136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1954136 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 842719 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 842719 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2796350 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2796350 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2796350 # number of overall misses -system.cpu.dcache.overall_misses::total 2796350 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79173694807 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79173694807 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 56852278531 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 56852278531 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 204750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 136025973338 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 136025973338 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 136025973338 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 136025973338 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 698744373 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 698744373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2796855 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2796855 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2796855 # number of overall misses +system.cpu.dcache.overall_misses::total 2796855 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80332980069 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80332980069 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58617620770 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58617620770 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 225000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 138950600839 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 138950600839 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 138950600839 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 138950600839 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 697264392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697264392 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 975680051 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 975680051 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 975680051 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 975680051 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002796 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002796 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 974200070 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974200070 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974200070 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974200070 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 68250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 68250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48644.115843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48644.115843 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2745 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41109.206355 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41109.206355 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69557.730121 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69557.730121 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49681.017013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49681.017013 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2430 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 892 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 86 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.392857 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.372093 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks -system.cpu.dcache.writebacks::total 96304 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96315 # number of writebacks +system.cpu.dcache.writebacks::total 96315 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489650 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489650 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765875 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765875 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1255525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1255525 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1255525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1255525 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464486 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76844 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76844 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541330 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541330 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541330 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541330 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42708562776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42708562776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4994223926 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4994223926 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47702786702 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47702786702 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47702786702 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47702786702 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29162.834452 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29162.834452 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64991.722529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64991.722529 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index c7e2525ee..4f4f69eed 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043769 # Number of seconds simulated -sim_ticks 43769191000 # Number of ticks simulated -final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043690 # Number of seconds simulated +sim_ticks 43690025000 # Number of ticks simulated +final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69144 # Simulator instruction rate (inst/s) -host_op_rate 69144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34257993 # Simulator tick rate (ticks/s) -host_mem_usage 232832 # Number of bytes of host memory used -host_seconds 1277.63 # Real time elapsed on the host +host_inst_rate 111109 # Simulator instruction rate (inst/s) +host_op_rate 111109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54950396 # Simulator tick rate (ticks/s) +host_mem_usage 264576 # Number of bytes of host memory used +host_seconds 795.08 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -23,81 +23,83 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10386118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 231632520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242018638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10386118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10386118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166688208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166688208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166688208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165515 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 113997 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 165515 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 113997 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 10592960 # Total number of bytes read from memory -system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10593 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6998 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6769 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6938 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7284 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43769170000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165515 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 10404938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 232052236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242457174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10404938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10404938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166990245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166990245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166990245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10404938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 232052236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 409447420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165515 # Number of read requests accepted +system.physmem.writeReqs 113997 # Number of write requests accepted +system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10592832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10379 # Per bank write bursts +system.physmem.perBankRdBursts::1 10437 # Per bank write bursts +system.physmem.perBankRdBursts::2 10256 # Per bank write bursts +system.physmem.perBankRdBursts::3 10015 # Per bank write bursts +system.physmem.perBankRdBursts::4 10350 # Per bank write bursts +system.physmem.perBankRdBursts::5 10362 # Per bank write bursts +system.physmem.perBankRdBursts::6 9796 # Per bank write bursts +system.physmem.perBankRdBursts::7 10273 # Per bank write bursts +system.physmem.perBankRdBursts::8 10509 # Per bank write bursts +system.physmem.perBankRdBursts::9 10590 # Per bank write bursts +system.physmem.perBankRdBursts::10 10479 # Per bank write bursts +system.physmem.perBankRdBursts::11 10188 # Per bank write bursts +system.physmem.perBankRdBursts::12 10237 # Per bank write bursts +system.physmem.perBankRdBursts::13 10581 # Per bank write bursts +system.physmem.perBankRdBursts::14 10468 # Per bank write bursts +system.physmem.perBankRdBursts::15 10593 # Per bank write bursts +system.physmem.perBankWrBursts::0 7081 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::4 7125 # Per bank write bursts +system.physmem.perBankWrBursts::5 7173 # Per bank write bursts +system.physmem.perBankWrBursts::6 6769 # Per bank write bursts +system.physmem.perBankWrBursts::7 7091 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6938 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts +system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::13 7284 # Per bank write bursts +system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 43690004000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 165515 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 113997 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,188 +127,195 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 366.351698 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.645495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 749.158032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 19754 40.46% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7696 15.76% 56.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4247 8.70% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2897 5.93% 70.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2142 4.39% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1740 3.56% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1303 2.67% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1111 2.28% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 826 1.69% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 678 1.39% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 468 0.96% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 525 1.08% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 411 0.84% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 341 0.70% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 262 0.54% 90.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 362 0.74% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 210 0.43% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 226 0.46% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 155 0.32% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 229 0.47% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 390 0.80% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 303 0.62% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 582 1.19% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 207 0.42% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 152 0.31% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 46 0.09% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 145 0.30% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 73 0.15% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 52 0.11% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 28 0.06% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 72 0.15% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 42 0.09% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 23 0.05% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.10% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 25 0.05% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 11 0.02% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 23 0.05% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 7 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 13 0.03% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 21 0.04% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 13 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 14 0.03% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 8 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 9 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 5 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 8 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 3 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 6 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 12 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48826 # Bytes accessed per row activation -system.physmem.totQLat 6287289000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8773086500 # Sum of mem lat for all requests -system.physmem.totBusLat 827575000 # Total cycles spent in databus access -system.physmem.totBankLat 1658222500 # Total cycles spent in bank access -system.physmem.avgQLat 37986.22 # Average queueing delay per request -system.physmem.avgBankLat 10018.56 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53004.78 # Average memory access latency -system.physmem.avgRdBW 242.02 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 166.69 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.02 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 166.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.19 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 10.49 # Average write queue length over time -system.physmem.readRowHits 153779 # Number of row buffer hits during reads -system.physmem.writeRowHits 76898 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.46 # Row buffer hit rate for writes -system.physmem.avgGap 156591.38 # Average gap between requests -system.membus.throughput 408706846 # Throughput (bytes/s) +system.physmem.bytesPerActivate::samples 51391 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.059076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.605304 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 670.587406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 21918 42.65% 42.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7689 14.96% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4202 8.18% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3191 6.21% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2222 4.32% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1690 3.29% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1284 2.50% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1159 2.26% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 851 1.66% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 652 1.27% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 530 1.03% 88.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 483 0.94% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 404 0.79% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 335 0.65% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 260 0.51% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 388 0.75% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 222 0.43% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 237 0.46% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 182 0.35% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 255 0.50% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 215 0.42% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 327 0.64% 94.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 148 0.29% 95.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 683 1.33% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 243 0.47% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 177 0.34% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 59 0.11% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 192 0.37% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 83 0.16% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 80 0.16% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 48 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 87 0.17% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 58 0.11% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 48 0.09% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 40 0.08% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 14 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 34 0.07% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 26 0.05% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 13 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 18 0.04% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 12 0.02% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 26 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 7 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 17 0.03% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 6 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 10 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 11 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 13 0.03% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 10 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 6 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 3 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 20 0.04% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 11 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 15 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 13 0.03% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 8 0.02% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 4 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 6 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 24 0.05% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 73 0.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 51391 # Bytes accessed per row activation +system.physmem.totQLat 6031819750 # Total ticks spent queuing +system.physmem.totMemAccLat 8481513500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827565000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1622128750 # Total ticks spent accessing banks +system.physmem.avgQLat 36443.18 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9800.61 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 51243.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 242.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 166.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 242.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 166.99 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.busUtilRead 1.89 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing +system.physmem.readRowHits 151507 # Number of row buffer hits during reads +system.physmem.writeRowHits 76598 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.19 # Row buffer hit rate for writes +system.physmem.avgGap 156308.15 # Average gap between requests +system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 10.59 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 409447420 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34625 # Transaction distribution system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution @@ -318,39 +327,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1218630500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1522799000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1521664000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.cpu.branchPred.lookups 18742730 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318368 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18742723 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15507340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4664027 # Number of BTB hits +system.cpu.branchPred.BTBLookups 15507309 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664026 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076254 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.076308 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277790 # DTB read hits +system.cpu.dtb.read_hits 20277713 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367938 # DTB read accesses -system.cpu.dtb.write_hits 14728966 # DTB write hits +system.cpu.dtb.read_accesses 20367861 # DTB read accesses +system.cpu.dtb.write_hits 14728970 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736218 # DTB write accesses -system.cpu.dtb.data_hits 35006756 # DTB hits +system.cpu.dtb.write_accesses 14736222 # DTB write accesses +system.cpu.dtb.data_hits 35006683 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35104156 # DTB accesses -system.cpu.itb.fetch_hits 12367759 # ITB hits +system.cpu.dtb.data_accesses 35104083 # DTB accesses +system.cpu.itb.fetch_hits 12367758 # ITB hits system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378780 # ITB accesses +system.cpu.itb.fetch_accesses 12378779 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -364,34 +373,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87538383 # number of cpu cycles simulated +system.cpu.numCycles 87380051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8074238 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668492 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74161920 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074237 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668486 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74161830 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126481170 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 126481080 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14174454 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 14174544 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 35060070 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed. +system.cpu.execution_unit.executions 44777932 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77194023 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77196543 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 231301 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17962893 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69575490 # Number of cycles cpu stages are processed. -system.cpu.activity 79.479981 # Percentage of cycles cpu is active +system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575628 # Number of cycles cpu stages are processed. +system.cpu.activity 79.624156 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -403,157 +412,157 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.990918 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.989126 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.990918 # CPI: Total CPI of All Threads -system.cpu.ipc 1.009165 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.989126 # CPI: Total CPI of All Threads +system.cpu.ipc 1.010994 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.009165 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34882792 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52655591 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.151432 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45083196 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42455187 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.498939 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44507774 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43030609 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.156276 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65417325 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22121058 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.270124 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.010994 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34724442 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655609 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.260447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44924893 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455158 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.586786 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44349560 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030491 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.245212 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65259184 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120867 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.315695 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41338146 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46041905 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.691552 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1906.431852 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250505 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760360 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250515 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250515 # number of overall hits -system.cpu.icache.overall_hits::total 12250515 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117235 # number of overall misses -system.cpu.icache.overall_misses::total 117235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2053420481 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2053420481 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2053420481 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2053420481 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2053420481 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2053420481 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367750 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367750 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367750 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367750 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009479 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009479 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009479 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009479 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009479 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009479 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17515.421854 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17515.421854 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17515.421854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17515.421854 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250505 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250505 # number of overall hits +system.cpu.icache.overall_hits::total 12250505 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117242 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117242 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117242 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117242 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117242 # number of overall misses +system.cpu.icache.overall_misses::total 117242 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2020332731 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2020332731 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2020332731 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2020332731 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2020332731 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2020332731 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367747 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367747 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367747 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17232.158535 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17232.158535 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17232.158535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17232.158535 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 376 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.117647 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30818 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30818 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30818 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30818 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30818 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30818 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30825 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30825 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30825 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30825 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30825 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30825 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1462353516 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1462353516 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1462353516 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1462353516 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1462353516 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1432321765 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1432321765 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1432321765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1432321765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1432321765 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1432321765 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16922.058345 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16922.058345 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16574.537012 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16574.537012 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 671326642 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution +system.cpu.toL2Bus.throughput 672540151 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168351 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577043 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 749877 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29383296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383296 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397908000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 131178984 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 130875735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 325637219 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30890.802594 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151432 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925335 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27098.006137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.747165 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1785.049292 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168352 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168352 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 112369 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168351 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168351 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125249 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 45934 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 125248 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45935 # number of overall hits -system.cpu.l2cache.overall_hits::total 125249 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 45934 # number of overall hits +system.cpu.l2cache.overall_hits::total 125248 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 34625 # number of ReadReq misses @@ -565,52 +574,52 @@ system.cpu.l2cache.demand_misses::total 165515 # nu system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses system.cpu.l2cache.overall_misses::total 165515 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 580141750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2014348750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2594490500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13747919500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13747919500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 580141750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15762268250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16342410000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 580141750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15762268250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16342410000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 550125750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2043322000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2593447750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13452980750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 550125750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15496302750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16046428500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 550125750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15496302750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16046428500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168351 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168351 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290763 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290763 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454331 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235554 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775215 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569244 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81675.594819 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73190.493060 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74931.133574 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105034.146994 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105034.146994 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98736.730810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98736.730810 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569244 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.814042 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.814042 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 96948.485032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 96948.485032 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -632,73 +641,73 @@ system.cpu.l2cache.demand_mshr_misses::total 165515 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 490395250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665695250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156090500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12145170500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12145170500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 490395250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13810865750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14301261000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 490395250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13810865750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14301261000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 460945750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695556500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156502250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11851363750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11851363750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460945750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13546920250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14007866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460945750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13546920250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14007866000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454331 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235554 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569244 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69040.581444 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60522.318509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62269.761733 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92789.139736 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92789.139736 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569244 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64894.516402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61607.314149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62281.653430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90544.455268 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90544.455268 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200251 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574569 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754840 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754840 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754840 # number of overall hits -system.cpu.dcache.overall_hits::total 33754840 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038808 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038808 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135175 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135175 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135175 # number of overall misses -system.cpu.dcache.overall_misses::total 1135175 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010614984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5010614984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 87491278500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 87491278500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92501893484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92501893484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92501893484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92501893484 # number of overall miss cycles +system.cpu.dcache.tags.replacements 200250 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.382661 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33754883 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204346 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.184946 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 297515000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574591 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754883 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754883 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754883 # number of overall hits +system.cpu.dcache.overall_hits::total 33754883 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96346 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96346 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038786 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038786 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135132 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses +system.cpu.dcache.overall_misses::total 1135132 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5098666734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765880 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85921765880 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91020432614 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91020432614 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91020432614 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91020432614 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -707,56 +716,56 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071086 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51995.133023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51995.133023 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84222.761569 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84222.761569 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81486.901565 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81486.901565 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5878259 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 106 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116796 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.377950 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.377950 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634839 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634839 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80184.888290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80184.888290 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.329284 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 106 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.220352 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks -system.cpu.dcache.writebacks::total 168352 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35600 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35600 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895228 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895228 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930828 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930828 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930828 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930828 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks +system.cpu.dcache.writebacks::total 168351 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35580 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35580 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895206 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895206 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930786 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930786 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930786 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930786 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2409027516 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2409027516 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14018315000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14018315000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16427342516 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16427342516 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16427342516 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16427342516 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723509265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723509265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161452281 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16161452281 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161452281 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16161452281 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -765,14 +774,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39643.680221 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39643.680221 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97634.176069 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97634.176069 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.925373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.925373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f889e2dcc..5daeaeb73 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024977 # Number of seconds simulated -sim_ticks 24977022500 # Number of ticks simulated -final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024874 # Number of seconds simulated +sim_ticks 24873813500 # Number of ticks simulated +final_tick 24873813500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179872 # Simulator instruction rate (inst/s) -host_op_rate 179872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56446381 # Simulator tick rate (ticks/s) -host_mem_usage 238148 # Number of bytes of host memory used -host_seconds 442.49 # Real time elapsed on the host +host_inst_rate 165069 # Simulator instruction rate (inst/s) +host_op_rate 165069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51586823 # Simulator tick rate (ticks/s) +host_mem_usage 265596 # Number of bytes of host memory used +host_seconds 482.17 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 489600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10643136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7650 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166305 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19617390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 406515068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 426132458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19617390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19617390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 292149475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 292149475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 292149475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166305 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 114016 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 166305 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 114016 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 10643520 # Total number of bytes read from memory -system.physmem.bytesWritten 7297024 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10060 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10625 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24976988500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166305 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114016 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.num_reads::total 166299 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19683351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408201822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 427885173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19683351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19683351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 293364264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 293364264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 293364264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19683351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408201822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 721249438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166299 # Number of read requests accepted +system.physmem.writeReqs 114017 # Number of write requests accepted +system.physmem.readBursts 166299 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10643008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7296896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10643136 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10432 # Per bank write bursts +system.physmem.perBankRdBursts::1 10453 # Per bank write bursts +system.physmem.perBankRdBursts::2 10310 # Per bank write bursts +system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::4 10431 # Per bank write bursts +system.physmem.perBankRdBursts::5 10400 # Per bank write bursts +system.physmem.perBankRdBursts::6 9846 # Per bank write bursts +system.physmem.perBankRdBursts::7 10320 # Per bank write bursts +system.physmem.perBankRdBursts::8 10615 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10549 # Per bank write bursts +system.physmem.perBankRdBursts::11 10234 # Per bank write bursts +system.physmem.perBankRdBursts::12 10280 # Per bank write bursts +system.physmem.perBankRdBursts::13 10614 # Per bank write bursts +system.physmem.perBankRdBursts::14 10489 # Per bank write bursts +system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankWrBursts::0 7083 # Per bank write bursts +system.physmem.perBankWrBursts::1 7257 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts +system.physmem.perBankWrBursts::3 6997 # Per bank write bursts +system.physmem.perBankWrBursts::4 7126 # Per bank write bursts +system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 7093 # Per bank write bursts +system.physmem.perBankWrBursts::8 7227 # Per bank write bursts +system.physmem.perBankWrBursts::9 6941 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::13 7287 # Per bank write bursts +system.physmem.perBankWrBursts::14 7286 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24873779500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 166299 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,230 +127,233 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49952 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.130045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.640646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 741.801736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 20814 41.67% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7820 15.66% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4185 8.38% 65.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3013 6.03% 71.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2148 4.30% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1700 3.40% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1301 2.60% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1098 2.20% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 776 1.55% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 657 1.32% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 496 0.99% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 568 1.14% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 406 0.81% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 302 0.60% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 268 0.54% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 357 0.71% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 241 0.48% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 170 0.34% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 145 0.29% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 323 0.65% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 351 0.70% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 146 0.29% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 301 0.60% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 689 1.38% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 236 0.47% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 76 0.15% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 36 0.07% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 184 0.37% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 89 0.18% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 34 0.07% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 40 0.08% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 93 0.19% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 64 0.13% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 19 0.04% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 44 0.09% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 19 0.04% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 19 0.04% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 36 0.07% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 21 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 12 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 20 0.04% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 10 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 10 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 15 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 9 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 8 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 9 0.02% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 10 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 5 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 11 0.02% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 7 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 169 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49952 # Bytes accessed per row activation -system.physmem.totQLat 6557959000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8953517750 # Sum of mem lat for all requests -system.physmem.totBusLat 831510000 # Total cycles spent in databus access -system.physmem.totBankLat 1564048750 # Total cycles spent in bank access -system.physmem.avgQLat 39434.04 # Average queueing delay per request -system.physmem.avgBankLat 9404.87 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53838.91 # Average memory access latency -system.physmem.avgRdBW 426.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 292.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 426.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 292.15 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.61 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.36 # Average read queue length over time -system.physmem.avgWrQLen 9.86 # Average write queue length over time -system.physmem.readRowHits 154145 # Number of row buffer hits during reads -system.physmem.writeRowHits 76216 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.85 # Row buffer hit rate for writes -system.physmem.avgGap 89101.38 # Average gap between requests -system.membus.throughput 718281933 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35508 # Transaction distribution -system.membus.trans_dist::ReadResp 35508 # Transaction distribution -system.membus.trans_dist::Writeback 114016 # Transaction distribution -system.membus.trans_dist::ReadExReq 130797 # Transaction distribution -system.membus.trans_dist::ReadExResp 130797 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446626 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446626 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940544 # Total data (bytes) +system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.243169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.634788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 670.449971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 22509 43.19% 43.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7813 14.99% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4251 8.16% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3108 5.96% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2227 4.27% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1678 3.22% 79.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1376 2.64% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1167 2.24% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 816 1.57% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 658 1.26% 87.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 508 0.97% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 506 0.97% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 390 0.75% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 297 0.57% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 306 0.59% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 440 0.84% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 200 0.38% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 185 0.36% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 164 0.31% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 351 0.67% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 222 0.43% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 266 0.51% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 128 0.25% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 805 1.54% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 220 0.42% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 67 0.13% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 43 0.08% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 225 0.43% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 103 0.20% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.10% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 84 0.16% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 57 0.11% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 36 0.07% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 55 0.11% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 21 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 12 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 17 0.03% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 18 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 24 0.05% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 13 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 9 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 11 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 6 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 11 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 9 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 13 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 6 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 10 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 6 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 8 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 7 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 8 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation +system.physmem.totQLat 6321612000 # Total ticks spent queuing +system.physmem.totMemAccLat 8667027000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831485000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1513930000 # Total ticks spent accessing banks +system.physmem.avgQLat 38013.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9103.77 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 52117.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 427.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 293.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 427.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 293.36 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.63 # Data bus utilization in percentage +system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.68 # Average write queue length when enqueuing +system.physmem.readRowHits 152202 # Number of row buffer hits during reads +system.physmem.writeRowHits 75997 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.65 # Row buffer hit rate for writes +system.physmem.avgGap 88734.78 # Average gap between requests +system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 721249438 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35493 # Transaction distribution +system.membus.trans_dist::ReadResp 35493 # Transaction distribution +system.membus.trans_dist::Writeback 114017 # Transaction distribution +system.membus.trans_dist::ReadExReq 130806 # Transaction distribution +system.membus.trans_dist::ReadExResp 130806 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446615 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17940224 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940224 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242127000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1541382250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1539178500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) -system.cpu.branchPred.lookups 16531947 # Number of BP lookups -system.cpu.branchPred.condPredicted 10672978 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 414050 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11481292 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7335496 # Number of BTB hits +system.cpu.branchPred.lookups 16532535 # Number of BP lookups +system.cpu.branchPred.condPredicted 10677865 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 412540 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11187771 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7331268 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.890858 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1991572 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 40927 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.529300 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1986493 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41581 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22403443 # DTB read hits -system.cpu.dtb.read_misses 219972 # DTB read misses -system.cpu.dtb.read_acv 45 # DTB read access violations -system.cpu.dtb.read_accesses 22623415 # DTB read accesses -system.cpu.dtb.write_hits 15699616 # DTB write hits -system.cpu.dtb.write_misses 41064 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15740680 # DTB write accesses -system.cpu.dtb.data_hits 38103059 # DTB hits -system.cpu.dtb.data_misses 261036 # DTB misses -system.cpu.dtb.data_acv 46 # DTB access violations -system.cpu.dtb.data_accesses 38364095 # DTB accesses -system.cpu.itb.fetch_hits 13905618 # ITB hits -system.cpu.itb.fetch_misses 35229 # ITB misses +system.cpu.dtb.read_hits 22399036 # DTB read hits +system.cpu.dtb.read_misses 220951 # DTB read misses +system.cpu.dtb.read_acv 40 # DTB read access violations +system.cpu.dtb.read_accesses 22619987 # DTB read accesses +system.cpu.dtb.write_hits 15703469 # DTB write hits +system.cpu.dtb.write_misses 40937 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 15744406 # DTB write accesses +system.cpu.dtb.data_hits 38102505 # DTB hits +system.cpu.dtb.data_misses 261888 # DTB misses +system.cpu.dtb.data_acv 45 # DTB access violations +system.cpu.dtb.data_accesses 38364393 # DTB accesses +system.cpu.itb.fetch_hits 13899355 # ITB hits +system.cpu.itb.fetch_misses 34906 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13940847 # ITB accesses +system.cpu.itb.fetch_accesses 13934261 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -362,98 +367,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49954048 # number of cpu cycles simulated +system.cpu.numCycles 49747630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15782352 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105305571 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16531947 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9327068 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19535430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1996105 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7525610 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314470 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13905618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 207845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44615196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.360307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15785028 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105317585 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16532535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9317761 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19533050 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1994568 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7608263 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7898 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 310217 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13899355 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 208294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44693564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.356437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120216 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25079766 56.21% 56.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1526701 3.42% 59.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1368492 3.07% 62.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1511592 3.39% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4137930 9.27% 75.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1849422 4.15% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 676249 1.52% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069566 2.40% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7395478 16.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25160514 56.30% 56.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1525973 3.41% 59.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1366086 3.06% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510374 3.38% 66.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4139884 9.26% 75.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1847459 4.13% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671184 1.50% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1072337 2.40% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7399753 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44615196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.330943 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.108049 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16870832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7056928 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18547803 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 794977 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743758 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107019 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103586885 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 307942 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17339272 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4755583 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85639 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18836599 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2253447 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102335224 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2492 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122982558 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319719 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44693564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.332328 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.117037 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16872770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7137515 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18556178 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 782832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344269 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743968 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106931 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103592319 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 303311 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344269 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17342531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4850765 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18829662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2241354 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102344042 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 512 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2574 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2122740 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61629886 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123330813 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123015128 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 315684 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5530 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4823408 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23239875 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16264209 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1185310 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 465013 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90722071 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5344 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88415019 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95015 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10694229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4666218 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44615196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981724 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109954 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9083005 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5522 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4827061 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23228738 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16269123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1186061 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452179 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90719899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5267 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88414674 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10680066 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4660295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 684 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44693564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.978242 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.110252 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16409410 36.78% 36.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6866152 15.39% 52.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5567351 12.48% 64.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4772569 10.70% 75.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4725060 10.59% 85.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2625070 5.88% 91.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1917083 4.30% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1291638 2.90% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 440863 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16504766 36.93% 36.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6842289 15.31% 52.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5576642 12.48% 64.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4760179 10.65% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4735432 10.60% 85.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2623142 5.87% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1921443 4.30% 96.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1284900 2.87% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 444771 1.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44615196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44693564 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126842 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126888 6.81% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available @@ -482,19 +487,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 784071 42.12% 48.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 950643 51.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 786366 42.17% 48.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 951332 51.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49344695 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43834 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49347874 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43826 0.05% 55.86% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121349 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121152 0.14% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38963 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120827 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120926 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38966 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -516,84 +521,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22855764 25.85% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15889119 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848043 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15894065 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88415019 # Type of FU issued -system.cpu.iq.rate 1.769927 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1861556 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021055 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222796879 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101023469 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86533748 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 604926 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415943 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294379 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89974024 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302551 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1471412 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88414674 # Type of FU issued +system.cpu.iq.rate 1.777264 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1864586 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021089 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222880329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101013312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86537625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 602080 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 409925 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89978136 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301124 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1470512 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2963237 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4955 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18224 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1650832 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2952100 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4699 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655746 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2867 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 96301 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2987 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 95590 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344656 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3651094 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 72855 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100203758 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 216158 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23239875 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16264209 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5344 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49772 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6561 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18224 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192723 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161669 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 354392 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87578159 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22626447 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 836860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344269 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3728175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74875 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100203568 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23228738 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16269123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5267 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49826 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 191969 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 352171 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87579420 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22623199 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 835254 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9476343 # number of nop insts executed -system.cpu.iew.exec_refs 38367436 # number of memory reference insts executed -system.cpu.iew.exec_branches 15087087 # Number of branches executed -system.cpu.iew.exec_stores 15740989 # Number of stores executed -system.cpu.iew.exec_rate 1.753174 # Inst execution rate -system.cpu.iew.wb_sent 87216851 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86828127 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33345535 # num instructions producing a value -system.cpu.iew.wb_consumers 43468305 # num instructions consuming a value +system.cpu.iew.exec_nop 9478402 # number of nop insts executed +system.cpu.iew.exec_refs 38367932 # number of memory reference insts executed +system.cpu.iew.exec_branches 15082234 # Number of branches executed +system.cpu.iew.exec_stores 15744733 # Number of stores executed +system.cpu.iew.exec_rate 1.760474 # Inst execution rate +system.cpu.iew.wb_sent 87221630 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86831789 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33348400 # num instructions producing a value +system.cpu.iew.wb_consumers 43473071 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.738160 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767123 # average fanout of values written-back +system.cpu.iew.wb_rate 1.745446 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767105 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8869178 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8866636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 309326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43270540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.041589 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791914 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 307777 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43349295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.037880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791190 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20425554 47.20% 47.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7044262 16.28% 63.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3374707 7.80% 71.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2054728 4.75% 76.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2036437 4.71% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1166697 2.70% 83.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108378 2.56% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 724905 1.68% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5334872 12.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20524240 47.35% 47.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7032147 16.22% 63.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3350548 7.73% 71.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2057076 4.75% 76.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2049777 4.73% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1169910 2.70% 83.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1109421 2.56% 86.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718391 1.66% 87.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5337785 12.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43270540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43349295 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,212 +609,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5334872 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5337785 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133828176 # The number of ROB reads -system.cpu.rob.rob_writes 195767077 # The number of ROB writes -system.cpu.timesIdled 83938 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5338852 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133901476 # The number of ROB reads +system.cpu.rob.rob_writes 195761663 # The number of ROB writes +system.cpu.timesIdled 83653 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5054066 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.627628 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.627628 # CPI: Total CPI of All Threads -system.cpu.ipc 1.593299 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.593299 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115893073 # number of integer regfile reads -system.cpu.int_regfile_writes 57500612 # number of integer regfile writes -system.cpu.fp_regfile_reads 249654 # number of floating regfile reads -system.cpu.fp_regfile_writes 240130 # number of floating regfile writes -system.cpu.misc_regfile_reads 38049 # number of misc regfile reads +system.cpu.cpi 0.625035 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625035 # CPI: Total CPI of All Threads +system.cpu.ipc 1.599911 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599911 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115904116 # number of integer regfile reads +system.cpu.int_regfile_writes 57506232 # number of integer regfile writes +system.cpu.fp_regfile_reads 249599 # number of floating regfile reads +system.cpu.fp_regfile_writes 239957 # number of floating regfile writes +system.cpu.misc_regfile_reads 38110 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1198592827 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580061 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 766612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5969600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29937280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes) +system.cpu.toL2Bus.throughput 1204474416 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168935 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143420 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187275 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 767312 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5992768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29959872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29959872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402997000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141571734 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141831227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326236500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91227 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13799737 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13799737 # number of overall hits -system.cpu.icache.overall_hits::total 13799737 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105880 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105880 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105880 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105880 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105880 # number of overall misses -system.cpu.icache.overall_misses::total 105880 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2067336982 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2067336982 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2067336982 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2067336982 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2067336982 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2067336982 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13905617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13905617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13905617 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13905617 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13905617 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13905617 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007614 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007614 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007614 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007614 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007614 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007614 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19525.283170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19525.283170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19525.283170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19525.283170 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.icache.tags.replacements 91589 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.117780 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13792950 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93637 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.302348 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20015752250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.117780 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940487 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940487 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13792950 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13792950 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13792950 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13792950 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13792950 # number of overall hits +system.cpu.icache.overall_hits::total 13792950 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses +system.cpu.icache.overall_misses::total 106403 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2026702474 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2026702474 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2026702474 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2026702474 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2026702474 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2026702474 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13899353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13899353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13899353 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13899353 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13899353 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13899353 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007655 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007655 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007655 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007655 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007655 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007655 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19047.418531 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19047.418531 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19047.418531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19047.418531 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 673 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 35.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.866667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12604 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93276 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93276 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93276 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93276 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93276 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1585767766 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1585767766 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1585767766 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1585767766 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1585767766 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1585767766 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006708 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006708 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006708 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006708 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17000.812278 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17000.812278 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17000.812278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17000.812278 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12765 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12765 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12765 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12765 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12765 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12765 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93638 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93638 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93638 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93638 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93638 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93638 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1554482273 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1554482273 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1554482273 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1554482273 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1554482273 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1554482273 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006737 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006737 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006737 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16600.976879 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16600.976879 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16600.976879 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16600.976879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16600.976879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16600.976879 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132400 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30717.176709 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 159637 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164461 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.970668 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132395 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30693.596872 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159984 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164457 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.972801 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26388.752281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2106.212865 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2222.211563 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.805321 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064277 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.067817 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937414 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85619 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34304 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 119923 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168929 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168929 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12613 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12613 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 85619 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46917 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132536 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 85619 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46917 # number of overall hits -system.cpu.l2cache.overall_hits::total 132536 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7657 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27852 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35509 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130797 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130797 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7657 # number of demand (read+write) misses +system.cpu.l2cache.tags.occ_blocks::writebacks 26343.566994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2104.284685 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2245.745192 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.803942 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064218 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.068535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.936694 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 85987 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34288 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 120275 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168935 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168935 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12614 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12614 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 85987 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46902 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132889 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 85987 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46902 # number of overall hits +system.cpu.l2cache.overall_hits::total 132889 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7651 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27843 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35494 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130806 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130806 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7651 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 158649 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166306 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7657 # number of overall misses +system.cpu.l2cache.demand_misses::total 166300 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7651 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158649 # number of overall misses -system.cpu.l2cache.overall_misses::total 166306 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 635688000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2109478250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2745166250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14069629000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14069629000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 635688000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 16179107250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16814795250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 635688000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 16179107250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16814795250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 93276 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62156 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 155432 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168929 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168929 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143410 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143410 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 93276 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205566 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 298842 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 93276 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205566 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 298842 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082090 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448098 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.228454 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_misses::total 166300 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 600341000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2116503000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2716844000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13805964000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13805964000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 600341000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15922467000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16522808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 600341000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15922467000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16522808000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 93638 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62131 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 155769 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168935 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168935 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143420 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143420 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93638 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205551 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 299189 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93638 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205551 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 299189 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081708 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448134 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.227863 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912049 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.912049 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082090 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771767 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.556501 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082090 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771767 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.556501 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83020.504114 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75738.842812 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77309.027289 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107568.438114 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107568.438114 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.504114 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101980.518314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 101107.568278 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.504114 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101980.518314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 101107.568278 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081708 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771823 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555836 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081708 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771823 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555836 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78465.690759 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76015.623316 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76543.753874 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105545.341957 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105545.341957 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78465.690759 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100362.857629 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 99355.429946 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78465.690759 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100362.857629 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 99355.429946 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -818,164 +823,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114016 # number of writebacks -system.cpu.l2cache.writebacks::total 114016 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7657 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27852 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35509 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130797 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130797 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7657 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 114017 # number of writebacks +system.cpu.l2cache.writebacks::total 114017 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7651 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27843 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35494 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130806 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130806 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7651 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158649 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166306 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7657 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166300 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7651 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158649 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166306 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 538279000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1751974750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2290253750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12463858000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12463858000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538279000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14215832750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14754111750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538279000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14215832750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14754111750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448098 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228454 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 166300 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503573000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1760000500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2263573500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12201880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12201880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503573000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13961880500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14465453500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503573000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13961880500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14465453500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.227863 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912049 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912049 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771767 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556501 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771767 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556501 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70298.942144 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62903.014146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64497.838576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95291.619838 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95291.619838 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70298.942144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70298.942144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555836 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771823 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555836 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65817.932296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63211.597170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63773.412408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93282.265340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93282.265340 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201470 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574108 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34190013 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34190013 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34190013 # number of overall hits -system.cpu.dcache.overall_hits::total 34190013 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267467 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267467 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039269 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039269 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306736 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306736 # number of overall misses -system.cpu.dcache.overall_misses::total 1306736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15939734750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15939734750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 90566913172 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 90566913172 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106506647922 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106506647922 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106506647922 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106506647922 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20883372 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20883372 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 201455 # number of replacements +system.cpu.dcache.tags.tagsinuse 4074.008979 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34185233 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205551 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.310225 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 220306250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4074.008979 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994631 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994631 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20611135 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20611135 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574043 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34185178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34185178 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34185178 # number of overall hits +system.cpu.dcache.overall_hits::total 34185178 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267491 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267491 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039334 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039334 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306825 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306825 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306825 # number of overall misses +system.cpu.dcache.overall_misses::total 1306825 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16297490000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16297490000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89003554001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89003554001 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105301044001 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105301044001 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105301044001 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105301044001 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20878626 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20878626 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35496749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35496749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35496749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35496749 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036813 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036813 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59595.145382 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59595.145382 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87144.823113 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 87144.823113 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81505.864935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81505.864935 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5253118 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 160 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112229 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35492003 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35492003 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35492003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35492003 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036820 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036820 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036820 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036820 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60927.246150 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60927.246150 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85635.179837 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85635.179837 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80577.769786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80577.769786 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5154697 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.807135 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.949822 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks -system.cpu.dcache.writebacks::total 168929 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205307 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205307 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895863 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101170 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62160 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62160 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205566 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205566 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2516687000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2516687000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14340164994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14340164994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16856851994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16856851994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16856851994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16856851994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 168935 # number of writebacks +system.cpu.dcache.writebacks::total 168935 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205357 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205357 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895917 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895917 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101274 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101274 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101274 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101274 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62134 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62134 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205551 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205551 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205551 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205551 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523454750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523454750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14076498244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14076498244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16599952994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16599952994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.242600 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.242600 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99996.966612 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99996.966612 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40613.106351 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40613.106351 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98150.834587 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98150.834587 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 9aa909b09..1084e1661 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026765 # Number of seconds simulated -sim_ticks 26765004500 # Number of ticks simulated -final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026816 # Number of seconds simulated +sim_ticks 26816405500 # Number of ticks simulated +final_tick 26816405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122306 # Simulator instruction rate (inst/s) -host_op_rate 173568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46166163 # Simulator tick rate (ticks/s) -host_mem_usage 255896 # Number of bytes of host memory used -host_seconds 579.75 # Real time elapsed on the host +host_inst_rate 109329 # Simulator instruction rate (inst/s) +host_op_rate 155152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41346943 # Simulator tick rate (ticks/s) +host_mem_usage 283460 # Number of bytes of host memory used +host_seconds 648.57 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7944704 # Number of bytes read from this memory -system.physmem.bytes_read::total 8242496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 297792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 297792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372160 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124136 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128789 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83940 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83940 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11126170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296831783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307957953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11126170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11126170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200715827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200715827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200715827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128790 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 83940 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 128790 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 83940 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 8242496 # Total number of bytes read from memory -system.physmem.bytesWritten 5372160 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8089 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7888 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7978 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8014 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5206 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5091 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26764988000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128790 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83940 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 76190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942848 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372096 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124107 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83939 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83939 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11128710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296193612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307322322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11128710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11128710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200328713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200328713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200328713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11128710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296193612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 507651035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128770 # Number of read requests accepted +system.physmem.writeReqs 83939 # Number of write requests accepted +system.physmem.readBursts 128770 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83939 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8241152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8241280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 318 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8144 # Per bank write bursts +system.physmem.perBankRdBursts::1 8386 # Per bank write bursts +system.physmem.perBankRdBursts::2 8247 # Per bank write bursts +system.physmem.perBankRdBursts::3 8164 # Per bank write bursts +system.physmem.perBankRdBursts::4 8296 # Per bank write bursts +system.physmem.perBankRdBursts::5 8451 # Per bank write bursts +system.physmem.perBankRdBursts::6 8094 # Per bank write bursts +system.physmem.perBankRdBursts::7 7961 # Per bank write bursts +system.physmem.perBankRdBursts::8 8061 # Per bank write bursts +system.physmem.perBankRdBursts::9 7610 # Per bank write bursts +system.physmem.perBankRdBursts::10 7787 # Per bank write bursts +system.physmem.perBankRdBursts::11 7813 # Per bank write bursts +system.physmem.perBankRdBursts::12 7882 # Per bank write bursts +system.physmem.perBankRdBursts::13 7886 # Per bank write bursts +system.physmem.perBankRdBursts::14 7979 # Per bank write bursts +system.physmem.perBankRdBursts::15 8007 # Per bank write bursts +system.physmem.perBankWrBursts::0 5180 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts +system.physmem.perBankWrBursts::2 5287 # Per bank write bursts +system.physmem.perBankWrBursts::3 5157 # Per bank write bursts +system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::5 5517 # Per bank write bursts +system.physmem.perBankWrBursts::6 5205 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5030 # Per bank write bursts +system.physmem.perBankWrBursts::9 5090 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5144 # Per bank write bursts +system.physmem.perBankWrBursts::12 5342 # Per bank write bursts +system.physmem.perBankWrBursts::13 5363 # Per bank write bursts +system.physmem.perBankWrBursts::14 5451 # Per bank write bursts +system.physmem.perBankWrBursts::15 5223 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 26816294000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 128770 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 83939 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 72833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,214 +127,221 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 389.285277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.799947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 855.459025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 13425 38.40% 38.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5427 15.52% 53.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3113 8.90% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2218 6.34% 69.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1684 4.82% 73.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1324 3.79% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1016 2.91% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 832 2.38% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 675 1.93% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 524 1.50% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 431 1.23% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 550 1.57% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 311 0.89% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 325 0.93% 91.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 173 0.49% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 178 0.51% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 117 0.33% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 209 0.60% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 130 0.37% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 238 0.68% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 111 0.32% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 314 0.90% 95.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 120 0.34% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 318 0.91% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 69 0.20% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 140 0.40% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 41 0.12% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 97 0.28% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 65 0.19% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 25 0.07% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 42 0.12% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 12 0.03% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 31 0.09% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.05% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 26 0.07% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 33 0.09% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 11 0.03% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 15 0.04% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 11 0.03% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 8 0.02% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 11 0.03% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 15 0.04% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 9 0.03% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 6 0.02% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 7 0.02% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 3 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 4 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 3 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 9 0.03% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 3 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 3 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 4 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 4 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 5 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 2 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 6 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 239 0.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34959 # Bytes accessed per row activation -system.physmem.totQLat 2852295000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4861110000 # Sum of mem lat for all requests -system.physmem.totBusLat 643935000 # Total cycles spent in databus access -system.physmem.totBankLat 1364880000 # Total cycles spent in bank access -system.physmem.avgQLat 22147.38 # Average queueing delay per request -system.physmem.avgBankLat 10597.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37745.35 # Average memory access latency -system.physmem.avgRdBW 307.96 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 200.72 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 307.96 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 200.72 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 37861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.431816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.292002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 695.442994 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15095 39.87% 39.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5646 14.91% 54.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3407 9.00% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2352 6.21% 69.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1734 4.58% 74.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1565 4.13% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1073 2.83% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 929 2.45% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 665 1.76% 85.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 565 1.49% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 384 1.01% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 558 1.47% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 286 0.76% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 361 0.95% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 176 0.46% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 218 0.58% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 133 0.35% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 117 0.31% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 270 0.71% 94.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 104 0.27% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 418 1.10% 95.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 100 0.26% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 243 0.64% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 38 0.10% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 144 0.38% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 38 0.10% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 86 0.23% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 54 0.14% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 16 0.04% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 43 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 22 0.06% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.04% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 32 0.08% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 11 0.03% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 29 0.08% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 17 0.04% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 31 0.08% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 15 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 11 0.03% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 11 0.03% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 9 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 8 0.02% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 21 0.06% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 10 0.03% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 21 0.06% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 6 0.02% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 10 0.03% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.02% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 17 0.04% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 5 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 7 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 6 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 6 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 13 0.03% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 11 0.03% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 8 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 10 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 6 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 7 0.02% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.02% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 4 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 6 0.02% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 3 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 36 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37861 # Bytes accessed per row activation +system.physmem.totQLat 3024623000 # Total ticks spent queuing +system.physmem.totMemAccLat 4968016750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643840000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1299553750 # Total ticks spent accessing banks +system.physmem.avgQLat 23488.93 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10092.21 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 38581.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.33 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.24 # Average write queue length over time -system.physmem.readRowHits 120249 # Number of row buffer hits during reads -system.physmem.writeRowHits 57506 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.51 # Row buffer hit rate for writes -system.physmem.avgGap 125816.71 # Average gap between requests -system.membus.throughput 508673780 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26538 # Transaction distribution -system.membus.trans_dist::ReadResp 26537 # Transaction distribution -system.membus.trans_dist::Writeback 83940 # Transaction distribution -system.membus.trans_dist::UpgradeReq 321 # Transaction distribution -system.membus.trans_dist::UpgradeResp 321 # Transaction distribution -system.membus.trans_dist::ReadExReq 102252 # Transaction distribution -system.membus.trans_dist::ReadExResp 102252 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342161 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13614656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13614656 # Total data (bytes) +system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.56 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.76 # Average write queue length when enqueuing +system.physmem.readRowHits 117866 # Number of row buffer hits during reads +system.physmem.writeRowHits 56971 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.87 # Row buffer hit rate for writes +system.physmem.avgGap 126070.33 # Average gap between requests +system.physmem.pageHitRate 82.20 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.88 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 507651035 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26514 # Transaction distribution +system.membus.trans_dist::ReadResp 26514 # Transaction distribution +system.membus.trans_dist::Writeback 83939 # Transaction distribution +system.membus.trans_dist::UpgradeReq 318 # Transaction distribution +system.membus.trans_dist::UpgradeResp 318 # Transaction distribution +system.membus.trans_dist::ReadExReq 102256 # Transaction distribution +system.membus.trans_dist::ReadExResp 102256 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342115 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342115 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613376 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13613376 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13613376 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934803500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1207011429 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203423433 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16635237 # Number of BP lookups -system.cpu.branchPred.condPredicted 12768503 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 604840 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10652885 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7773045 # Number of BTB hits +system.cpu.branchPred.lookups 16622919 # Number of BP lookups +system.cpu.branchPred.condPredicted 12749857 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 605504 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10570940 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7775711 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.966572 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1823659 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113448 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.557423 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1829148 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113993 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -376,136 +385,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53530010 # number of cpu cycles simulated +system.cpu.numCycles 53632812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12549473 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85279503 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16635237 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9596704 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21206249 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2379470 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10773225 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 477 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11686664 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 178212 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46277294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.580240 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12575227 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85200235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16622919 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9604859 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21200799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2368859 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10684050 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 493 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11692200 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 184239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46197272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332808 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25091643 54.22% 54.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2136768 4.62% 58.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1963962 4.24% 63.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042989 4.41% 67.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466847 3.17% 70.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1383026 2.99% 73.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 957932 2.07% 75.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1190240 2.57% 78.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10043887 21.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25016575 54.15% 54.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2138831 4.63% 58.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1968354 4.26% 63.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2045405 4.43% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466932 3.18% 70.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1376276 2.98% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 961294 2.08% 75.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190217 2.58% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10033388 21.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46277294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310765 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.593116 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14640784 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9115289 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19504792 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1371825 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1644604 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334519 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105037 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116943845 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363315 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1644604 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16350397 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2675070 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1001661 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19117578 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5487984 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115077475 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 183 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17134 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4627273 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476867094 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3452 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46197272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309939 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.588584 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14661485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9032065 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19500717 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1369785 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1633220 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334387 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105402 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116870755 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 365005 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1633220 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16370455 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2587455 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1031873 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19111398 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5462871 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114984523 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15960 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4602334 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 241 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115277175 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529754178 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476504412 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2548 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20253 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13031784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29643166 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22451729 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3891559 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4392801 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111618845 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35897 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107291250 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 275974 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10887740 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26073816 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2111 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46277294 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.318443 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990403 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16144503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20627 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12986013 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29603679 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22442541 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3905979 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4383979 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111534291 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36144 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107247539 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 279427 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10792871 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25872402 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2358 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46197272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.321512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.989577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11003161 23.78% 23.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8115395 17.54% 41.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7436608 16.07% 57.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7096880 15.34% 72.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5407297 11.68% 84.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3935038 8.50% 92.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1843993 3.98% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 867713 1.88% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571209 1.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10946962 23.70% 23.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8090791 17.51% 41.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7422192 16.07% 57.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7125519 15.42% 72.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5414632 11.72% 84.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3916527 8.48% 92.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842332 3.99% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 865884 1.87% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 572433 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46277294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46197272 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 113414 4.57% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1362149 54.91% 59.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1005332 40.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111334 4.52% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1349070 54.73% 59.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1004381 40.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56660345 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91595 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56643981 52.82% 52.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91446 0.09% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 269 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 176 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued @@ -531,84 +540,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28911335 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21627699 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28888115 26.94% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21623814 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107291250 # Type of FU issued -system.cpu.iq.rate 2.004320 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2480897 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023123 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263615967 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122570490 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105600159 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 698 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1174 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 216 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109771796 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 351 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2179165 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107247539 # Type of FU issued +system.cpu.iq.rate 1.999663 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2464786 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022982 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263436010 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122391385 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105557389 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 553 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 926 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109712054 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 271 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2336058 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6530 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30281 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1895991 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2296571 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6409 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29938 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1886803 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 805 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1644604 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1147402 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 47438 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111664541 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 286964 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29643166 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22451729 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19977 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6774 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4975 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30281 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393124 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181749 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 574873 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106260947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28610039 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030303 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1633220 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1092915 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45139 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111580294 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 294739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29603679 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22442541 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20224 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6335 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29938 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 394730 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181332 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 576062 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106214921 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28587238 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1032618 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9799 # number of nop insts executed -system.cpu.iew.exec_refs 49952901 # number of memory reference insts executed -system.cpu.iew.exec_branches 14605114 # Number of branches executed -system.cpu.iew.exec_stores 21342862 # Number of stores executed -system.cpu.iew.exec_rate 1.985072 # Inst execution rate -system.cpu.iew.wb_sent 105821179 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105600375 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53334269 # num instructions producing a value -system.cpu.iew.wb_consumers 103952809 # num instructions consuming a value +system.cpu.iew.exec_nop 9859 # number of nop insts executed +system.cpu.iew.exec_refs 49925863 # number of memory reference insts executed +system.cpu.iew.exec_branches 14600722 # Number of branches executed +system.cpu.iew.exec_stores 21338625 # Number of stores executed +system.cpu.iew.exec_rate 1.980409 # Inst execution rate +system.cpu.iew.wb_sent 105779922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105557547 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53302648 # num instructions producing a value +system.cpu.iew.wb_consumers 103946447 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.972732 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.513062 # average fanout of values written-back +system.cpu.iew.wb_rate 1.968152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512790 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11033009 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10948789 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 501673 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44632690 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.254680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.761954 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 502113 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44564052 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.258153 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763889 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15532654 34.80% 34.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11684135 26.18% 60.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462025 7.76% 68.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2877014 6.45% 75.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1854993 4.16% 79.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1951437 4.37% 83.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 690877 1.55% 85.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565658 1.27% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6013897 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15506218 34.80% 34.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11644493 26.13% 60.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3446423 7.73% 68.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2869378 6.44% 75.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1870309 4.20% 79.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1959985 4.40% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685768 1.54% 85.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 560638 1.26% 86.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6020840 13.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44632690 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44564052 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,226 +628,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6013897 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6020840 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150258931 # The number of ROB reads -system.cpu.rob.rob_writes 224984633 # The number of ROB writes -system.cpu.timesIdled 80350 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7252716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150099130 # The number of ROB reads +system.cpu.rob.rob_writes 224804524 # The number of ROB writes +system.cpu.timesIdled 76985 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7435540 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.754926 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.754926 # CPI: Total CPI of All Threads -system.cpu.ipc 1.324633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.324633 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511766096 # number of integer regfile reads -system.cpu.int_regfile_writes 103375635 # number of integer regfile writes -system.cpu.fp_regfile_reads 1160 # number of floating regfile reads -system.cpu.fp_regfile_writes 1012 # number of floating regfile writes -system.cpu.misc_regfile_reads 49188390 # number of misc regfile reads +system.cpu.cpi 0.756376 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.756376 # CPI: Total CPI of All Threads +system.cpu.ipc 1.322094 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.322094 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511539854 # number of integer regfile reads +system.cpu.int_regfile_writes 103334614 # number of integer regfile writes +system.cpu.fp_regfile_reads 734 # number of floating regfile reads +system.cpu.fp_regfile_writes 630 # number of floating regfile writes +system.cpu.misc_regfile_reads 49164319 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 771895107 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 86668 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 86666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129110 # Transaction distribution +system.cpu.toL2Bus.throughput 775188755 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 88572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 88572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129187 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61963 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454719 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 516682 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1966784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20627776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 107050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107050 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65806 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 520581 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2089088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18665280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20754368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20754368 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33408 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291762996 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47827231 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 50495227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260303004 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 28871 # number of replacements -system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 30799 # number of replacements +system.cpu.icache.tags.tagsinuse 1804.677341 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11655246 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 32836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 354.953283 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11651673 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11651673 # number of overall hits -system.cpu.icache.overall_hits::total 11651673 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34991 # number of overall misses -system.cpu.icache.overall_misses::total 34991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 840169228 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 840169228 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 840169228 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 840169228 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 840169228 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 840169228 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11686664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11686664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11686664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11686664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11686664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11686664 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002994 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002994 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002994 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002994 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002994 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002994 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24011.009345 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24011.009345 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24011.009345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24011.009345 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1080 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1804.677341 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881190 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881190 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11655255 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11655255 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11655255 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11655255 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11655255 # number of overall hits +system.cpu.icache.overall_hits::total 11655255 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 36945 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36945 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36945 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36945 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36945 # number of overall misses +system.cpu.icache.overall_misses::total 36945 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 836533724 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 836533724 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 836533724 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 836533724 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 836533724 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 836533724 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11692200 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11692200 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11692200 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11692200 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11692200 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11692200 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003160 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003160 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003160 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003160 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003160 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003160 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22642.677602 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22642.677602 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22642.677602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22642.677602 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 965 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.956522 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3759 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3759 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3759 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3759 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3759 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3759 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31232 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31232 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31232 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31232 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31232 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31232 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 684118269 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 684118269 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 684118269 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 684118269 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 684118269 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 684118269 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002672 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002672 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002672 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002672 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21904.401543 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21904.401543 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3781 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3781 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3781 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3781 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3781 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3781 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33164 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 33164 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 33164 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 33164 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 33164 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 33164 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 680570772 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 680570772 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 680570772 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 680570772 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 680570772 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 680570772 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002836 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002836 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002836 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20521.371728 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20521.371728 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95660 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 88398 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126774 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.697288 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95639 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29886.699201 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 90376 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126754 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.713003 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26705.369214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1845.081043 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.814983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041689 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.056307 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912979 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26062 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33492 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59554 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129110 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129110 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4780 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4780 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26062 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38272 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 64334 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26062 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38272 # number of overall hits -system.cpu.l2cache.overall_hits::total 64334 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4670 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21944 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26614 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 320 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 320 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102253 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102253 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4670 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124197 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128867 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4670 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124197 # number of overall misses -system.cpu.l2cache.overall_misses::total 128867 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 391521000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1869704500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2261225500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8377475499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8377475499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 391521000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10247179999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10638700999 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 391521000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10247179999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10638700999 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 30732 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 86168 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 129110 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 129110 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.occ_blocks::writebacks 26679.268686 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1365.813290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1841.617225 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.814187 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.056202 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.912070 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27962 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33496 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 61458 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 129187 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 129187 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 18 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 18 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4794 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4794 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27962 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 38290 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 66252 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27962 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 38290 # number of overall hits +system.cpu.l2cache.overall_hits::total 66252 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4680 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21912 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26592 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 318 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 318 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102256 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102256 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4680 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124168 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128848 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 124168 # number of overall misses +system.cpu.l2cache.overall_misses::total 128848 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 367025250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1881179499 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2248204749 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8506522000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8506522000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 367025250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10387701499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10754726749 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 367025250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10387701499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10754726749 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 32642 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 88050 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 129187 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 129187 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 336 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 336 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107033 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 30732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 162469 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 193201 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 30732 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 162469 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 193201 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.151959 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.308862 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.952381 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.952381 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955341 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955341 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.151959 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.764435 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.667010 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.151959 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.764435 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.667010 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83837.473233 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85203.449690 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84963.759675 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 71.871875 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 71.871875 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81928.896942 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81928.896942 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83837.473233 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82507.467966 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82555.665911 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83837.473233 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82507.467966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82555.665911 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107050 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107050 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 32642 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162458 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 195100 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 32642 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162458 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 195100 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.143374 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395466 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.302010 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.946429 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.946429 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955217 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955217 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143374 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.764308 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.660420 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143374 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.764308 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.660420 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78424.198718 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85851.565307 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84544.402414 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.896226 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.896226 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83188.487717 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83188.487717 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78424.198718 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83658.442586 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83468.325073 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78424.198718 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83658.442586 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83468.325073 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -847,195 +856,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83940 # number of writebacks -system.cpu.l2cache.writebacks::total 83940 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83939 # number of writebacks +system.cpu.l2cache.writebacks::total 83939 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4653 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21885 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26538 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 320 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 320 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102253 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102253 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4653 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124138 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128791 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4653 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124138 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128791 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 331760500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1590135750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1921896250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3200320 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3200320 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7097849501 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7097849501 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 331760500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8687985251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9019745751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 331760500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8687985251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9019745751 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394780 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307980 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.952381 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.952381 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955341 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955341 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764072 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.666617 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764072 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.666617 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71300.343864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72658.704592 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72420.538473 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69414.584423 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69414.584423 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 78 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4663 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21851 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26514 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 318 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 318 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124107 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4663 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124107 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128770 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307037750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1604664499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1911702249 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3189317 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3189317 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7230852500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7230852500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307037750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8835516999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9142554749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307037750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8835516999 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9142554749 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394365 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.301124 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.946429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.946429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955217 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955217 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.660021 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.660021 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65845.539352 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73436.661892 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72101.616090 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.298742 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.298742 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70713.234431 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70713.234431 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158372 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266800 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15987 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15987 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 158362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.865935 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44347537 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 272.978474 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.865935 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993375 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993375 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26048299 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26048299 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266707 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44341813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44341813 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44341813 # number of overall hits -system.cpu.dcache.overall_hits::total 44341813 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125377 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125377 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583101 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583101 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708478 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708478 # number of overall misses -system.cpu.dcache.overall_misses::total 1708478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5199394222 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5199394222 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 124981048011 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 124981048011 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 861250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 861250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 130180442233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 130180442233 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 130180442233 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 130180442233 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26200390 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26200390 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44315006 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44315006 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44315006 # number of overall hits +system.cpu.dcache.overall_hits::total 44315006 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125034 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125034 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583194 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583194 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708228 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708228 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708228 # number of overall misses +system.cpu.dcache.overall_misses::total 1708228 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5241649212 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5241649212 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126812367989 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126812367989 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 914750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 914750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 132054017201 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 132054017201 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132054017201 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132054017201 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26173333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26173333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46050291 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46050291 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46050291 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46050291 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004785 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004785 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079754 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002620 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002620 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037100 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037100 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037100 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037100 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41470.080015 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41470.080015 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78946.983175 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 78946.983175 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20505.952381 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20505.952381 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76196.733135 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76196.733135 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1249 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 129 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.581395 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 78.062500 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46023234 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46023234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46023234 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46023234 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004777 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004777 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079758 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079758 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037117 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037117 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037117 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037117 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41921.790969 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41921.790969 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80099.070606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80099.070606 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22310.975610 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22310.975610 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77304.679001 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77304.679001 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4730 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.028777 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 87.428571 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129110 # number of writebacks -system.cpu.dcache.writebacks::total 129110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69907 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69907 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475766 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475766 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545673 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545673 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545673 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545673 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55470 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55470 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107335 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162805 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162805 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162805 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162805 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2262652309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2262652309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8543267922 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8543267922 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10805920231 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10805920231 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10805920231 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10805920231 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40790.559023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40790.559023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79594.427931 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79594.427931 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129187 # number of writebacks +system.cpu.dcache.writebacks::total 129187 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69592 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69592 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475842 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475842 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545434 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545434 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545434 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545434 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55442 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55442 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107352 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107352 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162794 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162794 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162794 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162794 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2274282063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2274282063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8672803924 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8672803924 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947085987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10947085987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947085987 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10947085987 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003537 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003537 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41020.923902 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41020.923902 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80788.470862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80788.470862 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index b5eeb298e..e22bfa1d8 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,102 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.017017 # Number of seconds simulated -sim_ticks 1017016979500 # Number of ticks simulated -final_tick 1017016979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.009838 # Number of seconds simulated +sim_ticks 1009838214500 # Number of ticks simulated +final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89946 # Simulator instruction rate (inst/s) -host_op_rate 89946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50268200 # Simulator tick rate (ticks/s) -host_mem_usage 224748 # Number of bytes of host memory used -host_seconds 20231.82 # Real time elapsed on the host +host_inst_rate 108402 # Simulator instruction rate (inst/s) +host_op_rate 108402 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60154913 # Simulator tick rate (ticks/s) +host_mem_usage 256492 # Number of bytes of host memory used +host_seconds 16787.29 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125365248 # Number of bytes read from this memory -system.physmem.bytes_read::total 125420224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory -system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958832 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959691 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 123267606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 123321662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54056 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54056 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 64065511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 64065511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 64065511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 123267606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 187387172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959691 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 1018058 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 1959691 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 1018058 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 125420224 # Total number of bytes read from memory -system.physmem.bytesWritten 65155712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125420224 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 117699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 126961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 128618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123183 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61224 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 61467 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 60558 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 61216 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 61647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63085 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 65334 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65770 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65297 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 65611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64203 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 64552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1017016906500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959691 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1018058 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1654293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 74498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24401 # What read queue length does an incoming req see +system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 124143704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 124198144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64520751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64520751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64520751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 124143704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 188718895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959688 # Number of read requests accepted +system.physmem.writeReqs 1018055 # Number of write requests accepted +system.physmem.readBursts 1959688 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018055 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125384704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35328 # Total number of bytes read from write queue +system.physmem.bytesWritten 65154176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125420032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65155520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 552 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 118719 # Per bank write bursts +system.physmem.perBankRdBursts::1 114075 # Per bank write bursts +system.physmem.perBankRdBursts::2 116210 # Per bank write bursts +system.physmem.perBankRdBursts::3 117697 # Per bank write bursts +system.physmem.perBankRdBursts::4 117769 # Per bank write bursts +system.physmem.perBankRdBursts::5 117504 # Per bank write bursts +system.physmem.perBankRdBursts::6 119870 # Per bank write bursts +system.physmem.perBankRdBursts::7 124481 # Per bank write bursts +system.physmem.perBankRdBursts::8 126964 # Per bank write bursts +system.physmem.perBankRdBursts::9 130062 # Per bank write bursts +system.physmem.perBankRdBursts::10 128627 # Per bank write bursts +system.physmem.perBankRdBursts::11 130265 # Per bank write bursts +system.physmem.perBankRdBursts::12 125943 # Per bank write bursts +system.physmem.perBankRdBursts::13 125205 # Per bank write bursts +system.physmem.perBankRdBursts::14 122569 # Per bank write bursts +system.physmem.perBankRdBursts::15 123176 # Per bank write bursts +system.physmem.perBankWrBursts::0 61223 # Per bank write bursts +system.physmem.perBankWrBursts::1 61467 # Per bank write bursts +system.physmem.perBankWrBursts::2 60558 # Per bank write bursts +system.physmem.perBankWrBursts::3 61216 # Per bank write bursts +system.physmem.perBankWrBursts::4 61647 # Per bank write bursts +system.physmem.perBankWrBursts::5 63084 # Per bank write bursts +system.physmem.perBankWrBursts::6 64137 # Per bank write bursts +system.physmem.perBankWrBursts::7 65614 # Per bank write bursts +system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::9 65770 # Per bank write bursts +system.physmem.perBankWrBursts::10 65297 # Per bank write bursts +system.physmem.perBankWrBursts::11 65611 # Per bank write bursts +system.physmem.perBankWrBursts::12 64149 # Per bank write bursts +system.physmem.perBankWrBursts::13 64192 # Per bank write bursts +system.physmem.perBankWrBursts::14 64551 # Per bank write bursts +system.physmem.perBankWrBursts::15 64186 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1009838141500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1959688 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1018055 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1662262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21383 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -125,237 +127,233 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 45681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 46199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 48930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1724249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.484089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.062986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.322838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1380983 80.09% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 190835 11.07% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 56645 3.29% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 27563 1.60% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15745 0.91% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6630 0.38% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6555 0.38% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3694 0.21% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 2928 0.17% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2668 0.15% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2688 0.16% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1402 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1069 0.06% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1034 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 922 0.05% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 818 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 762 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 627 0.04% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3636 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 543 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 234 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 178 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 89 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 86 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 92 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 58 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 44 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 22 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 24 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 13 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 19 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 18 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 23 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 24 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 19 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 13 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 19 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 19 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 20 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 13 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 14 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 14 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 18 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 115 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 10 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1724249 # Bytes accessed per row activation -system.physmem.totQLat 33963917000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 98664809500 # Sum of mem lat for all requests -system.physmem.totBusLat 9795575000 # Total cycles spent in databus access -system.physmem.totBankLat 54905317500 # Total cycles spent in bank access -system.physmem.avgQLat 17336.36 # Average queueing delay per request -system.physmem.avgBankLat 28025.57 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50361.93 # Average memory access latency -system.physmem.avgRdBW 123.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 64.07 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 123.32 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 64.07 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.46 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.10 # Average read queue length over time -system.physmem.avgWrQLen 10.57 # Average write queue length over time -system.physmem.readRowHits 900981 # Number of row buffer hits during reads -system.physmem.writeRowHits 351934 # Number of row buffer hits during writes -system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes -system.physmem.avgGap 341538.83 # Average gap between requests -system.membus.throughput 187387172 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1178393 # Transaction distribution -system.membus.trans_dist::ReadResp 1178393 # Transaction distribution -system.membus.trans_dist::Writeback 1018058 # Transaction distribution -system.membus.trans_dist::ReadExReq 781298 # Transaction distribution -system.membus.trans_dist::ReadExResp 781298 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4937440 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190575936 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190575936 # Total data (bytes) +system.physmem.bytesPerActivate::samples 1862401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 102.289945 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.389421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 186.671108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1500565 80.57% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 201454 10.82% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 59784 3.21% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29274 1.57% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16603 0.89% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10401 0.56% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7224 0.39% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6892 0.37% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4048 0.22% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3343 0.18% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3041 0.16% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2820 0.15% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1620 0.09% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1539 0.08% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1515 0.08% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1490 0.08% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1330 0.07% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1308 0.07% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 968 0.05% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1341 0.07% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 595 0.03% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2192 0.12% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 189 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 700 0.04% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 112 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 81 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 79 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 79 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 66 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 55 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 71 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 36 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 40 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 43 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 52 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 33 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 35 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 28 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 29 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 30 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 34 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 33 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 22 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 20 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 16 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 21 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 15 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 14 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 18 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 13 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 16 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 25 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 21 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 12 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 14 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 106 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 8 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 15 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 5 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 14 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 9 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 64 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 154 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1862401 # Bytes accessed per row activation +system.physmem.totQLat 23049370500 # Total ticks spent queuing +system.physmem.totMemAccLat 84969994250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9795680000 # Total ticks spent in databus transfers +system.physmem.totBankLat 52124943750 # Total ticks spent accessing banks +system.physmem.avgQLat 11765.07 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26606.09 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 43371.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 124.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 64.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 124.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 64.52 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.47 # Data bus utilization in percentage +system.physmem.busUtilRead 0.97 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.50 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.29 # Average write queue length when enqueuing +system.physmem.readRowHits 771404 # Number of row buffer hits during reads +system.physmem.writeRowHits 343365 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.73 # Row buffer hit rate for writes +system.physmem.avgGap 339128.71 # Average gap between requests +system.physmem.pageHitRate 37.44 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.16 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 188718895 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178392 # Transaction distribution +system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.membus.trans_dist::Writeback 1018055 # Transaction distribution +system.membus.trans_dist::ReadExReq 781296 # Transaction distribution +system.membus.trans_dist::ReadExResp 781296 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937431 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4937431 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11803876500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11787413500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18471159750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18365913000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.branchPred.lookups 326564713 # Number of BP lookups -system.cpu.branchPred.condPredicted 252601424 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138218301 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 218593713 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135545625 # Number of BTB hits +system.cpu.branchPred.lookups 326538195 # Number of BP lookups +system.cpu.branchPred.condPredicted 252572806 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220428693 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135446272 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.008016 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.446752 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444840309 # DTB read hits +system.cpu.dtb.read_hits 444831815 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449737387 # DTB read accesses -system.cpu.dtb.write_hits 160847153 # DTB write hits +system.cpu.dtb.read_accesses 449728893 # DTB read accesses +system.cpu.dtb.write_hits 160846718 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162548457 # DTB write accesses -system.cpu.dtb.data_hits 605687462 # DTB hits +system.cpu.dtb.write_accesses 162548022 # DTB write accesses +system.cpu.dtb.data_hits 605678533 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612285844 # DTB accesses -system.cpu.itb.fetch_hits 231947501 # ITB hits +system.cpu.dtb.data_accesses 612276915 # DTB accesses +system.cpu.itb.fetch_hits 231928866 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231947523 # ITB accesses +system.cpu.itb.fetch_accesses 231928888 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,34 +367,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2034033960 # number of cpu cycles simulated +system.cpu.numCycles 2019676430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172359749 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154204964 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667587623 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172263192 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154275003 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667627607 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043790240 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043830224 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651716905 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884714 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120522396 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11097447 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131619843 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83580106 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.161652 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139337588 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651720859 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884928 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120516333 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11119574 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131635907 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83564055 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.169113 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139356886 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742086287 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742059065 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7521644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 462344107 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571689853 # Number of cycles cpu stages are processed. -system.cpu.activity 77.269597 # Percentage of cycles cpu is active +system.cpu.timesIdled 7515569 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 447943127 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571733303 # Number of cycles cpu stages are processed. +system.cpu.activity 77.821045 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -408,72 +406,72 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.117736 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.109846 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.117736 # CPI: Total CPI of All Threads -system.cpu.ipc 0.894666 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.109846 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901026 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.894666 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 847369948 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186664012 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.340423 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1100283558 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933750402 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.906333 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1061657822 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972376138 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 47.805305 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1624406509 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409627451 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.138673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 1012697898 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021336062 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.212341 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.901026 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 833031471 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186644959 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.754211 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1085876245 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933800185 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.235138 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1047285366 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972391064 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.145884 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1610051905 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409624525 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.281691 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 998329603 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021346827 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.569825 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 668.751330 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 231946364 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 668.332859 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 231927727 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 270019.050058 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 269997.353900 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 668.751330 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.326539 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.326539 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231946364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231946364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231946364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231946364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231946364 # number of overall hits -system.cpu.icache.overall_hits::total 231946364 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses -system.cpu.icache.overall_misses::total 1137 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82490250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82490250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82490250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82490250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82490250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82490250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231947501 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231947501 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231947501 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231947501 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231947501 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231947501 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231927727 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231927727 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231927727 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231927727 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231927727 # number of overall hits +system.cpu.icache.overall_hits::total 231927727 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses +system.cpu.icache.overall_misses::total 1139 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82717000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82717000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82717000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82717000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82717000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82717000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231928866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231928866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231928866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231928866 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231928866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231928866 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72550.791557 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72550.791557 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72550.791557 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72550.791557 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72550.791557 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.475856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72622.475856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72622.475856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72622.475856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -482,137 +480,137 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 162 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 278 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 278 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 278 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 278 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 278 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65194000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65136750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65136750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65136750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75895.227008 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75895.227008 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75895.227008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75895.227008 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75828.579744 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75828.579744 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 805844654 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7222689 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7222689 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3693279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889621 # Transaction distribution +system.cpu.toL2Bus.throughput 811573074 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7222683 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7222683 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889623 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916181 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21917899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916174 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21917892 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819557696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819557696 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 819557504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819557504 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10096073500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10096073000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1466500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1445250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14100129000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13991720500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 1926960 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30930.857959 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8958684 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1956753 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.578342 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 67691760750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.347502 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455442 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001048 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.487444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943935 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6044296 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044296 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693279 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693279 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108323 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108323 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7152619 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7152619 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7152619 # number of overall hits -system.cpu.l2cache.overall_hits::total 7152619 # number of overall hits +system.cpu.l2cache.tags.replacements 1926957 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30919.698652 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8958682 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578348 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 67892812750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14931.952178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.659960 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086514 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943594 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044291 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044291 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693280 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108327 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108327 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152618 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152618 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7152618 # number of overall hits +system.cpu.l2cache.overall_hits::total 7152618 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1177534 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1178393 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 781298 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 781298 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1177533 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1178392 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1958832 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1959691 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958829 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1959688 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1958832 # number of overall misses -system.cpu.l2cache.overall_misses::total 1959691 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64331000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104087297000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 104151628000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79166748750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 79166748750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 64331000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 183254045750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 183318376750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 64331000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 183254045750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 183318376750 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98167461500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98231735250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71142206750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 71142206750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 64273750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 169309668250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 169373942000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 64273750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 169309668250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 169373942000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221830 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222689 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3693279 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3693279 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889621 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889621 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221824 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222683 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693280 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693280 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889623 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889623 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111451 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112310 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111447 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112306 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111451 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112310 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111447 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413468 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413468 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413467 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413467 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214986 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.215060 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74890.570431 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88394.302840 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88384.459174 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101327.212856 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101327.212856 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93544.531638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74890.570431 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93552.711897 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93544.531638 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.923166 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83367.057654 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.830055 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91056.663224 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91056.663224 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86429.034622 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86429.034622 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -621,86 +619,86 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1018058 # number of writebacks -system.cpu.l2cache.writebacks::total 1018058 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks +system.cpu.l2cache.writebacks::total 1018055 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781298 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 781298 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177533 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178392 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958832 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1959691 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958829 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959688 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958832 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1959691 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53514000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89157154500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89210668500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69321257750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69321257750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53514000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158478412250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158531926250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53514000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158478412250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158531926250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53492750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83392423000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445915750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355655750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355655750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53492750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144748078750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 144801571500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53492750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144748078750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 144801571500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413468 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413468 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62298.020955 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75715.142408 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75705.361878 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88725.758609 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88725.758609 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62273.282887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70819.605905 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70813.375982 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.615477 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.615477 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9107355 # number of replacements -system.cpu.dcache.tags.tagsinuse 4082.476561 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 593297569 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111451 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.115597 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 12681367250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4082.476561 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996698 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268765 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268765 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156028804 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156028804 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593297569 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593297569 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593297569 # number of overall hits -system.cpu.dcache.overall_hits::total 593297569 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326898 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326898 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4699698 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4699698 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12026596 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12026596 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12026596 # number of overall misses -system.cpu.dcache.overall_misses::total 12026596 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 189082879500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 189082879500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 263051310000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 263051310000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 452134189500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 452134189500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 452134189500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 452134189500 # number of overall miss cycles +system.cpu.dcache.tags.replacements 9107351 # number of replacements +system.cpu.dcache.tags.tagsinuse 4082.357931 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 593283203 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111447 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.114049 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 12709353000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4082.357931 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156014426 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156014426 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593283203 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593283203 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593283203 # number of overall hits +system.cpu.dcache.overall_hits::total 593283203 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326886 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326886 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4714076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4714076 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12040962 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12040962 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12040962 # number of overall misses +system.cpu.dcache.overall_misses::total 12040962 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066802000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183066802000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 258282974250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 258282974250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 441349776250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 441349776250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 441349776250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 441349776250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -711,54 +709,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029240 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029240 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019868 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019868 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019868 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019868 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25806.675554 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25806.675554 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55971.960326 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55971.960326 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37594.527121 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37594.527121 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37594.527121 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15699726 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7389800 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 434712 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 73152 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.115235 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 101.019794 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029329 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029329 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019892 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019892 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019892 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019892 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.621723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.621723 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54789.734881 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54789.734881 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36654.029491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36654.029491 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12098438 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7855784 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 422645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73423 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625532 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 106.993503 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693279 # number of writebacks -system.cpu.dcache.writebacks::total 3693279 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2810519 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2810519 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2915145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2915145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2915145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2915145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889179 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889179 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111451 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111451 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111451 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111451 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171880361750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171880361750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92301345750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92301345750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264181707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 264181707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264181707500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 264181707500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks +system.cpu.dcache.writebacks::total 3693280 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104620 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104620 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824895 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2824895 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2929515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2929515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2929515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2929515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222266 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222266 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889181 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889181 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111447 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111447 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111447 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111447 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165960748500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 165960748500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84277565500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84277565500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250238314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 250238314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250238314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 250238314000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -767,14 +765,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23798.655292 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23798.655292 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48857.914337 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48857.914337 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28994.471627 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28994.471627 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22979.041273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22979.041273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.635773 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.635773 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d01882912..fbdbcc030 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,105 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.694171 # Number of seconds simulated -sim_ticks 694171131000 # Number of ticks simulated -final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.685488 # Number of seconds simulated +sim_ticks 685488076000 # Number of ticks simulated +final_tick 685488076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145628 # Simulator instruction rate (inst/s) -host_op_rate 145628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58230614 # Simulator tick rate (ticks/s) -host_mem_usage 230068 # Number of bytes of host memory used -host_seconds 11921.07 # Real time elapsed on the host +host_inst_rate 134484 # Simulator instruction rate (inst/s) +host_op_rate 134484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53101916 # Simulator tick rate (ticks/s) +host_mem_usage 257516 # Number of bytes of host memory used +host_seconds 12908.91 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125790400 # Number of bytes read from this memory -system.physmem.bytes_read::total 125852032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65261440 # Number of bytes written to this memory -system.physmem.bytes_written::total 65261440 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965475 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019710 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019710 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 181209495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 181298280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88785 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88785 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94013475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94013475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94013475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 181209495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 275311755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966438 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 1019710 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 1966438 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 1019710 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 125852032 # Total number of bytes read from memory -system.physmem.bytesWritten 65261440 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125852032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65261440 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 561 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 119011 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 114417 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 116554 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 118021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 118126 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 117795 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 124937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 127536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 130495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 129073 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 126583 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 125666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123677 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 61282 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 61566 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 60662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 61309 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 61746 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 64226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 65470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65888 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65399 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 65733 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64314 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 64641 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64291 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 694171008500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966438 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019710 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1645970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 229492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125793664 # Number of bytes read from this memory +system.physmem.bytes_read::total 125855616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265536 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265536 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966494 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019774 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019774 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 183509631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 183600008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95210316 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95210316 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95210316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 183509631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 278810323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966494 # Number of read requests accepted +system.physmem.writeReqs 1019774 # Number of write requests accepted +system.physmem.readBursts 1966494 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019774 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125820608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35008 # Total number of bytes read from write queue +system.physmem.bytesWritten 65264256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125855616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65265536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 547 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 119024 # Per bank write bursts +system.physmem.perBankRdBursts::1 114431 # Per bank write bursts +system.physmem.perBankRdBursts::2 116551 # Per bank write bursts +system.physmem.perBankRdBursts::3 118044 # Per bank write bursts +system.physmem.perBankRdBursts::4 118169 # Per bank write bursts +system.physmem.perBankRdBursts::5 117821 # Per bank write bursts +system.physmem.perBankRdBursts::6 120193 # Per bank write bursts +system.physmem.perBankRdBursts::7 124929 # Per bank write bursts +system.physmem.perBankRdBursts::8 127563 # Per bank write bursts +system.physmem.perBankRdBursts::9 130460 # Per bank write bursts +system.physmem.perBankRdBursts::10 129120 # Per bank write bursts +system.physmem.perBankRdBursts::11 130791 # Per bank write bursts +system.physmem.perBankRdBursts::12 126621 # Per bank write bursts +system.physmem.perBankRdBursts::13 125625 # Per bank write bursts +system.physmem.perBankRdBursts::14 122955 # Per bank write bursts +system.physmem.perBankRdBursts::15 123650 # Per bank write bursts +system.physmem.perBankWrBursts::0 61294 # Per bank write bursts +system.physmem.perBankWrBursts::1 61576 # Per bank write bursts +system.physmem.perBankWrBursts::2 60653 # Per bank write bursts +system.physmem.perBankWrBursts::3 61320 # Per bank write bursts +system.physmem.perBankWrBursts::4 61767 # Per bank write bursts +system.physmem.perBankWrBursts::5 63184 # Per bank write bursts +system.physmem.perBankWrBursts::6 64210 # Per bank write bursts +system.physmem.perBankWrBursts::7 65704 # Per bank write bursts +system.physmem.perBankWrBursts::8 65475 # Per bank write bursts +system.physmem.perBankWrBursts::9 65876 # Per bank write bursts +system.physmem.perBankWrBursts::10 65422 # Per bank write bursts +system.physmem.perBankWrBursts::11 65733 # Per bank write bursts +system.physmem.perBankWrBursts::12 64307 # Per bank write bursts +system.physmem.perBankWrBursts::13 64297 # Per bank write bursts +system.physmem.perBankWrBursts::14 64633 # Per bank write bursts +system.physmem.perBankWrBursts::15 64303 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 685487953500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1966494 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1019774 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1645141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 231582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -125,237 +127,235 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1724767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 110.763752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.212194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.511378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1378543 79.93% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 191920 11.13% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 57620 3.34% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 28373 1.65% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15698 0.91% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 9692 0.56% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6693 0.39% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6792 0.39% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3776 0.22% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 2960 0.17% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2630 0.15% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2677 0.16% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1390 0.08% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1126 0.07% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1092 0.06% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 878 0.05% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 859 0.05% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 813 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 757 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 627 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 709 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 705 0.04% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3570 0.21% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 579 0.03% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 253 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 194 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 146 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 142 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 94 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 85 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 102 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 71 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 61 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 59 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 49 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 59 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 39 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 46 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 39 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 28 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 48 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 43 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 24 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 32 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 25 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 21 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 25 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 26 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 19 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 25 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 21 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 14 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 28 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 7 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 9 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 14 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 12 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 10 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 21 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 8 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 19 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 11 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 123 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 12 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 18 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 15 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1429 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1724767 # Bytes accessed per row activation -system.physmem.totQLat 33917679750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 98022206000 # Sum of mem lat for all requests -system.physmem.totBusLat 9829385000 # Total cycles spent in databus access -system.physmem.totBankLat 54275141250 # Total cycles spent in bank access -system.physmem.avgQLat 17253.21 # Average queueing delay per request -system.physmem.avgBankLat 27608.62 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 49861.82 # Average memory access latency -system.physmem.avgRdBW 181.30 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 94.01 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 181.30 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 94.01 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 10.67 # Average write queue length over time -system.physmem.readRowHits 908058 # Number of row buffer hits during reads -system.physmem.writeRowHits 352757 # Number of row buffer hits during writes -system.physmem.readRowHitRate 46.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.59 # Row buffer hit rate for writes -system.physmem.avgGap 232463.70 # Average gap between requests -system.membus.throughput 275311755 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191259 # Transaction distribution -system.membus.trans_dist::ReadResp 1191259 # Transaction distribution -system.membus.trans_dist::Writeback 1019710 # Transaction distribution -system.membus.trans_dist::ReadExReq 775179 # Transaction distribution -system.membus.trans_dist::ReadExResp 775179 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952586 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191113472 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191113472 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191113472 # Total data (bytes) +system.physmem.wrQLenPdf::0 45485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 45674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 46118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 49534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 48711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1822247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.837037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.099826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.854977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1460763 80.16% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 186024 10.21% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 72307 3.97% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32393 1.78% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16822 0.92% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10551 0.58% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6953 0.38% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6800 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3880 0.21% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3184 0.17% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2717 0.15% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2015 0.11% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1651 0.09% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1492 0.08% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1271 0.07% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1102 0.06% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 982 0.05% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1041 0.06% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 864 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 817 0.04% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 719 0.04% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2906 0.16% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 391 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 753 0.04% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 249 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 220 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 185 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 207 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 171 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 149 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 132 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 171 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 381 0.02% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 117 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 95 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 87 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 78 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 78 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 61 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 72 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 41 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 45 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 35 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 29 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 23 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 45 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 24 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 26 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 27 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 27 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 22 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 20 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 15 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 17 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 14 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 14 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 21 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 10 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 11 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 23 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 10 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 13 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 21 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 13 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 16 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 16 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 12 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 85 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 29 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 125 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1822247 # Bytes accessed per row activation +system.physmem.totQLat 24360796250 # Total ticks spent queuing +system.physmem.totMemAccLat 84735751250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9829735000 # Total ticks spent in databus transfers +system.physmem.totBankLat 50545220000 # Total ticks spent accessing banks +system.physmem.avgQLat 12391.38 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 25710.37 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 43101.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 183.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.21 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 183.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.21 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.18 # Data bus utilization in percentage +system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.12 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.63 # Average write queue length when enqueuing +system.physmem.readRowHits 818889 # Number of row buffer hits during reads +system.physmem.writeRowHits 344565 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.79 # Row buffer hit rate for writes +system.physmem.avgGap 229546.70 # Average gap between requests +system.physmem.pageHitRate 38.97 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 7.09 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 278810323 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191305 # Transaction distribution +system.membus.trans_dist::ReadResp 1191305 # Transaction distribution +system.membus.trans_dist::Writeback 1019774 # Transaction distribution +system.membus.trans_dist::ReadExReq 775189 # Transaction distribution +system.membus.trans_dist::ReadExResp 775189 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952762 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191121152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191121152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191121152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11881655250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11874044250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18594236500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18494220250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.branchPred.lookups 381853679 # Number of BP lookups -system.cpu.branchPred.condPredicted 296812462 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16082560 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 263010897 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259938392 # Number of BTB hits +system.cpu.branchPred.lookups 381678235 # Number of BP lookups +system.cpu.branchPred.condPredicted 296637110 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16088915 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262749250 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259783318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.831796 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24703686 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3043 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.871193 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24705471 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613967200 # DTB read hits -system.cpu.dtb.read_misses 11252585 # DTB read misses +system.cpu.dtb.read_hits 613987676 # DTB read hits +system.cpu.dtb.read_misses 11260420 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625219785 # DTB read accesses -system.cpu.dtb.write_hits 212300531 # DTB write hits -system.cpu.dtb.write_misses 7117395 # DTB write misses +system.cpu.dtb.read_accesses 625248096 # DTB read accesses +system.cpu.dtb.write_hits 212348403 # DTB write hits +system.cpu.dtb.write_misses 7134109 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219417926 # DTB write accesses -system.cpu.dtb.data_hits 826267731 # DTB hits -system.cpu.dtb.data_misses 18369980 # DTB misses +system.cpu.dtb.write_accesses 219482512 # DTB write accesses +system.cpu.dtb.data_hits 826336079 # DTB hits +system.cpu.dtb.data_misses 18394529 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844637711 # DTB accesses -system.cpu.itb.fetch_hits 391085180 # ITB hits -system.cpu.itb.fetch_misses 51 # ITB misses +system.cpu.dtb.data_accesses 844730608 # DTB accesses +system.cpu.itb.fetch_hits 391118478 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391085231 # ITB accesses +system.cpu.itb.fetch_accesses 391118522 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,238 +369,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1388342263 # number of cpu cycles simulated +system.cpu.numCycles 1370976153 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402551684 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3162454030 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381853679 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284642078 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574754052 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140783496 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 197047269 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1488 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391085180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8065065 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1291251504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.449139 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402585457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3161328538 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381678235 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284488789 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574592396 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140681937 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 190961804 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1466 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391118478 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8069239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1284965558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.460244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.144346 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 716497452 55.49% 55.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42682670 3.31% 58.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21784053 1.69% 60.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39696423 3.07% 63.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129425846 10.02% 73.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61545626 4.77% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38574460 2.99% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28124081 2.18% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212920893 16.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 710373162 55.28% 55.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42677954 3.32% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21796461 1.70% 60.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39706509 3.09% 63.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129357441 10.07% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61547596 4.79% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38577258 3.00% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28126573 2.19% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212802604 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1291251504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275043 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.277863 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434540420 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 178303124 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542717448 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18794331 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116896181 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58354479 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 840 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3089587827 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116896181 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457532531 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 123212849 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5836 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535730171 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57873936 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3007379456 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610253 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1826446 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51579864 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2248363732 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3900421320 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3900278198 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 143121 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1284965558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.278399 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.305896 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434593706 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 172173126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542518914 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18856302 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116823510 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58351123 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 876 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3088655283 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2048 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116823510 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457554918 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116845929 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6766 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535622730 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58111705 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3006575354 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 610156 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1852925 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51779132 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247748999 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3899198212 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3899055356 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 142855 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 872160769 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 168 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 168 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123444205 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679751883 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255539846 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68026727 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37555626 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2725485841 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509620077 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3191439 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 980254556 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 417071077 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1291251504 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.943556 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971187 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 871546036 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 162 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 160 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123661161 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679705832 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255482967 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67737746 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37011786 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724988246 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509612209 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3204133 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979747229 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416253397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1284965558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953058 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971218 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 449456095 34.81% 34.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203314241 15.75% 50.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185688017 14.38% 64.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153487226 11.89% 76.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133078124 10.31% 87.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80722513 6.25% 93.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65115490 5.04% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15268261 1.18% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5121537 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 442955350 34.47% 34.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203613373 15.85% 50.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185757734 14.46% 64.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153374382 11.94% 76.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133013671 10.35% 87.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80752885 6.28% 93.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65067569 5.06% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15309053 1.19% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5121541 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1291251504 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1284965558 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2192750 11.84% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11923038 64.36% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4410634 23.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2189478 11.81% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11923612 64.31% 76.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4426862 23.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643953882 65.51% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 266 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 35 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641631628 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224033966 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643894908 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 110 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 256 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641620248 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224096461 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509620077 # Type of FU issued -system.cpu.iq.rate 1.807638 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18526422 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6330307505 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3704630064 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413135648 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1902014 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1217951 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 852306 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527206104 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 940395 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62612888 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509612209 # Type of FU issued +system.cpu.iq.rate 1.830529 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18539952 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007388 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6324036158 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3703625637 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413191204 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1897903 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1215976 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850771 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527214134 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938027 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62593572 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235156220 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263801 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 109236 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94811344 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235110169 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263246 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107760 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94754465 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 161 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1579414 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 95 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1543010 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116896181 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 59627165 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1293281 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867673451 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8945086 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679751883 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255539846 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 123 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 277586 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17880 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 109236 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10358298 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8554506 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18912804 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462213177 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625220360 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47406900 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116823510 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 56431673 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1297935 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867161807 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8942583 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679705832 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255482967 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282108 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18553 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107760 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10367292 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8554999 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18922291 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462270338 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625248683 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47341871 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142187487 # number of nop insts executed -system.cpu.iew.exec_refs 844638305 # number of memory reference insts executed -system.cpu.iew.exec_branches 300894564 # Number of branches executed -system.cpu.iew.exec_stores 219417945 # Number of stores executed -system.cpu.iew.exec_rate 1.773491 # Inst execution rate -system.cpu.iew.wb_sent 2441919357 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413987954 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388436926 # num instructions producing a value -system.cpu.iew.wb_consumers 1764428707 # num instructions consuming a value +system.cpu.iew.exec_nop 142173439 # number of nop insts executed +system.cpu.iew.exec_refs 844731223 # number of memory reference insts executed +system.cpu.iew.exec_branches 300901770 # Number of branches executed +system.cpu.iew.exec_stores 219482540 # Number of stores executed +system.cpu.iew.exec_rate 1.795998 # Inst execution rate +system.cpu.iew.wb_sent 2441991151 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2414041975 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388322535 # num instructions producing a value +system.cpu.iew.wb_consumers 1764247998 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.738756 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786905 # average fanout of values written-back +system.cpu.iew.wb_rate 1.760820 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786920 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 827192555 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826708029 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16081773 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1174355323 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.549599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.495377 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16088134 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1168142048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.557841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.499033 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 660542597 56.25% 56.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174710504 14.88% 71.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86129545 7.33% 78.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53592661 4.56% 83.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34688707 2.95% 85.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26049111 2.22% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21601989 1.84% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22901440 1.95% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94138769 8.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 654070645 55.99% 55.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174984637 14.98% 70.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86150926 7.38% 78.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53558629 4.58% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34734385 2.97% 85.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26071538 2.23% 88.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21585678 1.85% 89.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22876428 1.96% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94109182 8.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1174355323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1168142048 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,209 +611,209 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94138769 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94109182 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3641410035 # The number of ROB reads -system.cpu.rob.rob_writes 5410940495 # The number of ROB writes -system.cpu.timesIdled 938493 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 97090759 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3634741821 # The number of ROB reads +system.cpu.rob.rob_writes 5409898345 # The number of ROB writes +system.cpu.timesIdled 948322 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 86010595 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.799716 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.799716 # CPI: Total CPI of All Threads -system.cpu.ipc 1.250444 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.250444 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318091757 # number of integer regfile reads -system.cpu.int_regfile_writes 1932096202 # number of integer regfile writes -system.cpu.fp_regfile_reads 30725 # number of floating regfile reads -system.cpu.fp_regfile_writes 534 # number of floating regfile writes +system.cpu.cpi 0.789713 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.789713 # CPI: Total CPI of All Threads +system.cpu.ipc 1.266283 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.266283 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318184796 # number of integer regfile reads +system.cpu.int_regfile_writes 1932088897 # number of integer regfile writes +system.cpu.fp_regfile_reads 30223 # number of floating regfile reads +system.cpu.fp_regfile_writes 511 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1189905456 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297551 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297551 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085475 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087401 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825936384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 825998016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 825998016 # Total data (bytes) +system.cpu.toL2Bus.throughput 1204982897 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085568 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825939456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 826001408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 826001408 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178230165 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178244432 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1633750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14189007000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14084473000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 770.551884 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391083687 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 406109.747664 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 776.507603 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391116973 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 404046.459711 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 770.551884 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376246 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376246 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 391083687 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391083687 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391083687 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391083687 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391083687 # number of overall hits -system.cpu.icache.overall_hits::total 391083687 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1493 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1493 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1493 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1493 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1493 # number of overall misses -system.cpu.icache.overall_misses::total 1493 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108163750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108163750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108163750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108163750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108163750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108163750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391085180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391085180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391085180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391085180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391085180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391085180 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 776.507603 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.379154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.379154 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391116973 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391116973 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391116973 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391116973 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391116973 # number of overall hits +system.cpu.icache.overall_hits::total 391116973 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses +system.cpu.icache.overall_misses::total 1504 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108221250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108221250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108221250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108221250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108221250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108221250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391118477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391118477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391118477 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391118477 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391118477 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391118477 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72447.253851 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72447.253851 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72447.253851 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72447.253851 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72447.253851 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 340 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71955.618351 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71955.618351 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71955.618351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71955.618351 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 344 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 114.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 530 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 530 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 530 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 530 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 530 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 530 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75133750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75133750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75133750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75133750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75133750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75133750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 968 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75754750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75754750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75754750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75754750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75754750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75754750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78020.508827 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78020.508827 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78020.508827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78020.508827 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78259.039256 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78259.039256 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933728 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31435.165334 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058547 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963512 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613441 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28123107250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14593.465528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.016964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.445357 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000794 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513174 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.959325 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6106292 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106292 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725037 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725037 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108452 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108452 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214744 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214744 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214744 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214744 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191259 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775179 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775179 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965475 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966438 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965475 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966438 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74164750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 111539773000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 111613937750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71882646250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71882646250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 74164750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 183422419250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 183496584000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 74164750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 183422419250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 183496584000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 963 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296588 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883631 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883631 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 963 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180219 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181182 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 963 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180219 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181182 # number of overall (read+write) accesses +system.cpu.l2cache.tags.replacements 1933792 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31423.528987 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058568 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963567 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.613323 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28354220250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14586.952110 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.526107 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.050770 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.445158 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958970 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6106321 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6106321 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3725040 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3725040 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108417 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108417 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7214738 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7214738 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7214738 # number of overall hits +system.cpu.l2cache.overall_hits::total 7214738 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 968 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190337 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191305 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775189 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775189 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 968 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965526 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966494 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 968 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965526 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966494 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74779750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102580412000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 102655191750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67293864000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 67293864000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 74779750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 169874276000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 169949055750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 74779750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 169874276000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 169949055750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 968 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296658 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297626 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3725040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3725040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883606 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883606 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180264 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181232 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180264 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181232 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163130 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411534 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411534 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163135 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163246 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411545 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411545 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214099 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214181 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214103 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214186 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214099 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214181 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77014.278297 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 93707.592901 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 93694.098219 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92730.383886 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92730.383886 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77014.278297 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93322.183823 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93314.197549 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77014.278297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93322.183823 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93314.197549 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214103 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214186 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77251.807851 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86177.621968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 86170.369259 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86809.621912 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86809.621912 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77251.807851 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86426.878098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86422.361701 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77251.807851 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86426.878098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86422.361701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,180 +822,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019710 # number of writebacks -system.cpu.l2cache.writebacks::total 1019710 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190296 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191259 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775179 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775179 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965475 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966438 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 61969250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96454947000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96516916250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62065331750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62065331750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61969250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158520278750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158582248000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61969250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158520278750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158582248000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019774 # number of writebacks +system.cpu.l2cache.writebacks::total 1019774 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190337 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775189 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775189 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965526 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966494 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965526 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966494 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62594250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 87638263500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 87700857750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57538532000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57538532000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62594250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145176795500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145239389750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62594250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145176795500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145239389750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163130 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163135 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163246 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411545 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411545 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214099 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214181 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214103 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214186 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214099 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214181 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64350.207684 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81034.420850 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81020.933525 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80065.806414 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80065.806414 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64350.207684 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64350.207684 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80652.401455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80644.417978 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214103 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214186 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64663.481405 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73624.749546 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73617.468029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74225.165734 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74225.165734 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64663.481405 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73861.549275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73857.021557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64663.481405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73861.549275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73857.021557 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176123 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.719090 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694209653 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180219 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.620163 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5145271250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.719090 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997978 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997978 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538667558 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538667558 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155542093 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155542093 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694209651 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694209651 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694209651 # number of overall hits -system.cpu.dcache.overall_hits::total 694209651 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11383512 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11383512 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5186409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5186409 # number of WriteReq misses +system.cpu.dcache.tags.replacements 9176168 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.562922 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694279443 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180264 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.627394 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5178034250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.562922 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538739511 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538739511 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155539929 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155539929 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694279440 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694279440 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694279440 # number of overall hits +system.cpu.dcache.overall_hits::total 694279440 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11387381 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11387381 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5188573 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5188573 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16569921 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16569921 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16569921 # number of overall misses -system.cpu.dcache.overall_misses::total 16569921 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 354593331250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 354593331250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 296662127899 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296662127899 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 461500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 461500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 651255459149 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 651255459149 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 651255459149 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 651255459149 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550051070 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550051070 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16575954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16575954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16575954 # number of overall misses +system.cpu.dcache.overall_misses::total 16575954 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 342766302500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 342766302500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 296010973410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 296010973410 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 274500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 274500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 638777275910 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 638777275910 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 638777275910 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 638777275910 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550126892 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550126892 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710779572 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710779572 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710779572 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710779572 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020695 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020695 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032268 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032268 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023312 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023312 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023312 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023312 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31149.730527 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31149.730527 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57199.909976 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57199.909976 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 461500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 461500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39303.473997 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39303.473997 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39303.473997 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13761211 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8306103 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 744858 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.474946 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 127.521348 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710855394 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710855394 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710855394 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710855394 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020700 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020700 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032282 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032282 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023318 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023318 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023318 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023318 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30100.538702 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30100.538702 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57050.555791 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57050.555791 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 274500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 274500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38536.380827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38536.380827 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12380978 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8648655 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745505 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.607505 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.782495 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725037 # number of writebacks -system.cpu.dcache.writebacks::total 3725037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4086921 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4086921 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302782 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3302782 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7389703 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7389703 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7389703 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7389703 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883627 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883627 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725040 # number of writebacks +system.cpu.dcache.writebacks::total 3725040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4090717 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4090717 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304974 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3304974 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7395691 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7395691 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7395691 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7395691 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296664 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296664 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883599 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883599 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180218 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180218 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180218 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180218 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180738700500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 180738700500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85282559486 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85282559486 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 459500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 459500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 266021259986 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 266021259986 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 266021259986 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 266021259986 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013265 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013265 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180263 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180263 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180263 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180263 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171778792500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171778792500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80694684874 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80694684874 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 272500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 272500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252473477374 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 252473477374 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252473477374 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 252473477374 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012916 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012916 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012916 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24770.293484 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24770.293484 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45275.715142 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45275.715142 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 459500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 459500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28977.662620 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28977.662620 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23542.099855 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23542.099855 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42840.692140 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42840.692140 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 272500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 272500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 3c2739180..7989e6703 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541686 # Number of seconds simulated -sim_ticks 541686426500 # Number of ticks simulated -final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.533691 # Number of seconds simulated +sim_ticks 533690503000 # Number of ticks simulated +final_tick 533690503000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133850 # Simulator instruction rate (inst/s) -host_op_rate 149320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46941984 # Simulator tick rate (ticks/s) -host_mem_usage 248124 # Number of bytes of host memory used -host_seconds 11539.49 # Real time elapsed on the host +host_inst_rate 128085 # Simulator instruction rate (inst/s) +host_op_rate 142888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44256929 # Simulator tick rate (ticks/s) +host_mem_usage 275676 # Number of bytes of host memory used +host_seconds 12058.91 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143725568 # Number of bytes read from this memory -system.physmem.bytes_read::total 143773696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70430528 # Number of bytes written to this memory -system.physmem.bytes_written::total 70430528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245712 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246464 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100477 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100477 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265329831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265418679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 130020847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 130020847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 130020847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246464 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 1100477 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 2246464 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 1100477 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 143773696 # Total number of bytes read from memory -system.physmem.bytesWritten 70430528 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 599 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 133756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 136368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 134718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 135333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 136160 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 136095 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 143598 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 146293 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 144461 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 146176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 145883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 146345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 142220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 142522 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 67428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 65656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 66095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 66425 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67930 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68755 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 70311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 70943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 70521 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 70921 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 70374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70896 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69672 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69074 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 541686363500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246464 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100477 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1615292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 444627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 139018 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143713600 # Number of bytes read from this memory +system.physmem.bytes_read::total 143761344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70434112 # Number of bytes written to this memory +system.physmem.bytes_written::total 70434112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245525 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246271 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 269282663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 269372123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 131975577 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 131975577 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 131975577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 269282663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401347700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246271 # Number of read requests accepted +system.physmem.writeReqs 1100533 # Number of write requests accepted +system.physmem.readBursts 2246271 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100533 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143722048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 39296 # Total number of bytes read from write queue +system.physmem.bytesWritten 70432960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143761344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70434112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 614 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 139609 # Per bank write bursts +system.physmem.perBankRdBursts::1 136206 # Per bank write bursts +system.physmem.perBankRdBursts::2 133832 # Per bank write bursts +system.physmem.perBankRdBursts::3 136344 # Per bank write bursts +system.physmem.perBankRdBursts::4 135019 # Per bank write bursts +system.physmem.perBankRdBursts::5 135288 # Per bank write bursts +system.physmem.perBankRdBursts::6 136231 # Per bank write bursts +system.physmem.perBankRdBursts::7 136121 # Per bank write bursts +system.physmem.perBankRdBursts::8 143692 # Per bank write bursts +system.physmem.perBankRdBursts::9 146373 # Per bank write bursts +system.physmem.perBankRdBursts::10 144432 # Per bank write bursts +system.physmem.perBankRdBursts::11 146294 # Per bank write bursts +system.physmem.perBankRdBursts::12 145666 # Per bank write bursts +system.physmem.perBankRdBursts::13 146070 # Per bank write bursts +system.physmem.perBankRdBursts::14 142065 # Per bank write bursts +system.physmem.perBankRdBursts::15 142415 # Per bank write bursts +system.physmem.perBankWrBursts::0 69121 # Per bank write bursts +system.physmem.perBankWrBursts::1 67439 # Per bank write bursts +system.physmem.perBankWrBursts::2 65729 # Per bank write bursts +system.physmem.perBankWrBursts::3 66294 # Per bank write bursts +system.physmem.perBankWrBursts::4 66241 # Per bank write bursts +system.physmem.perBankWrBursts::5 66403 # Per bank write bursts +system.physmem.perBankWrBursts::6 67965 # Per bank write bursts +system.physmem.perBankWrBursts::7 68773 # Per bank write bursts +system.physmem.perBankWrBursts::8 70328 # Per bank write bursts +system.physmem.perBankWrBursts::9 70962 # Per bank write bursts +system.physmem.perBankWrBursts::10 70540 # Per bank write bursts +system.physmem.perBankWrBursts::11 70927 # Per bank write bursts +system.physmem.perBankWrBursts::12 70302 # Per bank write bursts +system.physmem.perBankWrBursts::13 70806 # Per bank write bursts +system.physmem.perBankWrBursts::14 69598 # Per bank write bursts +system.physmem.perBankWrBursts::15 69087 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 533690432500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2246271 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1100533 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1620463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 446151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 135620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,217 +127,217 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1997603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.193624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.812437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.653287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1593724 79.78% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 230021 11.51% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 68328 3.42% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32466 1.63% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 17759 0.89% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11013 0.55% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7534 0.38% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7551 0.38% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3933 0.20% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3162 0.16% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2715 0.14% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2783 0.14% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1408 0.07% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1190 0.06% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1060 0.05% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 829 0.04% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 802 0.04% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 757 0.04% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 590 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 531 0.03% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 601 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 798 0.04% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3587 0.18% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 465 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 167 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 158 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 120 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 86 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 82 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 107 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 81 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 77 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 52 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 39 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 40 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 36 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 29 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 41 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 32 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 31 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 29 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 27 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 30 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 20 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 12 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 18 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 11 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 17 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 17 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 21 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 17 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 17 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 31 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 28 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 33 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 13 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 14 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 16 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 15 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 10 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 12 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 17 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 11 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 10 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 9 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 8 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 15 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 14 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 7 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 7 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 122 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 15 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 8 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 6 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 8 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 20 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1459 0.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1997603 # Bytes accessed per row activation -system.physmem.totQLat 50283923250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 124431529500 # Sum of mem lat for all requests -system.physmem.totBusLat 11229325000 # Total cycles spent in databus access -system.physmem.totBankLat 62918281250 # Total cycles spent in bank access -system.physmem.avgQLat 22389.56 # Average queueing delay per request -system.physmem.avgBankLat 28015.17 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55404.72 # Average memory access latency -system.physmem.avgRdBW 265.42 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 130.02 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 265.42 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 130.02 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.23 # Average read queue length over time -system.physmem.avgWrQLen 10.65 # Average write queue length over time -system.physmem.readRowHits 1005654 # Number of row buffer hits during reads -system.physmem.writeRowHits 343066 # Number of row buffer hits during writes -system.physmem.readRowHitRate 44.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes -system.physmem.avgGap 161845.21 # Average gap between requests -system.membus.throughput 395439408 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420071 # Transaction distribution -system.membus.trans_dist::ReadResp 1420070 # Transaction distribution -system.membus.trans_dist::Writeback 1100477 # Transaction distribution -system.membus.trans_dist::ReadExReq 826393 # Transaction distribution -system.membus.trans_dist::ReadExResp 826393 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593404 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214204160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214204160 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214204160 # Total data (bytes) +system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 49049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 49091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 49066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 49073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 49089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 49084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 49051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 49094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 49119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 49964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 50324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 51901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 52174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 2077885 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.053834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.951836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 184.653120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1660855 79.93% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 226890 10.92% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 69105 3.33% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 37676 1.81% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 25011 1.20% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 12112 0.58% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 8103 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4494 0.22% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3425 0.16% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2747 0.13% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2032 0.10% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1669 0.08% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1441 0.07% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1240 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1051 0.05% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 987 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 902 0.04% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 711 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 694 0.03% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3096 0.15% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 406 0.02% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 291 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 190 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 185 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 205 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 473 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 132 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 131 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 122 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 122 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 103 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 129 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 90 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 83 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 94 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 68 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 57 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 64 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 70 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 60 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 55 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 48 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 43 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 58 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 55 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 43 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 33 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 30 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 32 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 24 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 19 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 34 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 24 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 14 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 24 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 24 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 21 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 21 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 20 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 13 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 16 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 16 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 27 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 36 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 16 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 187 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 9 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 34 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 26 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 4 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 83 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2077885 # Bytes accessed per row activation +system.physmem.totQLat 32824703500 # Total ticks spent queuing +system.physmem.totMemAccLat 104040704750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11228285000 # Total ticks spent in databus transfers +system.physmem.totBankLat 59987716250 # Total ticks spent accessing banks +system.physmem.avgQLat 14616.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26712.77 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 46329.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 131.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 131.98 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.08 # Average write queue length when enqueuing +system.physmem.readRowHits 931610 # Number of row buffer hits during reads +system.physmem.writeRowHits 336677 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes +system.physmem.avgGap 159462.71 # Average gap between requests +system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.89 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 401347580 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1419678 # Transaction distribution +system.membus.trans_dist::ReadResp 1419677 # Transaction distribution +system.membus.trans_dist::Writeback 1100533 # Transaction distribution +system.membus.trans_dist::ReadExReq 826593 # Transaction distribution +system.membus.trans_dist::ReadExResp 826593 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593074 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214195392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214195392 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214195392 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12924294750 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21152142500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21079818750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.9 # Layer utilization (%) -system.cpu.branchPred.lookups 304298989 # Number of BP lookups -system.cpu.branchPred.condPredicted 250519406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15198708 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 177303182 # Number of BTB lookups -system.cpu.branchPred.BTBHits 162516904 # Number of BTB hits +system.cpu.branchPred.lookups 303467870 # Number of BP lookups +system.cpu.branchPred.condPredicted 249715061 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15195903 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 175178105 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161776963 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.660455 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17540360 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 213 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.349990 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17540871 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 204 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -379,98 +381,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1083372854 # number of cpu cycles simulated +system.cpu.numCycles 1067381007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 300343787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2195221955 # Number of instructions fetch has processed -system.cpu.fetch.Branches 304298989 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180057264 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436998042 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88977352 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 165479201 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 101 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 290623561 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6109702 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 973376815 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494162 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.204787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 299148062 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2189533318 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303467870 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179317834 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435752088 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88086251 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 164106751 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289566494 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5997594 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 968963067 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.499628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206367 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536378856 55.10% 55.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25841118 2.65% 57.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39079231 4.01% 61.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48353852 4.97% 66.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43959831 4.52% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46474608 4.77% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38397974 3.94% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19032697 1.96% 81.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175858648 18.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 533211067 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25485631 2.63% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39032754 4.03% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48282665 4.98% 66.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43767932 4.52% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46382840 4.79% 75.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38389210 3.96% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18960850 1.96% 81.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175450118 18.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973376815 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.280881 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026285 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 332723748 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 143314435 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 406466996 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20316722 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70554914 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46046806 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 803 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2374638821 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2490 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70554914 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 356505375 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 71902909 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22171 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 401350772 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73040674 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2310606044 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 153145 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5003938 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60088597 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9782199775 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 333 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 968963067 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284311 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.051314 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331377153 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 141962670 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405350137 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20317948 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69955159 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46017147 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2369104960 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2426 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69955159 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354884990 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70530339 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17935 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400511119 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73063525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2306250708 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 150920 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5011927 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60136403 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282159345 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10649371145 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9763416611 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 460 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 862 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 859 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 161072397 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 625574992 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 221105439 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85703818 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70396970 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2205173654 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 876 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2020003765 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4023223 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 477517821 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1138229874 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973376815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.075254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906645 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575839415 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 404 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 401 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160989021 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624749088 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220784728 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85932352 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70842412 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202316968 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 440 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018777354 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4015619 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474672323 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127531541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 270 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 968963067 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.083441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906294 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 290079957 29.80% 29.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153607537 15.78% 45.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161004232 16.54% 62.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120476061 12.38% 74.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123716545 12.71% 87.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73794754 7.58% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38284776 3.93% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9892649 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2520304 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 286087063 29.53% 29.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153648666 15.86% 45.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160841319 16.60% 61.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120316001 12.42% 74.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123517924 12.75% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73816539 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38325528 3.96% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9889728 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2520299 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973376815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 968963067 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 894925 3.74% 3.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5467 0.02% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 895423 3.74% 3.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5601 0.02% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available @@ -498,118 +501,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18249723 76.22% 79.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4791929 20.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18274862 76.27% 80.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4786167 19.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1237561423 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 924895 0.05% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588422338 29.13% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193095054 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236899038 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924736 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 48 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587872837 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193080663 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2020003765 # Type of FU issued -system.cpu.iq.rate 1.864551 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23942044 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011852 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5041349349 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2682881596 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957831333 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 100 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2043945677 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64652125 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018777354 # Type of FU issued +system.cpu.iq.rate 1.891337 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23962053 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011870 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5034495136 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2677178912 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957310102 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 311 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 694 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 129 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042739250 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 157 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64569425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 139648223 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271348 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192348 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46258394 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138822319 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 268987 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192391 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45937683 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5367173 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4778132 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70554914 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 34630118 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1599053 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2205174629 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7647376 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 625574992 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 221105439 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 814 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 476287 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97145 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192348 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8141918 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9600574 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17742492 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1989129664 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574576777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30874101 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69955159 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33483642 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1603224 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202317539 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7879544 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624749088 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220784728 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 378 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 478707 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97428 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192391 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8138332 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9600465 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17738797 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988042975 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574015030 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30734379 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99 # number of nop insts executed -system.cpu.iew.exec_refs 764789002 # number of memory reference insts executed -system.cpu.iew.exec_branches 238317780 # Number of branches executed -system.cpu.iew.exec_stores 190212225 # Number of stores executed -system.cpu.iew.exec_rate 1.836053 # Inst execution rate -system.cpu.iew.wb_sent 1966244201 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957831433 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295814578 # num instructions producing a value -system.cpu.iew.wb_consumers 2059506895 # num instructions consuming a value +system.cpu.iew.exec_nop 131 # number of nop insts executed +system.cpu.iew.exec_refs 764217607 # number of memory reference insts executed +system.cpu.iew.exec_branches 238311346 # Number of branches executed +system.cpu.iew.exec_stores 190202577 # Number of stores executed +system.cpu.iew.exec_rate 1.862543 # Inst execution rate +system.cpu.iew.wb_sent 1965731650 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957310231 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295404026 # num instructions producing a value +system.cpu.iew.wb_consumers 2059270839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.807163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629187 # average fanout of values written-back +system.cpu.iew.wb_rate 1.833750 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629060 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 482200307 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479343339 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15197938 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 902821901 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.908542 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.715709 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15195240 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 899007908 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.916639 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 414368116 45.90% 45.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193212165 21.40% 67.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72772864 8.06% 75.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35254508 3.90% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18855841 2.09% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30818249 3.41% 84.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19938130 2.21% 86.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11407177 1.26% 88.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106194851 11.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 410513863 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193235979 21.49% 67.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72768373 8.09% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35278706 3.92% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18862057 2.10% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30820454 3.43% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19957331 2.22% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11398634 1.27% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106172511 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 902821901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 899007908 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -620,212 +623,212 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106194851 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106172511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3001900611 # The number of ROB reads -system.cpu.rob.rob_writes 4481254115 # The number of ROB writes -system.cpu.timesIdled 1150610 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 109996039 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2995251990 # The number of ROB reads +system.cpu.rob.rob_writes 4474939624 # The number of ROB writes +system.cpu.timesIdled 1152982 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98417940 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.701411 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.701411 # CPI: Total CPI of All Threads -system.cpu.ipc 1.425698 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.425698 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9960721721 # number of integer regfile reads -system.cpu.int_regfile_writes 1937694107 # number of integer regfile writes -system.cpu.fp_regfile_reads 91 # number of floating regfile reads -system.cpu.fp_regfile_writes 89 # number of floating regfile writes -system.cpu.misc_regfile_reads 737621013 # number of misc regfile reads +system.cpu.cpi 0.691057 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.691057 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447059 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447059 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956212388 # number of integer regfile reads +system.cpu.int_regfile_writes 1937181821 # number of integer regfile writes +system.cpu.fp_regfile_reads 130 # number of floating regfile reads +system.cpu.fp_regfile_writes 139 # number of floating regfile writes +system.cpu.misc_regfile_reads 737624314 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1581534685 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709688 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22987414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22988978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856645824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856695872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes) +system.cpu.toL2Bus.throughput 1605146644 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709082 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709081 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22987676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856601984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856651520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856651520 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1321749 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10475431595 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1294249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14768966243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) system.cpu.icache.tags.replacements 22 # number of replacements -system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 628.527972 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289565308 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 374115.385013 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 290622345 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 290622345 # number of overall hits -system.cpu.icache.overall_hits::total 290622345 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1216 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1216 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1216 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1216 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1216 # number of overall misses -system.cpu.icache.overall_misses::total 1216 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 85849749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 85849749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 85849749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 85849749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 85849749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 85849749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290623561 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290623561 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290623561 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290623561 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290623561 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290623561 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 628.527972 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306898 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306898 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 289565308 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289565308 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289565308 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289565308 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289565308 # number of overall hits +system.cpu.icache.overall_hits::total 289565308 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1186 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1186 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1186 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1186 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1186 # number of overall misses +system.cpu.icache.overall_misses::total 1186 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82924749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82924749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82924749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82924749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82924749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82924749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289566494 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289566494 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289566494 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289566494 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289566494 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289566494 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70600.122533 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70600.122533 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70600.122533 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70600.122533 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69919.687184 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69919.687184 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69919.687184 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69919.687184 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 50.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59439751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59439751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59439751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59439751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59439751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59439751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57029751 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 57029751 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57029751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 57029751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57029751 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 57029751 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76009.911765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76009.911765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73681.848837 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73681.848837 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2213775 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.122109 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 21352949250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14312.491305 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.144724 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17213.727277 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.436783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.525321 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.962719 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6289580 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6289609 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3782769 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3782769 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1067024 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1067024 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7356604 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7356633 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7356604 # number of overall hits -system.cpu.l2cache.overall_hits::total 7356633 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 753 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1419326 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1420079 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826393 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826393 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 753 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2245719 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2246472 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 753 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2245719 # number of overall misses -system.cpu.l2cache.overall_misses::total 2246472 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58361250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 138416431000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 138474792250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84266311250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84266311250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58361250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 222682742250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 222741103500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58361250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 222682742250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 222741103500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 782 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7708906 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7709688 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3782769 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3782769 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893417 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893417 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 782 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9602323 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9603105 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 782 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9602323 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9603105 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962916 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184115 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436456 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436456 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962916 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233872 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233932 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962916 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233872 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233932 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77504.980080 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97522.648778 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 97512.034366 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101968.810542 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101968.810542 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77504.980080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99158.773760 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 99151.515576 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77504.980080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99158.773760 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 99151.515576 # average overall miss latency +system.cpu.l2cache.tags.replacements 2213583 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31532.604049 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9247674 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2243357 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.122248 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14306.578053 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.421352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 17205.604643 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.436602 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000623 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.525073 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.962299 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6289369 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6289396 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3782685 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3782685 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1066821 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1066821 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7356190 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7356217 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7356190 # number of overall hits +system.cpu.l2cache.overall_hits::total 7356217 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 747 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1418939 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1419686 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826593 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826593 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 747 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2245532 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246279 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 747 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2245532 # number of overall misses +system.cpu.l2cache.overall_misses::total 2246279 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55980750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125563538750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 125619519500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76414651500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 76414651500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 55980750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 201978190250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 202034171000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 55980750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 201978190250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 202034171000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7708308 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7709082 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3782685 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3782685 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893414 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893414 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9601722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9602496 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9601722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9602496 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965116 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184079 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965116 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233868 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233927 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965116 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233868 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233927 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74940.763052 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88491.146378 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88484.016536 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92445.316498 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92445.316498 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89941.708488 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89941.708488 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -834,8 +837,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100477 # number of writebacks -system.cpu.l2cache.writebacks::total 1100477 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1100533 # number of writebacks +system.cpu.l2cache.writebacks::total 1100533 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits @@ -845,176 +848,176 @@ system.cpu.l2cache.demand_mshr_hits::total 8 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 752 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419319 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1420071 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826393 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 826393 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 752 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2245712 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2246464 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 752 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2245712 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2246464 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48787000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 120499016750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120547803750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73852563750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73852563750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 194351580500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 194400367500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48787000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194351580500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 194400367500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184114 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184193 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436456 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436456 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233931 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64876.329787 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84899.178233 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84888.575113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89367.363651 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89367.363651 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418932 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1419678 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826593 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826593 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2245525 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2245525 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246271 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46519250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107766607500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107813126750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66030369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66030369000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46519250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173796976500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 173843495750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46519250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173796976500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 173843495750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184078 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233926 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233926 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62358.243968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75949.099393 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75941.957789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79882.564938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79882.564938 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9598226 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166960447 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 9597625 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.040332 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 656028832 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9601721 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.324088 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.040332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 489072771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489072771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166955934 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166955934 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 66 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 66 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 655929494 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 655929494 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 655929494 # number of overall hits -system.cpu.dcache.overall_hits::total 655929494 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11507818 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11507818 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5625600 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5625600 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656028705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656028705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656028705 # number of overall hits +system.cpu.dcache.overall_hits::total 656028705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11514039 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11514039 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5630113 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5630113 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17133418 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17133418 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17133418 # number of overall misses -system.cpu.dcache.overall_misses::total 17133418 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 381897864985 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 381897864985 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 310946372440 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 310946372440 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 692844237425 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 692844237425 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 692844237425 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 692844237425 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500476865 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500476865 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17144152 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17144152 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17144152 # number of overall misses +system.cpu.dcache.overall_misses::total 17144152 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 363445631238 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 363445631238 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307798034677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307798034677 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 225500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 671243665915 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 671243665915 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 671243665915 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 671243665915 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500586810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500586810 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673062912 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673062912 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673062912 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673062912 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022994 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022994 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032596 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032596 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025456 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025456 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025456 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025456 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33185.949325 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33185.949325 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55273.459265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55273.459265 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40438.179786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40438.179786 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29551948 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3560628 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1217583 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.270993 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 54.667874 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673172857 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673172857 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673172857 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673172857 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032622 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025468 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025468 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025468 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025468 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31565.433402 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31565.433402 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54669.956833 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54669.956833 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39152.923161 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39152.923161 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24614592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3988980 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1212230 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65133 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.305216 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.243609 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3782769 # number of writebacks -system.cpu.dcache.writebacks::total 3782769 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798912 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3798912 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732183 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3732183 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782685 # number of writebacks +system.cpu.dcache.writebacks::total 3782685 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3805731 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3805731 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736699 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3736699 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7531095 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7531095 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7531095 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7531095 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708906 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708906 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893417 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893417 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602323 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602323 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602323 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602323 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210908812007 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 210908812007 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97317389015 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97317389015 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308226201022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 308226201022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308226201022 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 308226201022 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7542430 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7542430 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7542430 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7542430 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708308 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708308 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893414 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893414 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601722 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601722 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601722 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601722 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198054864257 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 198054864257 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89469568032 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89469568032 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287524432289 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 287524432289 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287524432289 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 287524432289 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014267 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014267 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27359.110619 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27359.110619 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51397.758135 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51397.758135 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25693.688454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25693.688454 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47253.040292 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47253.040292 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 5350fe782..d049654a9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041672 # Number of seconds simulated -sim_ticks 41671895000 # Number of ticks simulated -final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041680 # Number of seconds simulated +sim_ticks 41680207000 # Number of ticks simulated +final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101828 # Simulator instruction rate (inst/s) -host_op_rate 101828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46172411 # Simulator tick rate (ticks/s) -host_mem_usage 228672 # Number of bytes of host memory used -host_seconds 902.53 # Real time elapsed on the host +host_inst_rate 118687 # Simulator instruction rate (inst/s) +host_op_rate 118687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53827332 # Simulator tick rate (ticks/s) +host_mem_usage 260144 # Number of bytes of host memory used +host_seconds 774.33 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4291046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7583816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4291046 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4291046 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4938 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 4938 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 316032 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 499 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 212 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 423 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41671821000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 4938 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4938 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 316032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 316032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 443 # Per bank write bursts +system.physmem.perBankRdBursts::1 270 # Per bank write bursts +system.physmem.perBankRdBursts::2 295 # Per bank write bursts +system.physmem.perBankRdBursts::3 499 # Per bank write bursts +system.physmem.perBankRdBursts::4 209 # Per bank write bursts +system.physmem.perBankRdBursts::5 212 # Per bank write bursts +system.physmem.perBankRdBursts::6 207 # Per bank write bursts +system.physmem.perBankRdBursts::7 265 # Per bank write bursts +system.physmem.perBankRdBursts::8 219 # Per bank write bursts +system.physmem.perBankRdBursts::9 249 # Per bank write bursts +system.physmem.perBankRdBursts::10 238 # Per bank write bursts +system.physmem.perBankRdBursts::11 236 # Per bank write bursts +system.physmem.perBankRdBursts::12 379 # Per bank write bursts +system.physmem.perBankRdBursts::13 325 # Per bank write bursts +system.physmem.perBankRdBursts::14 469 # Per bank write bursts +system.physmem.perBankRdBursts::15 423 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 41680133000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 4938 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,92 +152,83 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 858.311111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 328.631203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1420.533351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 87 24.17% 24.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 46 12.78% 36.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 36 10.00% 46.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 14 3.89% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 20 5.56% 56.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 14 3.89% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 9 2.50% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7 1.94% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 8 2.22% 66.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3 0.83% 67.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 2.22% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 5 1.39% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.67% 73.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 7 1.94% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 1.11% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 2 0.56% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 1.39% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.28% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.83% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 5 1.39% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.28% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.83% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 1.11% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.56% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.83% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.83% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.56% 85.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 4 1.11% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.28% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 4 1.11% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.56% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.83% 89.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.28% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.28% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.83% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.56% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.28% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.56% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.28% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 2 0.56% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.28% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.28% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.28% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.56% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.28% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.28% 95.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.28% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.28% 95.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.28% 95.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.56% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.28% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.28% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.28% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.28% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.28% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.28% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation -system.physmem.totQLat 20561250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 109587500 # Sum of mem lat for all requests -system.physmem.totBusLat 24690000 # Total cycles spent in databus access -system.physmem.totBankLat 64336250 # Total cycles spent in bank access -system.physmem.avgQLat 4163.88 # Average queueing delay per request -system.physmem.avgBankLat 13028.81 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22192.69 # Average memory access latency -system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation +system.physmem.totQLat 34068750 # Total ticks spent queuing +system.physmem.totMemAccLat 126422500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers +system.physmem.totBankLat 67663750 # Total ticks spent accessing banks +system.physmem.avgQLat 6899.30 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25601.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4578 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4195 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8439007.90 # Average gap between requests -system.membus.throughput 7583816 # Throughput (bytes/s) +system.physmem.avgGap 8440691.17 # Average gap between requests +system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 7582304 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -246,9 +239,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46068500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45976500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.branchPred.lookups 13412627 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted @@ -263,22 +256,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996270 # DTB read hits +system.cpu.dtb.read_hits 19996265 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996280 # DTB read accesses -system.cpu.dtb.write_hits 6501863 # DTB write hits +system.cpu.dtb.read_accesses 19996275 # DTB read accesses +system.cpu.dtb.write_hits 6501862 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501886 # DTB write accesses -system.cpu.dtb.data_hits 26498133 # DTB hits +system.cpu.dtb.write_accesses 6501885 # DTB write accesses +system.cpu.dtb.data_hits 26498127 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498166 # DTB accesses -system.cpu.itb.fetch_hits 9956949 # ITB hits +system.cpu.dtb.data_accesses 26498160 # DTB accesses +system.cpu.itb.fetch_hits 9956950 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956998 # ITB accesses +system.cpu.itb.fetch_accesses 9956999 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,17 +285,17 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83343791 # number of cpu cycles simulated +system.cpu.numCycles 83360415 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570550 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146022 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206131 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058019 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. @@ -310,16 +303,16 @@ system.cpu.execution_unit.predictedNotTakenIncorrect 799060 system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57404028 # Number of Instructions Executed. +system.cpu.execution_unit.executions 57404027 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970405 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10389 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7736037 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607754 # Number of cycles cpu stages are processed. -system.cpu.activity 90.717920 # Percentage of cycles cpu is active +system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7752656 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607759 # Number of cycles cpu stages are processed. +system.cpu.activity 90.699835 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -331,72 +324,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.906866 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.906866 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102698 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102698 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27663446 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680345 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.808030 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34092107 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.094605 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33492443 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.814111 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65317278 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026513 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.629101 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29500659 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859756 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.610710 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits system.cpu.icache.overall_hits::total 9945551 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11398 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11398 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11398 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11398 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11398 # number of overall misses -system.cpu.icache.overall_misses::total 11398 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 318279500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 318279500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 318279500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 318279500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 318279500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 318279500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956949 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 11399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses +system.cpu.icache.overall_misses::total 11399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 325867750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 325867750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 325867750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 325867750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 325867750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 325867750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956950 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27924.153360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27924.153360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27924.153360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27924.153360 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.398017 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28587.398017 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28587.398017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28587.398017 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -405,38 +398,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1878 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1878 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1878 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1878 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1878 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1878 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 259449500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 259449500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 259449500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 259449500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 259449500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 259449500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266340500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 266340500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266340500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 266340500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266340500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 266340500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27253.098739 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27253.098739 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.943277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.943277 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18199316 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -452,23 +445,23 @@ system.cpu.toL2Bus.data_through_bus 758400 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14868500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits @@ -493,17 +486,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 182392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29940500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 212332500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115205000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 182392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 145145500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 327537500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 182392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 145145500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 327537500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189283000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 221678250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122427250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 122427250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 189283000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 154822500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 344105500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 189283000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 154822500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 344105500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -528,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65279.885469 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70949.052133 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66023.787313 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66901.858304 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66901.858304 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66329.991900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66329.991900 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67746.241947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.804104 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.963995 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.963995 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69685.196436 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69685.196436 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -558,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147140500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24615500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171756000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147140500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118660500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 265801000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147140500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118660500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 265801000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282558000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -580,51 +573,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52663.027917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58330.568720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53406.716418 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.821138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.821138 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1441.367779 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492886 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488508 # number of overall hits -system.cpu.dcache.overall_hits::total 26488508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8217 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8217 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8793 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8793 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8793 # number of overall misses -system.cpu.dcache.overall_misses::total 8793 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38176750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38176750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 468176250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 468176250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 506353000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 506353000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 506353000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 506353000 # number of overall miss cycles +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits +system.cpu.dcache.overall_hits::total 26488450 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses +system.cpu.dcache.overall_misses::total 8851 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41022750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41022750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 492651500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 492651500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 533674250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 533674250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 533674250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 533674250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -635,38 +628,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001264 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001264 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66279.079861 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66279.079861 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56976.542534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56976.542534 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57585.920619 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57585.920619 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22475 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71096.620451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71096.620451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59542.119894 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59542.119894 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60295.362106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60295.362106 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23885 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 847 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.534829 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.400713 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6570 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6570 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6570 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6570 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -675,14 +668,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117222500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117222500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 148186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 148186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 148186500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 148186500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124444750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124444750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157863500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 157863500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157863500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157863500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -691,14 +684,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65187.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65187.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67060.926773 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67060.926773 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71192.648741 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71192.648741 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 758c8228e..1aa820757 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023492 # Number of seconds simulated -sim_ticks 23492267500 # Number of ticks simulated -final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023462 # Number of seconds simulated +sim_ticks 23461709500 # Number of ticks simulated +final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158745 # Simulator instruction rate (inst/s) -host_op_rate 158745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44301493 # Simulator tick rate (ticks/s) -host_mem_usage 233720 # Number of bytes of host memory used -host_seconds 530.28 # Real time elapsed on the host +host_inst_rate 165875 # Simulator instruction rate (inst/s) +host_op_rate 165875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46230980 # Simulator tick rate (ticks/s) +host_mem_usage 261164 # Number of bytes of host memory used +host_seconds 507.49 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8339084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5898111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14237195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8339084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8339084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5226 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 5226 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 334464 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 446 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23492140500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5226 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8352674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5908521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14261194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8352674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8352674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8352674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5908521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14261194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 466 # Per bank write bursts +system.physmem.perBankRdBursts::1 290 # Per bank write bursts +system.physmem.perBankRdBursts::2 300 # Per bank write bursts +system.physmem.perBankRdBursts::3 524 # Per bank write bursts +system.physmem.perBankRdBursts::4 220 # Per bank write bursts +system.physmem.perBankRdBursts::5 226 # Per bank write bursts +system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::7 288 # Per bank write bursts +system.physmem.perBankRdBursts::8 240 # Per bank write bursts +system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::11 254 # Per bank write bursts +system.physmem.perBankRdBursts::12 400 # Per bank write bursts +system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::15 447 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 23461582500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5228 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,135 +152,127 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 780.923077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 283.989164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1375.157964 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 120 28.85% 28.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 59 14.18% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 37 8.89% 51.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 19 4.57% 56.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16 3.85% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 20 4.81% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8 1.92% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8 1.92% 68.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 1.20% 70.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 5 1.20% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 1.44% 72.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 1.92% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.44% 76.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 4 0.96% 77.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.96% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 2 0.48% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 1.20% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.96% 83.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.72% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.72% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.96% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 4 0.96% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.48% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.24% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.48% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.24% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.48% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.24% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.24% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 5 1.20% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.24% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.24% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.24% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 416 # Bytes accessed per row activation -system.physmem.totQLat 21308250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 115583250 # Sum of mem lat for all requests -system.physmem.totBusLat 26130000 # Total cycles spent in databus access -system.physmem.totBankLat 68145000 # Total cycles spent in bank access -system.physmem.avgQLat 4077.35 # Average queueing delay per request -system.physmem.avgBankLat 13039.61 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22116.96 # Average memory access latency -system.physmem.avgRdBW 14.24 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.24 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 750 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 442.026667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.409345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 807.667918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 266 35.47% 35.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 111 14.80% 50.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 59 7.87% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 40 5.33% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 26 3.47% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 30 4.00% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 24 3.20% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 16 2.13% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.20% 77.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 13 1.73% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 15 2.00% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.73% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 37 4.93% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 11 1.47% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.80% 90.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.40% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 7 0.93% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.93% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.40% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.40% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 8 1.07% 94.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.13% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3 0.40% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.27% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.53% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 2 0.27% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.13% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.13% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.40% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.40% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.40% 97.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.13% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.13% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 3 0.40% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.13% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 2 0.27% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.13% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.13% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.13% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.13% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.13% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.13% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation +system.physmem.totQLat 37518250 # Total ticks spent queuing +system.physmem.totMemAccLat 134402000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers +system.physmem.totBankLat 70743750 # Total ticks spent accessing banks +system.physmem.avgQLat 7176.41 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25708.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4810 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4478 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.04 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4495243.11 # Average gap between requests -system.membus.throughput 14237195 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3520 # Transaction distribution -system.membus.trans_dist::ReadResp 3520 # Transaction distribution -system.membus.trans_dist::ReadExReq 1706 # Transaction distribution -system.membus.trans_dist::ReadExResp 1706 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334464 # Total data (bytes) +system.physmem.avgGap 4487678.37 # Average gap between requests +system.physmem.pageHitRate 85.65 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.19 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 14261194 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3523 # Transaction distribution +system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.membus.trans_dist::ReadExReq 1705 # Transaction distribution +system.membus.trans_dist::ReadExResp 1705 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49069500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49013750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14868892 # Number of BP lookups -system.cpu.branchPred.condPredicted 10787177 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926932 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8430316 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6969924 # Number of BTB hits +system.cpu.branchPred.lookups 14847721 # Number of BP lookups +system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6957683 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.676901 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1469870 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3126 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.809492 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23134581 # DTB read hits -system.cpu.dtb.read_misses 192685 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23327266 # DTB read accesses -system.cpu.dtb.write_hits 7072669 # DTB write hits -system.cpu.dtb.write_misses 1128 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7073797 # DTB write accesses -system.cpu.dtb.data_hits 30207250 # DTB hits -system.cpu.dtb.data_misses 193813 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 30401063 # DTB accesses -system.cpu.itb.fetch_hits 14756036 # ITB hits -system.cpu.itb.fetch_misses 101 # ITB misses +system.cpu.dtb.read_hits 23117785 # DTB read hits +system.cpu.dtb.read_misses 192281 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23310066 # DTB read accesses +system.cpu.dtb.write_hits 7068175 # DTB write hits +system.cpu.dtb.write_misses 1137 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7069312 # DTB write accesses +system.cpu.dtb.data_hits 30185960 # DTB hits +system.cpu.dtb.data_misses 193418 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30379378 # DTB accesses +system.cpu.itb.fetch_hits 14734161 # ITB hits +system.cpu.itb.fetch_misses 103 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14756137 # ITB accesses +system.cpu.itb.fetch_accesses 14734264 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,237 +286,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46984536 # number of cpu cycles simulated +system.cpu.numCycles 46923420 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15488073 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127117981 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14868892 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8439794 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22159630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4494895 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5563054 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2312 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14756036 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 325999 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46746670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.719295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15463377 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126961895 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8425661 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22130057 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473004 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5559399 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 324640 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24587040 52.60% 52.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2365337 5.06% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1191741 2.55% 60.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1747442 3.74% 63.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2760154 5.90% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1154764 2.47% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1218466 2.61% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 772204 1.65% 76.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10949522 23.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24541545 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2755702 5.90% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771783 1.65% 76.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10936610 23.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46746670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705528 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17316199 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4260248 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20549941 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1098483 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3521799 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2517933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12169 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124122749 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32253 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3521799 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18461305 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 962240 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7648 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20480612 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3313066 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121283530 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 398899 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150534218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7060874 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.705726 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17289391 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20524695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3504753 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123979131 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3504753 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18431775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20455401 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121154586 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 88974234 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157440436 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150394666 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 733 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 729 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8785388 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25392018 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8252125 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2596537 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 925406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105547434 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2098 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96644788 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 177437 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20878127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15672265 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1709 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46746670 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.067415 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876261 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20546873 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 749 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25363135 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8241350 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105438340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96565073 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20784584 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15622472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12170136 26.03% 26.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9358863 20.02% 46.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8416132 18.00% 64.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6289434 13.45% 77.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4916374 10.52% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2864607 6.13% 94.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1727461 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 797242 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 206421 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12133901 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9340973 20.01% 46.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4921134 10.54% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2853572 6.11% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 798698 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46746670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46671602 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 188535 12.02% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 207 0.01% 12.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7191 0.46% 12.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5653 0.36% 12.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842893 53.74% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 446132 28.45% 95.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77750 4.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 198 0.01% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7114 0.45% 12.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5683 0.36% 12.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843073 53.81% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 444038 28.34% 94.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58781922 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479844 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58732394 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2799901 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115380 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387749 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311051 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760106 0.79% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23852037 24.68% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7156472 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115272 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387143 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 310920 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760028 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96644788 # Type of FU issued -system.cpu.iq.rate 2.056949 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568361 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016228 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226659796 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117693658 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87130802 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15122248 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8768674 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7065649 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90221948 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7991194 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1517986 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96565073 # Type of FU issued +system.cpu.iq.rate 2.057929 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226434514 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117518312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90145383 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5395820 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18680 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34810 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1751022 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5366937 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740247 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10535 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1932 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3521799 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133427 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18321 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115791419 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 375079 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25392018 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8252125 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2892 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34810 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 537595 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 497018 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034613 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95405393 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23327731 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1239395 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3504753 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115674273 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25363135 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8241350 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34629 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 535207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 494157 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1227384 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10241887 # number of nop insts executed -system.cpu.iew.exec_refs 30401730 # number of memory reference insts executed -system.cpu.iew.exec_branches 12031007 # Number of branches executed -system.cpu.iew.exec_stores 7073999 # Number of stores executed -system.cpu.iew.exec_rate 2.030570 # Inst execution rate -system.cpu.iew.wb_sent 94717591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94196451 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64508240 # num instructions producing a value -system.cpu.iew.wb_consumers 89892394 # num instructions consuming a value +system.cpu.iew.exec_nop 10234972 # number of nop insts executed +system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed +system.cpu.iew.exec_branches 12022158 # Number of branches executed +system.cpu.iew.exec_stores 7069522 # Number of stores executed +system.cpu.iew.exec_rate 2.031772 # Inst execution rate +system.cpu.iew.wb_sent 94652013 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64474348 # num instructions producing a value +system.cpu.iew.wb_consumers 89850693 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004839 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717616 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23889448 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23772324 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 915179 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43224871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.126161 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.744271 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16760873 38.78% 38.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9929358 22.97% 61.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4485318 10.38% 72.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2262602 5.23% 77.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1610546 3.73% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1125217 2.60% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 721883 1.67% 85.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 816904 1.89% 87.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5512170 12.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16723467 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9908467 22.95% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818064 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5518957 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43224871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43166849 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,212 +528,212 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5512170 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5518957 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153504164 # The number of ROB reads -system.cpu.rob.rob_writes 235130535 # The number of ROB writes -system.cpu.timesIdled 5262 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 237866 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153322231 # The number of ROB reads +system.cpu.rob.rob_writes 234879486 # The number of ROB writes +system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 251818 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.558146 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558146 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791647 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791647 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129142322 # number of integer regfile reads -system.cpu.int_regfile_writes 70569523 # number of integer regfile writes -system.cpu.fp_regfile_reads 6189856 # number of floating regfile reads -system.cpu.fp_regfile_writes 6047601 # number of floating regfile writes -system.cpu.misc_regfile_reads 714537 # number of misc regfile reads +system.cpu.cpi 0.557420 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.557420 # CPI: Total CPI of All Threads +system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129048096 # number of integer regfile reads +system.cpu.int_regfile_writes 70519804 # number of integer regfile writes +system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads +system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes +system.cpu.misc_regfile_reads 714547 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37717943 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12006 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution +system.cpu.toL2Bus.throughput 37824354 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4598 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 735488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 886080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 736640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7042000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17871250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17847250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9559 # number of replacements -system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9576 # number of replacements +system.cpu.icache.tags.tagsinuse 1596.482982 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14719875 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1278.877063 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14741729 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14741729 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14741729 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14741729 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14741729 # number of overall hits -system.cpu.icache.overall_hits::total 14741729 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14307 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14307 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14307 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14307 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14307 # number of overall misses -system.cpu.icache.overall_misses::total 14307 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 399491250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 399491250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 399491250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 399491250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 399491250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 399491250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14756036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14756036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14756036 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14756036 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14756036 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14756036 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482982 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14719875 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14719875 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14719875 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14719875 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14719875 # number of overall hits +system.cpu.icache.overall_hits::total 14719875 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14285 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14285 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14285 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14285 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14285 # number of overall misses +system.cpu.icache.overall_misses::total 14285 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413142250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413142250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413142250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413142250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413142250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413142250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14734160 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14734160 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14734160 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14734160 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14734160 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14734160 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27922.782554 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27922.782554 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27922.782554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27922.782554 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28921.403570 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28921.403570 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28921.403570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28921.403570 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2815 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2815 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2815 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2815 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2815 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2815 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11492 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11492 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11492 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11492 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11492 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11492 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295512250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 295512250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295512250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 295512250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295512250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 295512250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000779 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000779 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25714.605813 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25714.605813 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2775 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2775 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2775 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2775 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2775 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2775 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11510 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11510 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11510 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11510 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11510 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11510 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303669750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 303669750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303669750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 303669750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303669750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 303669750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000781 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000781 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26383.123371 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26383.123371 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2404.485668 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8502 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.370226 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2409.583503 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8517 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3590 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.372423 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.679636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.666457 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 379.139575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.678720 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447961 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 381.456822 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061269 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011570 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073379 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8431 # number of ReadReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011641 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8448 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8486 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8431 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8511 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8431 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits -system.cpu.l2cache.overall_hits::total 8511 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3061 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 459 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3520 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1706 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1706 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3061 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5226 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3061 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses -system.cpu.l2cache.overall_misses::total 5226 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 199703250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34029500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 233732750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114147250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 114147250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 199703250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 148176750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 347880000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 199703250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 148176750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 347880000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 11492 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 514 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12006 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits::total 8503 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8448 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8529 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8448 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits +system.cpu.l2cache.overall_hits::total 8529 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3062 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 461 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3523 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1705 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1705 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3062 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2166 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5228 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2166 # number of overall misses +system.cpu.l2cache.overall_misses::total 5228 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207669750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34561250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 242231000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124309250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 124309250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207669750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158870500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 366540250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207669750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158870500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 366540250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11510 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 516 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12026 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11492 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13737 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11492 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13737 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266359 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892996 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.293187 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985557 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985557 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266359 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.380432 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266359 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.380432 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65241.179353 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74138.344227 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66401.349432 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66909.290739 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66909.290739 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65241.179353 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68441.916859 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66567.164179 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65241.179353 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68441.916859 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66567.164179 # average overall miss latency +system.cpu.l2cache.demand_accesses::cpu.inst 11510 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2247 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13757 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11510 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2247 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13757 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266030 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.893411 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.292949 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266030 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963952 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.380025 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.603527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74970.173536 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68757.025263 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.651026 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.651026 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70110.988906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70110.988906 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,178 +742,178 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3061 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3520 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3061 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5226 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3061 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5226 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160781250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28303000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 189084250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93191250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93191250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160781250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121494250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282275500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160781250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121494250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282275500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266359 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892996 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293187 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266359 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.380432 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266359 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.380432 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52525.726887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61662.309368 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53717.116477 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54625.586166 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54625.586166 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52525.726887 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56117.436490 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52525.726887 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56117.436490 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3062 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3523 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2166 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168835250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28858250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103389750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103389750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168835250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132248000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 301083250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168835250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132248000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 301083250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292949 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.380025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.380025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.879817 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56115.100766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.149560 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.149560 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 159 # number of replacements +system.cpu.dcache.tags.tagsinuse 1459.152637 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21603146 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21603146 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492891 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492891 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28096037 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28096037 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28096037 # number of overall hits -system.cpu.dcache.overall_hits::total 28096037 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 988 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 988 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8212 # number of WriteReq misses +system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152637 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21586035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492869 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 264 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 264 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28078904 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28078904 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28078904 # number of overall hits +system.cpu.dcache.overall_hits::total 28078904 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 974 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 974 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8234 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8234 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9200 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9200 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9200 # number of overall misses -system.cpu.dcache.overall_misses::total 9200 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 60150500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 60150500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 476870547 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 476870547 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9208 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9208 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9208 # number of overall misses +system.cpu.dcache.overall_misses::total 9208 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58289750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 505815795 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 505815795 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 537021047 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 537021047 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 537021047 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 537021047 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21604134 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21604134 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 564105545 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 564105545 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 564105545 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 564105545 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 237 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28105237 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28105237 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28105237 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28105237 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001263 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004219 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004219 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60881.072874 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60881.072874 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58069.964321 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58069.964321 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 265 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 265 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28088112 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28088112 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28088112 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28088112 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.739220 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.739220 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.142701 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.142701 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58371.852935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58371.852935 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21919 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.235119 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.583333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108 # number of writebacks -system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 475 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 475 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6481 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6481 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6956 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6956 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6956 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6956 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 109 # number of writebacks +system.cpu.dcache.writebacks::total 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6503 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6503 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6962 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6962 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6962 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6962 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35017250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35017250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116268497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116268497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126440497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126440497 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151285747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151285747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151285747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151285747 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161992997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161992997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161992997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161992997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003774 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003774 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68259.746589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68259.746589 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67168.398036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.980583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.980583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73044.770075 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73044.770075 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a815317b1..4425c72f1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074201 # Number of seconds simulated -sim_ticks 74201024500 # Number of ticks simulated -final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074220 # Number of seconds simulated +sim_ticks 74219948500 # Number of ticks simulated +final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115322 # Simulator instruction rate (inst/s) -host_op_rate 126267 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49662501 # Simulator tick rate (ticks/s) -host_mem_usage 251448 # Number of bytes of host memory used -host_seconds 1494.11 # Real time elapsed on the host +host_inst_rate 110839 # Simulator instruction rate (inst/s) +host_op_rate 121359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47744278 # Simulator tick rate (ticks/s) +host_mem_usage 278976 # Number of bytes of host memory used +host_seconds 1554.53 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111872 # Number of bytes read from this memory -system.physmem.bytes_read::total 243200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1748 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3800 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1769895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1507688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3277583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1769895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1769895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3801 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 243200 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 216 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 191 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 200 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74201006000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3801 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory +system.physmem.bytes_read::total 242752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3794 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 306 # Per bank write bursts +system.physmem.perBankRdBursts::1 215 # Per bank write bursts +system.physmem.perBankRdBursts::2 133 # Per bank write bursts +system.physmem.perBankRdBursts::3 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 298 # Per bank write bursts +system.physmem.perBankRdBursts::5 299 # Per bank write bursts +system.physmem.perBankRdBursts::6 264 # Per bank write bursts +system.physmem.perBankRdBursts::7 216 # Per bank write bursts +system.physmem.perBankRdBursts::8 246 # Per bank write bursts +system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::10 289 # Per bank write bursts +system.physmem.perBankRdBursts::11 193 # Per bank write bursts +system.physmem.perBankRdBursts::12 189 # Per bank write bursts +system.physmem.perBankRdBursts::13 206 # Per bank write bursts +system.physmem.perBankRdBursts::14 217 # Per bank write bursts +system.physmem.perBankRdBursts::15 200 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 74219930000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3794 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,114 +152,100 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 616.966581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.267348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1216.553816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 139 35.73% 35.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 59 15.17% 50.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 33 8.48% 59.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 24 6.17% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15 3.86% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 13 3.34% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 4 1.03% 73.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7 1.80% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 1.29% 76.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 8 2.06% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 1.03% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 1.03% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.77% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 1.29% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 4 1.03% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 1.03% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.26% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.26% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.77% 87.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.77% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.77% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.51% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.26% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.77% 90.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.77% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.26% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.26% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.26% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.26% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.51% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.26% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.26% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.26% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.26% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.26% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.26% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.26% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.26% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.26% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.26% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.26% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 4 1.03% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.26% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.26% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.26% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.26% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.26% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.26% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.26% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.26% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.26% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.26% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.26% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.26% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 389 # Bytes accessed per row activation -system.physmem.totQLat 12962000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86183250 # Sum of mem lat for all requests -system.physmem.totBusLat 19005000 # Total cycles spent in databus access -system.physmem.totBankLat 54216250 # Total cycles spent in bank access -system.physmem.avgQLat 3410.16 # Average queueing delay per request -system.physmem.avgBankLat 14263.68 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22673.84 # Average memory access latency -system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation +system.physmem.totQLat 25205500 # Total ticks spent queuing +system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers +system.physmem.totBankLat 56540000 # Total ticks spent accessing banks +system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3412 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 3077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19521443.30 # Average gap between requests -system.membus.throughput 3277583 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2726 # Transaction distribution -system.membus.trans_dist::ReadResp 2725 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 1075 # Transaction distribution -system.membus.trans_dist::ReadExResp 1075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7605 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 243200 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 243200 # Total data (bytes) +system.physmem.avgGap 19562448.60 # Average gap between requests +system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3270711 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2723 # Transaction distribution +system.membus.trans_dist::ReadResp 2722 # Transaction distribution +system.membus.trans_dist::ReadExReq 1071 # Transaction distribution +system.membus.trans_dist::ReadExResp 1071 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 242752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35707998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94803777 # Number of BP lookups -system.cpu.branchPred.condPredicted 74793629 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6279390 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44652033 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43049215 # Number of BTB hits +system.cpu.branchPred.lookups 94784279 # Number of BP lookups +system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.410425 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4355984 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88442 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -301,135 +289,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148402050 # number of cpu cycles simulated +system.cpu.numCycles 148439898 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39645282 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380210735 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94803777 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47405199 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80366135 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283939 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7211893 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5835 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 74 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36839707 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1829204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148218142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68020669 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5263809 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10529342 7.10% 56.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10284383 6.94% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8663442 5.85% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6544357 4.42% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6237651 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8018779 5.41% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655710 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148218142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638831 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.562032 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45496346 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5881053 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74801402 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1203851 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20835490 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14335605 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164633 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392823460 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 736203 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20835490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50883815 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 724795 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 600466 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70555670 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4617906 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371356593 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 342994 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3662384 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1507069248 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3196133 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25185 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13032916 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43019038 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16425001 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5693552 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3686945 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329243417 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249464214 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 795417 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139561180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362246737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148218142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761802 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56048230 37.81% 37.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22642926 15.28% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24814212 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20312337 13.70% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12552656 8.47% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6518158 4.40% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4033272 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1116001 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 180350 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148218142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 965237 38.47% 38.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5595 0.22% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168121 46.56% 85.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 370007 14.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194903493 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979289 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -448,93 +436,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33083 0.01% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164442 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254821 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76413 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465720 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38359883 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13948512 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249464214 # Type of FU issued -system.cpu.iq.rate 1.681002 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2509108 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646714008 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466681926 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237887502 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3737087 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2188015 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1841410 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250098110 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875212 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2005238 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued +system.cpu.iq.rate 1.680523 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13169554 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11470 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18663 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3780367 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 113 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20835490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18710 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 879 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329307607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785363 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43019038 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16425001 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18663 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889158 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3759638 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7648796 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242968769 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36856935 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6495445 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 16987 # number of nop insts executed -system.cpu.iew.exec_refs 50502724 # number of memory reference insts executed -system.cpu.iew.exec_branches 53433142 # Number of branches executed -system.cpu.iew.exec_stores 13645789 # Number of stores executed -system.cpu.iew.exec_rate 1.637233 # Inst execution rate -system.cpu.iew.wb_sent 240789077 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239728912 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148477198 # num instructions producing a value -system.cpu.iew.wb_consumers 267296630 # num instructions consuming a value +system.cpu.iew.exec_nop 17196 # number of nop insts executed +system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed +system.cpu.iew.exec_branches 53426072 # Number of branches executed +system.cpu.iew.exec_stores 13648456 # Number of stores executed +system.cpu.iew.exec_rate 1.636760 # Inst execution rate +system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148474079 # num instructions producing a value +system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615402 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555477 # average fanout of values written-back +system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140636703 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6125970 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127382652 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481135 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.185870 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57681624 45.28% 45.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696418 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13781439 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7634613 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4380226 3.44% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1319827 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1706186 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1307951 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7874368 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127382652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -545,220 +533,212 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7874368 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448810677 # The number of ROB reads -system.cpu.rob.rob_writes 679560182 # The number of ROB writes -system.cpu.timesIdled 2800 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 183908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448787441 # The number of ROB reads +system.cpu.rob.rob_writes 679451137 # The number of ROB writes +system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861285 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861285 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161056 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161056 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079439367 # number of integer regfile reads -system.cpu.int_regfile_writes 384873719 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913212 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497494 # number of floating regfile writes -system.cpu.misc_regfile_reads 54494427 # number of misc regfile reads +system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads +system.cpu.int_regfile_writes 384871783 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads +system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes +system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5172543 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4896 # Transaction distribution +system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11979 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6609745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2391 # number of replacements -system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2394 # number of replacements +system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36834377 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36834377 # number of overall hits -system.cpu.icache.overall_hits::total 36834377 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5330 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5330 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5330 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5330 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5330 # number of overall misses -system.cpu.icache.overall_misses::total 5330 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 215954243 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 215954243 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 215954243 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 215954243 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 215954243 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 215954243 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36839707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36839707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36839707 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36839707 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36839707 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36839707 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits +system.cpu.icache.overall_hits::total 36845555 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses +system.cpu.icache.overall_misses::total 5337 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40516.743527 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40516.743527 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40516.743527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40516.743527 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1739 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 82.809524 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1205 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1205 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1205 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1205 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1205 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1205 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4125 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4125 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4125 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4125 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4125 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4125 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 162387254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 162387254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 162387254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 162387254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 162387254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 162387254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39366.607030 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39366.607030 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39366.607030 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39366.607030 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1961.044100 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2153 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2735 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.787203 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.994051 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1423.034105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 533.015945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.059846 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2065 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2152 # number of ReadReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2065 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 95 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2160 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2065 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 95 # number of overall hits -system.cpu.l2cache.overall_hits::total 2160 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2058 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 2073 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2169 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2073 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits +system.cpu.l2cache.overall_hits::total 2169 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2053 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2743 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2058 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3818 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2058 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses -system.cpu.l2cache.overall_misses::total 3818 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137602750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 47264250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 184867000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68147750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 68147750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137602750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 115412000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 253014750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137602750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 115412000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 253014750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4123 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 772 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4895 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_misses::total 2738 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2053 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3809 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses +system.cpu.l2cache.overall_misses::total 3809 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4123 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1855 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 5978 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4123 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1855 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4126 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 5978 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.499151 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887306 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.560368 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.499151 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.948787 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.638675 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.499151 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.948787 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.638675 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66862.366375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68998.905109 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67395.916879 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63393.255814 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63393.255814 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66862.366375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66268.923520 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66862.366375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66268.923520 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497576 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.558890 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,123 +747,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2053 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2726 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1748 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3801 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2053 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1748 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3801 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111409500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38132750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 149542250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54590750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54590750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111409500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92723500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 204133000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111409500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92723500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 204133000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871762 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.556895 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942318 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.635831 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942318 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.635831 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54266.682903 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56660.846954 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54857.758621 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50782.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50782.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 674 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2723 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46753571 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46753571 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46753571 # number of overall hits -system.cpu.dcache.overall_hits::total 46753571 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1913 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1913 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits +system.cpu.dcache.overall_hits::total 46741275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9643 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9643 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9643 # number of overall misses -system.cpu.dcache.overall_misses::total 9643 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114314976 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114314976 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 447415748 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 447415748 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses +system.cpu.dcache.overall_misses::total 9625 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 561730724 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 561730724 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 561730724 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 561730724 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34398927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34398927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46763214 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46763214 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46763214 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46763214 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses @@ -892,68 +864,68 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59756.913748 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59756.913748 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57880.433118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57880.433118 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58252.693560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58252.693560 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 154 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.272727 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1140 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6646 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6646 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7786 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7786 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7786 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7786 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 773 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1084 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1084 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48960262 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48960262 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69313496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 69313496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118273758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 118273758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118273758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 118273758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63337.984476 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63337.984476 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63942.339483 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63942.339483 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 06f12379e..003c2ae7a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144337 # Number of seconds simulated -sim_ticks 144337151000 # Number of ticks simulated -final_tick 144337151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144463 # Number of seconds simulated +sim_ticks 144463317000 # Number of ticks simulated +final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71990 # Simulator instruction rate (inst/s) -host_op_rate 120663 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78676444 # Simulator tick rate (ticks/s) -host_mem_usage 280564 # Number of bytes of host memory used -host_seconds 1834.57 # Real time elapsed on the host +host_inst_rate 66822 # Simulator instruction rate (inst/s) +host_op_rate 111999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73091533 # Simulator tick rate (ticks/s) +host_mem_usage 308580 # Number of bytes of host memory used +host_seconds 1976.47 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125184 # Number of bytes read from this memory -system.physmem.bytes_read::total 343168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1956 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5362 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1510242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 867303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2377545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1510242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1510242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1510242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 867303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2377545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5363 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 5363 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 343168 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 343168 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 155 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 287 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 285 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 144337117000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5363 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory +system.physmem.bytes_read::total 342656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5354 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 289 # Per bank write bursts +system.physmem.perBankRdBursts::1 357 # Per bank write bursts +system.physmem.perBankRdBursts::2 453 # Per bank write bursts +system.physmem.perBankRdBursts::3 356 # Per bank write bursts +system.physmem.perBankRdBursts::4 332 # Per bank write bursts +system.physmem.perBankRdBursts::5 326 # Per bank write bursts +system.physmem.perBankRdBursts::6 402 # Per bank write bursts +system.physmem.perBankRdBursts::7 377 # Per bank write bursts +system.physmem.perBankRdBursts::8 341 # Per bank write bursts +system.physmem.perBankRdBursts::9 276 # Per bank write bursts +system.physmem.perBankRdBursts::10 232 # Per bank write bursts +system.physmem.perBankRdBursts::11 277 # Per bank write bursts +system.physmem.perBankRdBursts::12 205 # Per bank write bursts +system.physmem.perBankRdBursts::13 465 # Per bank write bursts +system.physmem.perBankRdBursts::14 384 # Per bank write bursts +system.physmem.perBankRdBursts::15 282 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 144463266500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5354 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,350 +152,344 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 668.557769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 237.238454 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1295.396575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 170 33.86% 33.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 76 15.14% 49.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 42 8.37% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 23 4.58% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 26 5.18% 67.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11 2.19% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 3.19% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 9 1.79% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.79% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 1.39% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.60% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 1.59% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 1.00% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.60% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.80% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 1.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.80% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 1.00% 84.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.40% 85.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.40% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.60% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 1.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.60% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.40% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.20% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.40% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 4 0.80% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.80% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.20% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.40% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 4 0.80% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.40% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.40% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 5 1.00% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.20% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.20% 95.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.20% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.20% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.40% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.20% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 2 0.40% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.20% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 5 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 502 # Bytes accessed per row activation -system.physmem.totQLat 12694000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests -system.physmem.totBusLat 26815000 # Total cycles spent in databus access -system.physmem.totBankLat 79695000 # Total cycles spent in bank access -system.physmem.avgQLat 2366.96 # Average queueing delay per request -system.physmem.avgBankLat 14860.15 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22227.11 # Average memory access latency -system.physmem.avgRdBW 2.38 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.38 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation +system.physmem.totQLat 28805000 # Total ticks spent queuing +system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers +system.physmem.totBankLat 82293750 # Total ticks spent accessing banks +system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4861 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4397 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.64 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26913503.08 # Average gap between requests -system.membus.throughput 2376658 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3834 # Transaction distribution -system.membus.trans_dist::ReadResp 3831 # Transaction distribution -system.membus.trans_dist::UpgradeReq 155 # Transaction distribution -system.membus.trans_dist::UpgradeResp 155 # Transaction distribution -system.membus.trans_dist::ReadExReq 1529 # Transaction distribution -system.membus.trans_dist::ReadExResp 1529 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11033 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 343040 # Total data (bytes) +system.physmem.avgGap 26982306.03 # Average gap between requests +system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2371924 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3822 # Transaction distribution +system.membus.trans_dist::ReadResp 3822 # Transaction distribution +system.membus.trans_dist::UpgradeReq 163 # Transaction distribution +system.membus.trans_dist::UpgradeResp 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 1532 # Transaction distribution +system.membus.trans_dist::ReadExResp 1532 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18643050 # Number of BP lookups -system.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1490032 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10785938 # Number of BTB hits +system.cpu.branchPred.lookups 18648234 # Number of BP lookups +system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1319504 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23183 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 288958646 # number of cpu cycles simulated +system.cpu.numCycles 289221873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23449793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10399 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848467 1.06% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2311919 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3216253 1.19% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3385278 1.26% 85.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3830479 1.42% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2556488 0.95% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064518 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715304 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41579230 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 32723 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42705730 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2069 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30099442 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18921052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3023 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 133548 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2286947 84.14% 88.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 301448 11.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210947 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035610 2.70% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1446949 0.56% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22551399 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260554870 # Type of FU issued -system.cpu.iq.rate 0.901703 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010432 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4887232 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3589351 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349681 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2459714 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued +system.cpu.iq.rate 0.900700 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26598 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 287421 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9583725 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133416 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30099442 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13828 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 287421 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 641114 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 899581 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87035316 # number of memory reference insts executed -system.cpu.iew.exec_branches 14266808 # Number of branches executed -system.cpu.iew.exec_stores 22347618 # Number of stores executed -system.cpu.iew.exec_rate 0.895563 # Inst execution rate -system.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257541896 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206006775 # num instructions producing a value -system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value +system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed +system.cpu.iew.exec_branches 14265860 # Number of branches executed +system.cpu.iew.exec_stores 22347175 # Number of stores executed +system.cpu.iew.exec_rate 0.894581 # Inst execution rate +system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back +system.cpu.iew.wb_producers 205928299 # num instructions producing a value +system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.891276 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557971 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1491544 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57071451 22.34% 83.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14008929 5.48% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2970306 1.16% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 908783 0.36% 96.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -504,224 +500,222 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571301422 # The number of ROB reads -system.cpu.rob.rob_writes 659310799 # The number of ROB writes -system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571692691 # The number of ROB reads +system.cpu.rob.rob_writes 659422929 # The number of ROB writes +system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.187901 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.187901 # CPI: Total CPI of All Threads -system.cpu.ipc 0.457059 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.457059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451358394 # number of integer regfile reads -system.cpu.int_regfile_writes 233998694 # number of integer regfile writes -system.cpu.fp_regfile_reads 3217923 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009376 # number of floating regfile writes -system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads -system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes -system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads +system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 451224157 # number of integer regfile reads +system.cpu.int_regfile_writes 233957254 # number of integer regfile writes +system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads +system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes +system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads +system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes +system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3892220 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7233 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7229 # Transaction distribution +system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1536 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1536 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13381 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4322 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17703 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 551808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 551808 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4482000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10834750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3517155 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4647 # number of replacements -system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6612 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4653 # number of replacements +system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.794202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.794202 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits -system.cpu.icache.overall_hits::total 22335618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8823 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8823 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8823 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8823 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8823 # number of overall misses -system.cpu.icache.overall_misses::total 8823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000395 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000395 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000395 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000395 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000395 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000395 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 978 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits +system.cpu.icache.overall_hits::total 22344301 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses +system.cpu.icache.overall_misses::total 8911 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.529412 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6769 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6769 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6769 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6769 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6769 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6769 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262819250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 262819250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262819250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 262819250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262819250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 262819250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38826.894667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38826.894667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2554.251018 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3246 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3834 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.846635 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.761986 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158882 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330149 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009532 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.077950 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3206 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3242 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3206 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 3227 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 43 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3249 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3206 # number of overall hits +system.cpu.l2cache.demand_hits::total 3270 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3227 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 43 # number of overall hits -system.cpu.l2cache.overall_hits::total 3249 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3835 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 155 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 155 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1529 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1529 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3407 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1957 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5364 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3407 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1957 # number of overall misses -system.cpu.l2cache.overall_misses::total 5364 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223827000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31029500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 254856500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 96683500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 96683500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 223827000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 127713000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 351540000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 223827000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 127713000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 351540000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6613 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 464 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7077 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_hits::total 3270 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3393 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 430 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3823 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 163 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 163 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1532 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1532 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5355 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses +system.cpu.l2cache.overall_misses::total 5355 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 156 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 156 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1536 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1536 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6613 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8613 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6613 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8613 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.515197 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.922414 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.541896 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993590 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993590 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995443 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.995443 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.515197 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.978500 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.622780 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.515197 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.978500 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.622780 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65696.213678 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72498.831776 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66455.410691 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63233.158927 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63233.158927 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65536.912752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65536.912752 # average overall miss latency +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 163 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 163 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6620 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2005 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8625 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6620 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2005 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8625 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.512538 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.922747 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.539515 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995452 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.995452 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.512538 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.978554 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.620870 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -730,166 +724,166 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3835 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1529 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3407 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1957 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5364 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3407 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1957 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5364 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180933000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25685000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206618000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1550155 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1550155 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77075500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77075500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180933000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 283693500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180933000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 283693500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922414 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.541896 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993590 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993590 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.622780 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.622780 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53106.251834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60011.682243 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53876.923077 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 430 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3823 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 163 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 163 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3393 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5355 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50409.090909 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50409.090909 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 54 # number of replacements -system.cpu.dcache.tags.tagsinuse 1431.071380 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66125331 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33112.334001 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 57 # number of replacements +system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071380 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349383 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349383 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45611085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45611085 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66125123 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66125123 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66125123 # number of overall hits -system.cpu.dcache.overall_hits::total 66125123 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 915 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 915 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1693 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1693 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2608 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2608 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2608 # number of overall misses -system.cpu.dcache.overall_misses::total 2608 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55175302 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55175302 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 106081155 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 106081155 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 161256457 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 161256457 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 161256457 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 161256457 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45612000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45612000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits +system.cpu.dcache.overall_hits::total 66102125 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses +system.cpu.dcache.overall_misses::total 2637 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66127731 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66127731 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66127731 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66127731 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60300.876503 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60300.876503 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62658.685765 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62658.685765 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61831.463574 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61831.463574 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 450 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 452 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 465 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1691 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1691 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2156 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2156 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2156 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2156 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31924750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31924750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101851095 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101851095 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133775845 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133775845 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133775845 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index b46274bd4..676e01409 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,133 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961841 # Number of seconds simulated -sim_ticks 1961841175000 # Number of ticks simulated -final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961837 # Number of seconds simulated +sim_ticks 1961837389000 # Number of ticks simulated +final_tick 1961837389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1272238 # Simulator instruction rate (inst/s) -host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42053157352 # Simulator tick rate (ticks/s) -host_mem_usage 308880 # Number of bytes of host memory used -host_seconds 46.65 # Real time elapsed on the host -sim_insts 59351715 # Number of instructions simulated -sim_ops 59351715 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24914752 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 32192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 287808 # Number of bytes read from this memory -system.physmem.bytes_read::total 28716928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 32192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7746368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7746368 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389293 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4497 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121037 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121037 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12699678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 146703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14637744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3948519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3948519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3948519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12699678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28716928 # Total number of bytes read from memory -system.physmem.bytesWritten 7746368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28019 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27836 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27466 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27826 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28236 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7314 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7222 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7890 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1961833946000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448702 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121037 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +host_inst_rate 1325125 # Simulator instruction rate (inst/s) +host_op_rate 1325124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42668778131 # Simulator tick rate (ticks/s) +host_mem_usage 308960 # Number of bytes of host memory used +host_seconds 45.98 # Real time elapsed on the host +sim_insts 60926932 # Number of instructions simulated +sim_ops 60926932 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 833280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 338432 # Number of bytes read from this memory +system.physmem.bytes_read::total 28741376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7742464 # Number of bytes written to this memory +system.physmem.bytes_written::total 7742464 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5288 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449084 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120976 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120976 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12685610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 172508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14650234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3946537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3946537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3946537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12685610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 172508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18596771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449084 # Number of read requests accepted +system.physmem.writeReqs 120976 # Number of write requests accepted +system.physmem.readBursts 449084 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120976 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28737920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3456 # Total number of bytes read from write queue +system.physmem.bytesWritten 7741568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28741376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7742464 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 54 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7077 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28167 # Per bank write bursts +system.physmem.perBankRdBursts::1 28458 # Per bank write bursts +system.physmem.perBankRdBursts::2 28055 # Per bank write bursts +system.physmem.perBankRdBursts::3 27665 # Per bank write bursts +system.physmem.perBankRdBursts::4 27762 # Per bank write bursts +system.physmem.perBankRdBursts::5 27792 # Per bank write bursts +system.physmem.perBankRdBursts::6 28261 # Per bank write bursts +system.physmem.perBankRdBursts::7 27879 # Per bank write bursts +system.physmem.perBankRdBursts::8 28077 # Per bank write bursts +system.physmem.perBankRdBursts::9 27735 # Per bank write bursts +system.physmem.perBankRdBursts::10 27671 # Per bank write bursts +system.physmem.perBankRdBursts::11 28135 # Per bank write bursts +system.physmem.perBankRdBursts::12 28173 # Per bank write bursts +system.physmem.perBankRdBursts::13 28505 # Per bank write bursts +system.physmem.perBankRdBursts::14 28655 # Per bank write bursts +system.physmem.perBankRdBursts::15 28040 # Per bank write bursts +system.physmem.perBankWrBursts::0 7931 # Per bank write bursts +system.physmem.perBankWrBursts::1 7869 # Per bank write bursts +system.physmem.perBankWrBursts::2 7539 # Per bank write bursts +system.physmem.perBankWrBursts::3 7157 # Per bank write bursts +system.physmem.perBankWrBursts::4 7275 # Per bank write bursts +system.physmem.perBankWrBursts::5 7313 # Per bank write bursts +system.physmem.perBankWrBursts::6 7748 # Per bank write bursts +system.physmem.perBankWrBursts::7 7258 # Per bank write bursts +system.physmem.perBankWrBursts::8 7316 # Per bank write bursts +system.physmem.perBankWrBursts::9 7114 # Per bank write bursts +system.physmem.perBankWrBursts::10 7078 # Per bank write bursts +system.physmem.perBankWrBursts::11 7523 # Per bank write bursts +system.physmem.perBankWrBursts::12 7676 # Per bank write bursts +system.physmem.perBankWrBursts::13 8141 # Per bank write bursts +system.physmem.perBankWrBursts::14 8336 # Per bank write bursts +system.physmem.perBankWrBursts::15 7688 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1961830378000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 449084 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 120976 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 409885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -139,382 +141,444 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 922.589599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.543369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2381.494153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13878 35.12% 35.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6056 15.33% 50.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3741 9.47% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2391 6.05% 65.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1744 4.41% 70.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1425 3.61% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1039 2.63% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 750 1.90% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 668 1.69% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 592 1.50% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 528 1.34% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 459 1.16% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 301 0.76% 84.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 245 0.62% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 187 0.47% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 264 0.67% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 137 0.35% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 111 0.28% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 92 0.23% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 96 0.24% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 88 0.22% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 105 0.27% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1100 2.78% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 187 0.47% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 132 0.33% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 88 0.22% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 54 0.14% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 43 0.11% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 23 0.06% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 21 0.05% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 20 0.05% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 29 0.07% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 11 0.03% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 14 0.04% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 4 0.01% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 6 0.02% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.00% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 4 0.01% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 3 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 2 0.01% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.01% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.01% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 6 0.02% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2432 6.15% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 3 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 242 0.61% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 10 0.03% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 6 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 6 0.02% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39515 # Bytes accessed per row activation -system.physmem.totQLat 3750140000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12006448750 # Sum of mem lat for all requests -system.physmem.totBusLat 2243145000 # Total cycles spent in databus access -system.physmem.totBankLat 6013163750 # Total cycles spent in bank access -system.physmem.avgQLat 8359.11 # Average queueing delay per request -system.physmem.avgBankLat 13403.42 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26762.53 # Average memory access latency -system.physmem.avgRdBW 14.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 49252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 740.628604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 223.502021 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1737.958624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 17638 35.81% 35.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7255 14.73% 50.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4934 10.02% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2938 5.97% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1843 3.74% 70.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1471 2.99% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1137 2.31% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 871 1.77% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 749 1.52% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 678 1.38% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 696 1.41% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 441 0.90% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 346 0.70% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 295 0.60% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 325 0.66% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 366 0.74% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 215 0.44% 85.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 196 0.40% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 200 0.41% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 126 0.26% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 182 0.37% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 862 1.75% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 228 0.46% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 113 0.23% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 126 0.26% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 100 0.20% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 86 0.17% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 47 0.10% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 73 0.15% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 75 0.15% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 79 0.16% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 32 0.06% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 84 0.17% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 62 0.13% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 61 0.12% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 26 0.05% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 60 0.12% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 59 0.12% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 68 0.14% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 29 0.06% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 67 0.14% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 63 0.13% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 57 0.12% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 25 0.05% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 61 0.12% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 59 0.12% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 69 0.14% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 25 0.05% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 65 0.13% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 58 0.12% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 65 0.13% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 25 0.05% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 59 0.12% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 71 0.14% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 22 0.04% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 70 0.14% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 53 0.11% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 60 0.12% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 27 0.05% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 61 0.12% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 53 0.11% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 63 0.13% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 34 0.07% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 63 0.13% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 57 0.12% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 62 0.13% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 28 0.06% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 58 0.12% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 54 0.11% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 66 0.13% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 361 0.73% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 57 0.12% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 23 0.05% 95.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 53 0.11% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 23 0.05% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 58 0.12% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 23 0.05% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 51 0.10% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 22 0.04% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 54 0.11% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 39 0.08% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 55 0.11% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.04% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 55 0.11% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 27 0.05% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 50 0.10% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 22 0.04% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 54 0.11% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 25 0.05% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 53 0.11% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 22 0.04% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 52 0.11% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 23 0.05% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 54 0.11% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 23 0.05% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 52 0.11% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 23 0.05% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 54 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 23 0.05% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 53 0.11% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 23 0.05% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 55 0.11% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 26 0.05% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 57 0.12% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 421 0.85% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 12 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 6 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 40 0.08% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 179 0.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49252 # Bytes accessed per row activation +system.physmem.totQLat 6314810500 # Total ticks spent queuing +system.physmem.totMemAccLat 14686644250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2245150000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6126683750 # Total ticks spent accessing banks +system.physmem.avgQLat 14063.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13644.26 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32707.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 6.90 # Average write queue length over time -system.physmem.readRowHits 433153 # Number of row buffer hits during reads -system.physmem.writeRowHits 96987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes -system.physmem.avgGap 3443390.65 # Average gap between requests -system.membus.throughput 18639952 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292620 # Transaction distribution -system.membus.trans_dist::ReadResp 292620 # Transaction distribution -system.membus.trans_dist::WriteReq 12397 # Transaction distribution -system.membus.trans_dist::WriteResp 12397 # Transaction distribution -system.membus.trans_dist::Writeback 121037 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4186 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 858 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3168 # Transaction distribution -system.membus.trans_dist::ReadExReq 163944 # Transaction distribution -system.membus.trans_dist::ReadExResp 163855 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36531890 # Total data (bytes) -system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39129000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing +system.physmem.readRowHits 424855 # Number of row buffer hits during reads +system.physmem.writeRowHits 95885 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.26 # Row buffer hit rate for writes +system.physmem.avgGap 3441445.42 # Average gap between requests +system.physmem.pageHitRate 91.36 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18657286 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292799 # Transaction distribution +system.membus.trans_dist::ReadResp 292799 # Transaction distribution +system.membus.trans_dist::WriteReq 14111 # Transaction distribution +system.membus.trans_dist::WriteResp 14111 # Transaction distribution +system.membus.trans_dist::Writeback 120976 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16467 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11554 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7080 # Transaction distribution +system.membus.trans_dist::ReadExReq 164905 # Transaction distribution +system.membus.trans_dist::ReadExResp 164053 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1098283 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82306 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31175680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31257986 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36566146 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36566146 # Total data (bytes) +system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43190000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1559666750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1566162500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3812357322 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3824002662 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376301000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 341780 # number of replacements -system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use -system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 28709 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1793292 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820882 # number of Writeback hits -system.l2c.Writeback_hits::total 820882 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 160 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 201 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 36 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 176285 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7535 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183820 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 908184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 953017 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 79667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 36244 # number of demand (read+write) hits -system.l2c.demand_hits::total 1977112 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 908184 # number of overall hits -system.l2c.overall_hits::cpu0.data 953017 # number of overall hits -system.l2c.overall_hits::cpu1.inst 79667 # number of overall hits -system.l2c.overall_hits::cpu1.data 36244 # number of overall hits -system.l2c.overall_hits::total 1977112 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12993 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271572 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 511 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 178 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2440 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2923 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 33 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 106 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 118111 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 4331 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122442 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12993 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389683 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 511 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 4509 # number of demand (read+write) misses -system.l2c.demand_misses::total 407696 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12993 # number of overall misses -system.l2c.overall_misses::cpu0.data 389683 # number of overall misses -system.l2c.overall_misses::cpu1.inst 511 # number of overall misses -system.l2c.overall_misses::cpu1.data 4509 # number of overall misses -system.l2c.overall_misses::total 407696 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1030661993 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16900238244 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 41124000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 15490750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17987514987 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1078963 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 302487 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1381450 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 69997 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 92496 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 162493 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7866556623 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 326108488 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8192665111 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1030661993 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 24766794867 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 41124000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 341599238 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 26180180098 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1030661993 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 24766794867 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 41124000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 341599238 # number of overall miss cycles -system.l2c.overall_miss_latency::total 26180180098 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 921177 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1048304 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 80178 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 28887 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2078546 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820882 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820882 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2600 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 524 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3124 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 51 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 91 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 142 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 294396 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 11866 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306262 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 921177 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1342700 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 80178 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 40753 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2384808 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 921177 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1342700 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 80178 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 40753 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2384808 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014105 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259058 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.006373 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006162 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137237 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938462 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.921756 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.935659 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.647059 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.802198 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.746479 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.401198 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.364992 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.399795 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014105 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290223 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006373 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.110642 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170955 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014105 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290223 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006373 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.110642 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170955 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79324.404910 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 62231.151385 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80477.495108 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 87026.685393 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 63057.888713 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 442.197951 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 626.267081 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 472.613753 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2121.121212 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1267.068493 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1532.952830 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66603.082041 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75296.349111 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 66910.578976 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 79324.404910 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 63556.262057 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80477.495108 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75759.422932 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64214.954520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 79324.404910 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 63556.262057 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80477.495108 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75759.422932 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64214.954520 # average overall miss latency +system.l2c.tags.replacements 342163 # number of replacements +system.l2c.tags.tagsinuse 65223.750612 # Cycle average of tags in use +system.l2c.tags.total_refs 2442870 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407350 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.996980 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8613125750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55316.946263 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4805.666179 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4897.139369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 159.783438 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 44.215363 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.844070 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073329 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.074724 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002438 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995235 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 684304 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 664415 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 317640 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 107160 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1773519 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 792069 # number of Writeback hits +system.l2c.Writeback_hits::total 792069 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 188 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 543 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 129070 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 43262 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172332 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 684304 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 793485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 317640 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 150422 # number of demand (read+write) hits +system.l2c.demand_hits::total 1945851 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 684304 # number of overall hits +system.l2c.overall_hits::cpu0.data 793485 # number of overall hits +system.l2c.overall_hits::cpu1.inst 317640 # number of overall hits +system.l2c.overall_hits::cpu1.data 150422 # number of overall hits +system.l2c.overall_hits::total 1945851 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13023 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271669 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 503 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 242 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285437 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2958 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1767 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4725 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 919 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 927 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1846 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 117954 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5056 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 123010 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13023 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 389623 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 503 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 5298 # number of demand (read+write) misses +system.l2c.demand_misses::total 408447 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13023 # number of overall misses +system.l2c.overall_misses::cpu0.data 389623 # number of overall misses +system.l2c.overall_misses::cpu1.inst 503 # number of overall misses +system.l2c.overall_misses::cpu1.data 5298 # number of overall misses +system.l2c.overall_misses::total 408447 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 996362741 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17553106248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 38541500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 19247750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18607258239 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1197458 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 10193060 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11390518 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 953959 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 139494 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1093453 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8253462501 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 385340740 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8638803241 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 996362741 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 25806568749 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 38541500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 404588490 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 27246061480 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 996362741 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 25806568749 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 38541500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 404588490 # number of overall miss cycles +system.l2c.overall_miss_latency::total 27246061480 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 697327 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 936084 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 318143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 107402 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2058956 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 792069 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 792069 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3146 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2310 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5456 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 956 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 949 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1905 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 247024 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 48318 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295342 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 697327 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1183108 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 318143 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 155720 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2354298 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 697327 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1183108 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 318143 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 155720 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2354298 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018676 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.290219 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001581 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002253 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138632 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940242 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764935 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.866019 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961297 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976818 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969029 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.477500 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.104640 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.416500 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018676 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.329322 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001581 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.034023 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173490 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018676 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.329322 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001581 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.034023 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173490 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76507.927590 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 64612.106085 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76623.260437 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 79536.157025 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 65188.669440 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 404.820149 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5768.568195 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2410.691640 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1038.040261 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 150.478964 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 592.336403 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69971.874638 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76214.545095 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 70228.463060 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76507.927590 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 66234.715992 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76623.260437 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76366.268403 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 66706.479617 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76507.927590 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 66234.715992 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76623.260437 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76366.268403 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 66706.479617 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,8 +587,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79517 # number of writebacks -system.l2c.writebacks::total 79517 # number of writebacks +system.l2c.writebacks::writebacks 79456 # number of writebacks +system.l2c.writebacks::total 79456 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits @@ -534,111 +598,111 @@ system.l2c.demand_mshr_hits::total 11 # nu system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12990 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271572 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 503 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 178 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285243 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2440 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 33 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 106 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 118111 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 4331 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122442 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12990 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 389683 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 503 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 4509 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407685 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12990 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 389683 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 503 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 4509 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407685 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 866381257 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13503893756 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 34165000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13232750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 14417672763 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24556937 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4864483 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29421420 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 330033 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1060106 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6385916377 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 270944012 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6656860389 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 866381257 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 19889810133 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 34165000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 284176762 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 21074533152 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 866381257 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 19889810133 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 34165000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 284176762 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 21074533152 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373141500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17611000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1390752500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1974248000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 499178500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2473426500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3347389500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 516789500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3864179000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259058 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006162 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.137232 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938462 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.921756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.935659 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.647059 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.802198 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401198 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.364992 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.399795 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290223 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.110642 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.170951 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290223 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.110642 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.170951 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49724.911832 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74341.292135 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 50545.229026 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.318443 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10071.393375 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10065.487513 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13020 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271669 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 495 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 242 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285426 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2958 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1767 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4725 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 919 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 927 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1846 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 117954 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5056 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 123010 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13020 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389623 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 495 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 5298 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408436 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13020 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389623 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 495 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 5298 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408436 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 832352009 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14156448252 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31778000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 16225250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15036803511 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29732955 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17692267 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47425222 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9190919 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9270927 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 18461846 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6776581499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 321158260 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7097739759 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 832352009 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 20933029751 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 31778000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 337383510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22134543270 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 832352009 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 20933029751 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 31778000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 337383510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22134543270 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373137500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17612000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1390749500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154547500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 679451000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2833998500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527685000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 697063000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4224748000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290219 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002253 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138627 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940242 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764935 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.866019 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961297 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969029 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477500 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.104640 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.416500 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.329322 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.034023 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173485 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.329322 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.034023 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173485 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52109.177904 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67046.487603 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52681.968395 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.708925 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.601585 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.084021 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54067.075692 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62559.226968 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 54367.458789 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57451.052944 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63520.225475 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57700.510194 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -649,39 +713,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.571330 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.tags.warmup_cycle 1754532770000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.571330 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035708 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035708 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21912883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21912883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10439154521 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10439154521 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10461067404 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10461067404 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10461067404 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10461067404 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12952701816 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12952701816 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12973950199 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12973950199 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12973950199 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12973950199 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -690,40 +754,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123106.084270 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123106.084270 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251231.096482 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251231.096482 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250684.577139 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250684.577139 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 274830 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 311722.704467 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 311722.704467 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 310932.037555 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 310932.037555 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 405757 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27442 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29467 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.014941 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.769878 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12655383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12655383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8277077521 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8277077521 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8289732904 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8289732904 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8289732904 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8289732904 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10790464816 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10790464816 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10802664199 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10802664199 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10802664199 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10802664199 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -732,14 +796,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71097.657303 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71097.657303 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199198.053547 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199198.053547 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 259685.810936 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 259685.810936 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -757,22 +821,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8725663 # DTB read hits +system.cpu0.dtb.read_hits 7530179 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 6139453 # DTB write hits +system.cpu0.dtb.write_hits 5118893 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 14865116 # DTB hits +system.cpu0.dtb.data_hits 12649072 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 4015307 # ITB hits +system.cpu0.itb.fetch_hits 3650586 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 4019291 # ITB accesses +system.cpu0.itb.fetch_accesses 3654570 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -785,55 +849,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923682350 # number of cpu cycles simulated +system.cpu0.numCycles 3923674778 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54601969 # Number of instructions committed -system.cpu0.committedOps 54601969 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50544405 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 297630 # Number of float alu accesses -system.cpu0.num_func_calls 1438477 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6291508 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50544405 # number of integer instructions -system.cpu0.num_fp_insts 297630 # number of float instructions -system.cpu0.num_int_register_reads 69247284 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37427910 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 145753 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 148838 # number of times the floating registers were written -system.cpu0.num_mem_refs 14912078 # number of memory refs -system.cpu0.num_load_insts 8757685 # Number of load instructions -system.cpu0.num_store_insts 6154393 # Number of store instructions -system.cpu0.num_idle_cycles 3674902109.498127 # Number of idle cycles -system.cpu0.num_busy_cycles 248780240.501873 # Number of busy cycles -system.cpu0.not_idle_fraction 0.063405 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.936595 # Percentage of idle cycles +system.cpu0.committedInsts 47959136 # Number of instructions committed +system.cpu0.committedOps 47959136 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44491652 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211334 # Number of float alu accesses +system.cpu0.num_func_calls 1203195 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5632072 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44491652 # number of integer instructions +system.cpu0.num_fp_insts 211334 # number of float instructions +system.cpu0.num_int_register_reads 61191395 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33136181 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 103249 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 105046 # number of times the floating registers were written +system.cpu0.num_mem_refs 12690027 # number of memory refs +system.cpu0.num_load_insts 7557911 # Number of load instructions +system.cpu0.num_store_insts 5132116 # Number of store instructions +system.cpu0.num_idle_cycles 3700191977.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223482800.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.056958 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.943042 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 204697 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 73289 40.68% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104766 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 180167 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71920 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.35% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71914 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 145946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899196330000 96.81% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95025500 0.00% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 769055500 0.04% 96.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5164500 0.00% 96.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 61774827500 3.15% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961840403000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981321 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6812 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165228 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56779 40.23% 40.23% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.40% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81809 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141128 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56269 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55834 48.70% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114643 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902446374500 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95095000 0.00% 96.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 766988500 0.04% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 322426000 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58205747500 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961836631500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991018 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.686425 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810060 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682492 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812333 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -865,37 +929,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3942 2.08% 2.13% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.16% # number of callpals executed -system.cpu0.kern.callpal::swpipl 173212 91.45% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 6702 3.54% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rti 4842 2.56% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 189397 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7440 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches +system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3084 2.06% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134176 89.75% 92.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.48% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rti 4411 2.95% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149500 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7010 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1368 -system.cpu0.kern.mode_good::user 1369 +system.cpu0.kern.mode_good::kernel 1372 +system.cpu0.kern.mode_good::user 1373 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.183871 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195720 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.310705 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958025785500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3814613000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327448 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958037655500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3798971500 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3943 # number of times the context was actually changed +system.cpu0.kern.swap_context 3085 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -927,47 +991,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 105075557 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2099191 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2099176 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12397 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12397 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 820882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4248 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 894 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 205232754 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.throughput 103908079 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2101783 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101768 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14111 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14111 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792069 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16689 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11613 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28302 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 338794 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297244 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1394675 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121086 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 636287 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 464415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5616463 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44628928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119461456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20361152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17008562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201460098 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201449794 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2400960 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4792055385 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4148559004 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3140628756 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 6195378103 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5519397625 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 360929992 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 206344318 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1431747492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 796288703 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1391673 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 53949 # Transaction distribution -system.iobus.trans_dist::WriteResp 53949 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1398649 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55663 # Transaction distribution +system.iobus.trans_dist::WriteResp 55663 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -979,11 +1043,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42620 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126072 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56040 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -995,12 +1059,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2730242 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 82306 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2743922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743922 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13365000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1022,59 +1086,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378297154 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377760199 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26795000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42664000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 920572 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53689788 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53689788 # number of overall hits -system.cpu0.icache.overall_hits::total 53689788 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 921200 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 921200 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 921200 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 921200 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 921200 # number of overall misses -system.cpu0.icache.overall_misses::total 921200 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12937764004 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12937764004 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12937764004 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12937764004 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12937764004 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12937764004 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54610988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54610988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54610988 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54610988 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54610988 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54610988 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016868 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016868 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016868 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016868 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016868 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016868 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14044.468089 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14044.468089 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14044.468089 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14044.468089 # average overall miss latency +system.cpu0.icache.tags.replacements 696718 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.401211 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47270807 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 697230 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.798011 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40083254250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.401211 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992971 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992971 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47270807 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47270807 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47270807 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47270807 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47270807 # number of overall hits +system.cpu0.icache.overall_hits::total 47270807 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 697348 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 697348 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 697348 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 697348 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 697348 # number of overall misses +system.cpu0.icache.overall_misses::total 697348 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9977651756 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9977651756 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9977651756 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9977651756 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9977651756 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9977651756 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47968155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47968155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47968155 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47968155 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47968155 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47968155 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014538 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014538 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014538 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014538 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014538 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014538 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14307.995084 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14307.995084 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14307.995084 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14307.995084 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1083,112 +1147,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 921200 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 921200 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 921200 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 921200 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 921200 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 921200 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11089045996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11089045996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11089045996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11089045996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11089045996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11089045996 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016868 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016868 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016868 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12037.609635 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697348 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 697348 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 697348 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 697348 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 697348 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 697348 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8577830244 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8577830244 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8577830244 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8577830244 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8577830244 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8577830244 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014538 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014538 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014538 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12300.645078 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1349865 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5646858 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177791 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177791 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 193304 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 193304 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 13154053 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13154053 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 13154053 # number of overall hits -system.cpu0.dcache.overall_hits::total 13154053 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1040730 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1040730 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297940 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297940 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16884 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16884 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 399 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 399 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1338670 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1338670 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1338670 # number of overall misses -system.cpu0.dcache.overall_misses::total 1338670 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27787431256 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27787431256 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10644315314 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10644315314 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 223091000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 223091000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2495533 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2495533 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38431746570 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38431746570 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38431746570 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38431746570 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8547925 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8547925 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5944798 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5944798 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194675 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194675 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193703 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 193703 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14492723 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14492723 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14492723 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14492723 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.121752 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.121752 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050118 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.050118 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086729 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086729 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092368 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092368 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092368 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092368 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26699.942594 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26699.942594 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35726.372135 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35726.372135 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13213.160389 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13213.160389 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6254.468672 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6254.468672 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28708.902545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 28708.902545 # average overall miss latency +system.cpu0.dcache.tags.replacements 1186136 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.274988 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11457169 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1186648 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.655070 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 107469250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.274988 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986865 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6449366 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6449366 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4705451 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4705451 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140478 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140478 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147984 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147984 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11154817 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11154817 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11154817 # number of overall hits +system.cpu0.dcache.overall_hits::total 11154817 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 939343 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 939343 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 256772 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 256772 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13639 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13639 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5591 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5591 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1196115 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1196115 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1196115 # number of overall misses +system.cpu0.dcache.overall_misses::total 1196115 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27074316502 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27074316502 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10448735954 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10448735954 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148878750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 148878750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43336419 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 43336419 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37523052456 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37523052456 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37523052456 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37523052456 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7388709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7388709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4962223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4962223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153575 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153575 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12350932 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12350932 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12350932 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12350932 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127132 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127132 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051745 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051745 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036406 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036406 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096844 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096844 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096844 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096844 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28822.609528 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28822.609528 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40692.661014 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40692.661014 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10915.664638 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10915.664638 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7751.103380 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7751.103380 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31370.773258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31370.773258 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1197,62 +1261,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 798646 # number of writebacks -system.cpu0.dcache.writebacks::total 798646 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1040730 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1040730 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297940 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297940 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16884 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16884 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1338670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1338670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1338670 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1338670 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25571734744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25571734744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9990567686 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9990567686 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 189290000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 189290000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1697467 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1697467 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35562302430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35562302430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35562302430 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35562302430 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2094321000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2094321000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3559901500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3559901500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121752 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121752 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086729 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086729 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092368 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092368 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24570.959561 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24570.959561 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33532.146358 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33532.146358 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11211.205875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11211.205875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4254.303258 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4254.303258 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 682430 # number of writebacks +system.cpu0.dcache.writebacks::total 682430 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939343 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939343 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256772 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256772 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13639 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13639 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5590 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5590 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1196115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196115 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1196115 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25063726498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25063726498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9880374046 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9880374046 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121588250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121588250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32154581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32154581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34944100544 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34944100544 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34944100544 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34944100544 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465575000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465575000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284904500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284904500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750479500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750479500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096844 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096844 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26682.187974 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26682.187974 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38479.172363 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38479.172363 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8914.748149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8914.748149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5752.161181 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5752.161181 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1264,22 +1328,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 957039 # DTB read hits +system.cpu1.dtb.read_hits 2385380 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 556340 # DTB write hits +system.cpu1.dtb.write_hits 1707840 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 1513379 # DTB hits +system.cpu1.dtb.data_hits 4093220 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1320031 # ITB hits +system.cpu1.itb.fetch_hits 1814538 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1321095 # ITB accesses +system.cpu1.itb.fetch_accesses 1815602 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1292,51 +1356,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921887017 # number of cpu cycles simulated +system.cpu1.numCycles 3921880904 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 4749746 # Number of instructions committed -system.cpu1.committedOps 4749746 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4446088 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 30301 # Number of float alu accesses -system.cpu1.num_func_calls 145582 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 455512 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4446088 # number of integer instructions -system.cpu1.num_fp_insts 30301 # number of float instructions -system.cpu1.num_int_register_reads 6169769 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3384887 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 19629 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 19442 # number of times the floating registers were written -system.cpu1.num_mem_refs 1521715 # number of memory refs -system.cpu1.num_load_insts 962201 # Number of load instructions -system.cpu1.num_store_insts 559514 # Number of store instructions -system.cpu1.num_idle_cycles 3904242469.193159 # Number of idle cycles -system.cpu1.num_busy_cycles 17644547.806841 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004499 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995501 # Percentage of idle cycles +system.cpu1.committedInsts 12967796 # Number of instructions committed +system.cpu1.committedOps 12967796 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11946960 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses +system.cpu1.num_func_calls 410982 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1284197 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11946960 # number of integer instructions +system.cpu1.num_fp_insts 174217 # number of float instructions +system.cpu1.num_int_register_reads 16422187 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8787604 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written +system.cpu1.num_mem_refs 4116157 # number of memory refs +system.cpu1.num_load_insts 2399132 # Number of load instructions +system.cpu1.num_store_insts 1717025 # Number of store instructions +system.cpu1.num_idle_cycles 3872385828.119347 # Number of idle cycles +system.cpu1.num_busy_cycles 49495075.880653 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012620 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987380 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2329 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 33659 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8392 30.97% 30.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 7.27% 38.24% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.32% 38.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 16645 61.43% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 27095 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8384 44.74% 44.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 10.51% 55.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.47% 55.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8296 44.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 18738 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917649813500 97.79% 97.79% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700167000 0.04% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 60318500 0.00% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42533179500 2.17% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960943478500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999047 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2742 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78306 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26634 38.27% 38.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40476 58.16% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69596 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25767 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25250 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53503 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909643308000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700945000 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 361639500 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50234529500 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940422000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967448 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.498408 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.691567 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.623826 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.768765 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1352,81 +1416,81 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 283 1.02% 1.06% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.07% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.03% 1.09% # number of callpals executed -system.cpu1.kern.callpal::swpipl 22604 81.73% 82.82% # number of callpals executed -system.cpu1.kern.callpal::rdps 2147 7.76% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.60% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.61% # number of callpals executed -system.cpu1.kern.callpal::rti 2432 8.79% 99.41% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.44% 99.84% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.78% 3.39% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63390 88.19% 91.60% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 2.99% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::rti 3719 5.17% 99.77% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 27656 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 652 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 379 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 12 -system.cpu1.kern.mode_switch_good::kernel 0.581288 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71875 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2907 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 809 +system.cpu1.kern.mode_good::user 368 +system.cpu1.kern.mode_good::idle 441 +system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.005811 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.245785 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 284 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 79630 # number of replacements -system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 4672446 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 4672446 # number of overall hits -system.cpu1.icache.overall_hits::total 4672446 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 80179 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 80179 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 80179 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 80179 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 80179 # number of overall misses -system.cpu1.icache.overall_misses::total 80179 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1082064992 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1082064992 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1082064992 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1082064992 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1082064992 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1082064992 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 4752625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 4752625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 4752625 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 4752625 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 4752625 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 4752625 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016870 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016870 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016870 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016870 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016870 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016870 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13495.615959 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13495.615959 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13495.615959 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13495.615959 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.151703 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309310 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17986321500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1483696000 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1940592550000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2002 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 317593 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.454785 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12652531 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318104 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.774825 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1959964216000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.454785 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871982 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871982 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12652531 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12652531 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12652531 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12652531 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12652531 # number of overall hits +system.cpu1.icache.overall_hits::total 12652531 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318144 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318144 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318144 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318144 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318144 # number of overall misses +system.cpu1.icache.overall_misses::total 318144 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4187615492 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4187615492 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4187615492 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4187615492 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4187615492 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4187615492 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12970675 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12970675 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12970675 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12970675 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12970675 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12970675 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024528 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024528 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024528 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024528 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.641735 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13162.641735 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13162.641735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13162.641735 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1435,112 +1499,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 80179 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 80179 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 80179 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 80179 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 80179 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 80179 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 921458008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 921458008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 921458008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 921458008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 921458008 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 921458008 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016870 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016870 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11492.510608 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318144 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 318144 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318144 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318144 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318144 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3551128508 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3551128508 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3551128508 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3551128508 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3551128508 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3551128508 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024528 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024528 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024528 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11162.016282 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11162.016282 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11162.016282 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 40890 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 531046 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 9250 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 9250 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 9554 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 9554 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1448467 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1448467 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1448467 # number of overall hits -system.cpu1.dcache.overall_hits::total 1448467 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 31971 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 31971 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 13337 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 13337 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 850 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 850 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 495 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 495 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 45308 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 45308 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 45308 # number of overall misses -system.cpu1.dcache.overall_misses::total 45308 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 398942000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 398942000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 455916495 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 455916495 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 9380250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 9380250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3699073 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3699073 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 854858495 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 854858495 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 854858495 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 854858495 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 949392 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 949392 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 544383 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 544383 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 10100 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 10100 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 10049 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 10049 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1493775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1493775 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1493775 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1493775 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033675 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.033675 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.024499 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.024499 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.049259 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.049259 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030331 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.030331 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030331 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030331 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12478.245910 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12478.245910 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34184.336432 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34184.336432 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11035.588235 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11035.588235 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7472.874747 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7472.874747 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18867.716408 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18867.716408 # average overall miss latency +system.cpu1.dcache.tags.replacements 159205 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.204508 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3919863 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 159531 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.571168 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048842695500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.204508 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949618 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949618 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2222453 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2222453 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1596000 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1596000 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48034 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48034 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50617 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50617 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3818453 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3818453 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3818453 # number of overall hits +system.cpu1.dcache.overall_hits::total 3818453 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 116850 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 116850 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 57159 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 57159 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9086 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9086 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6023 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6023 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 174009 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 174009 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 174009 # number of overall misses +system.cpu1.dcache.overall_misses::total 174009 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1411488249 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1411488249 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1045308027 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1045308027 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82519500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 82519500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44276427 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 44276427 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2456796276 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2456796276 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2456796276 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2456796276 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2339303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2339303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1653159 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1653159 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57120 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57120 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56640 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56640 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3992462 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3992462 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3992462 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3992462 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049951 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049951 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034576 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034576 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159069 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159069 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106338 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106338 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043584 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043584 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043584 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043584 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12079.488652 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12079.488652 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18287.724190 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18287.724190 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9082.049307 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9082.049307 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7351.224805 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7351.224805 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14118.788545 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14118.788545 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14118.788545 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14118.788545 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1549,62 +1613,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 22236 # number of writebacks -system.cpu1.dcache.writebacks::total 22236 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 31971 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 31971 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 13337 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 13337 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 850 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 850 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 495 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 45308 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 45308 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 45308 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 45308 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 334917000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 334917000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 427133505 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 427133505 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 7677750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 7677750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2708927 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2708927 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 762050505 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 762050505 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 762050505 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 762050505 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 527878500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 527878500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 546646500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 546646500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033675 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033675 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024499 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.024499 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.084158 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.084158 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.049259 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030331 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030331 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10475.649808 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10475.649808 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32026.205668 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32026.205668 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.647059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9032.647059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.579798 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5472.579798 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 109639 # number of writebacks +system.cpu1.dcache.writebacks::total 109639 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116850 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116850 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57159 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57159 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9086 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9086 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6023 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6023 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 174009 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 174009 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 174009 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 174009 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1177711751 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1177711751 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 928682973 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 928682973 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64347500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64347500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32228573 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32228573 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2106394724 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2106394724 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2106394724 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2106394724 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18769000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18769000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718428000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718428000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737197000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737197000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034576 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034576 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159069 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159069 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106338 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106338 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043584 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043584 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10078.833984 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10078.833984 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16247.362148 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16247.362148 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7082.049307 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7082.049307 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5350.916985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5350.916985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 0de871519..479e1f707 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,123 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.918473 # Number of seconds simulated -sim_ticks 1918473094000 # Number of ticks simulated -final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920428 # Number of seconds simulated +sim_ticks 1920428041000 # Number of ticks simulated +final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 948634 # Simulator instruction rate (inst/s) -host_op_rate 948634 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32389976926 # Simulator tick rate (ticks/s) -host_mem_usage 304780 # Number of bytes of host memory used -host_seconds 59.23 # Real time elapsed on the host -sim_insts 56188014 # Number of instructions simulated -sim_ops 56188014 # Number of ops (including micro ops) simulated +host_inst_rate 1218375 # Simulator instruction rate (inst/s) +host_op_rate 1218374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41646226437 # Simulator tick rate (ticks/s) +host_mem_usage 305884 # Number of bytes of host memory used +host_seconds 46.11 # Real time elapsed on the host +sim_insts 56182750 # Number of instructions simulated +sim_ops 56182750 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory +system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory +system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28350528 # Total number of bytes read from memory -system.physmem.bytesWritten 7389888 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1918461222000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442977 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 115467 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442968 # Number of read requests accepted +system.physmem.writeReqs 115466 # Number of write requests accepted +system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue +system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 27966 # Per bank write bursts +system.physmem.perBankRdBursts::1 28089 # Per bank write bursts +system.physmem.perBankRdBursts::2 28297 # Per bank write bursts +system.physmem.perBankRdBursts::3 28053 # Per bank write bursts +system.physmem.perBankRdBursts::4 27407 # Per bank write bursts +system.physmem.perBankRdBursts::5 27545 # Per bank write bursts +system.physmem.perBankRdBursts::6 26911 # Per bank write bursts +system.physmem.perBankRdBursts::7 26762 # Per bank write bursts +system.physmem.perBankRdBursts::8 27807 # Per bank write bursts +system.physmem.perBankRdBursts::9 27255 # Per bank write bursts +system.physmem.perBankRdBursts::10 27714 # Per bank write bursts +system.physmem.perBankRdBursts::11 27327 # Per bank write bursts +system.physmem.perBankRdBursts::12 27431 # Per bank write bursts +system.physmem.perBankRdBursts::13 28073 # Per bank write bursts +system.physmem.perBankRdBursts::14 28024 # Per bank write bursts +system.physmem.perBankRdBursts::15 28256 # Per bank write bursts +system.physmem.perBankWrBursts::0 7722 # Per bank write bursts +system.physmem.perBankWrBursts::1 7593 # Per bank write bursts +system.physmem.perBankWrBursts::2 7833 # Per bank write bursts +system.physmem.perBankWrBursts::3 7543 # Per bank write bursts +system.physmem.perBankWrBursts::4 7010 # Per bank write bursts +system.physmem.perBankWrBursts::5 6982 # Per bank write bursts +system.physmem.perBankWrBursts::6 6469 # Per bank write bursts +system.physmem.perBankWrBursts::7 6223 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts +system.physmem.perBankWrBursts::9 6661 # Per bank write bursts +system.physmem.perBankWrBursts::10 7099 # Per bank write bursts +system.physmem.perBankWrBursts::11 6780 # Per bank write bursts +system.physmem.perBankWrBursts::12 7009 # Per bank write bursts +system.physmem.perBankWrBursts::13 7722 # Per bank write bursts +system.physmem.perBankWrBursts::14 7773 # Per bank write bursts +system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1920416169000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 442968 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 115466 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -129,233 +131,289 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation -system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests -system.physmem.totBusLat 2214635000 # Total cycles spent in databus access -system.physmem.totBankLat 5924943750 # Total cycles spent in bank access -system.physmem.avgQLat 8261.25 # Average queueing delay per request -system.physmem.avgBankLat 13376.80 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26638.04 # Average memory access latency -system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation +system.physmem.totQLat 6257775000 # Total ticks spent queuing +system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks +system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 13.19 # Average write queue length over time -system.physmem.readRowHits 427838 # Number of row buffer hits during reads -system.physmem.writeRowHits 93417 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes -system.physmem.avgGap 3435369.03 # Average gap between requests -system.membus.throughput 18671288 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292313 # Transaction distribution -system.membus.trans_dist::ReadResp 292313 # Transaction distribution -system.membus.trans_dist::WriteReq 9649 # Transaction distribution -system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115467 # Transaction distribution +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing +system.physmem.readRowHits 419360 # Number of row buffer hits during reads +system.physmem.writeRowHits 92763 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes +system.physmem.avgGap 3438931.31 # Average gap between requests +system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18651952 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292310 # Transaction distribution +system.membus.trans_dist::ReadResp 292310 # Transaction distribution +system.membus.trans_dist::WriteReq 9650 # Transaction distribution +system.membus.trans_dist::WriteResp 9650 # Transaction distribution +system.membus.trans_dist::Writeback 115466 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158147 # Transaction distribution -system.membus.trans_dist::ReadExResp 158147 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 158141 # Transaction distribution +system.membus.trans_dist::ReadExResp 158141 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35784972 # Total data (bytes) +system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35784340 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -364,14 +422,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -388,19 +446,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -414,14 +472,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +488,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +513,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9065600 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9064966 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6356756 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6356267 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15422356 # DTB hits -system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15421233 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974352 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973920 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979362 # ITB accesses +system.cpu.itb.fetch_accesses 4978917 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -483,51 +541,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3836946188 # number of cpu cycles simulated +system.cpu.numCycles 3840856082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56188014 # Number of instructions committed -system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1483456 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls -system.cpu.num_int_insts 52059797 # number of integer instructions -system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read -system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15474978 # number of memory refs -system.cpu.num_load_insts 9102456 # Number of load instructions -system.cpu.num_store_insts 6372522 # Number of store instructions -system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles -system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles -system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934855 # Percentage of idle cycles +system.cpu.committedInsts 56182750 # Number of instructions committed +system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses +system.cpu.num_func_calls 1483342 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054772 # number of integer instructions +system.cpu.num_fp_insts 324326 # number of float instructions +system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read +system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written +system.cpu.num_mem_refs 15473812 # number of memory refs +system.cpu.num_load_insts 9101789 # Number of load instructions +system.cpu.num_store_insts 6372023 # Number of store instructions +system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934400 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -563,33 +621,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192891 # number of callpals executed +system.cpu.kern.callpal::total 192898 # number of callpals executed system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4176 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -621,12 +679,12 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1410582 # Throughput (bytes/s) +system.iobus.throughput 1409150 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51201 # Transaction distribution -system.iobus.trans_dist::WriteResp 51201 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51202 # Transaction distribution +system.iobus.trans_dist::WriteResp 51202 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -638,11 +696,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -654,12 +712,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2706164 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2706172 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -681,59 +739,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928665 # number of replacements -system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits -system.cpu.icache.overall_hits::total 55270512 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses -system.cpu.icache.overall_misses::total 929336 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency +system.cpu.icache.tags.replacements 928358 # number of replacements +system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits +system.cpu.icache.overall_hits::total 55265541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses +system.cpu.icache.overall_misses::total 929029 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,126 +800,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929336 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929336 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11150220743 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11150220743 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11150220743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11150220743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11150220743 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11150220743 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016536 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016536 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016536 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.051020 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.051020 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336065 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 835407 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 835407 # number of Writeback hits +system.cpu.l2cache.tags.replacements 336056 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65296.863719 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2447536 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401218 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.100265 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6747777750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55582.845445 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4758.900638 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4955.117636 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072615 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075609 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996351 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 915717 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 814814 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1730531 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 835114 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 835114 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187779 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187779 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916024 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002748 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918772 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916024 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002748 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918772 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187645 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187645 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915717 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002459 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918176 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915717 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002459 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918176 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271918 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285210 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271915 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285207 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116714 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116708 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116708 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388632 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 401924 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388623 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 401915 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388632 # number of overall misses -system.cpu.l2cache.overall_misses::total 401924 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1060624743 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16925556244 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17986180987 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 388623 # number of overall misses +system.cpu.l2cache.overall_misses::total 401915 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1012336742 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17564329991 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18576666733 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7757662128 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7757662128 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1060624743 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24683218372 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25743843115 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1060624743 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24683218372 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25743843115 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 929316 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1086887 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2016203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 835407 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 835407 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8190852374 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8190852374 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1012336742 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 25755182365 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26767519107 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1012336742 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 25755182365 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26767519107 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 929009 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1086729 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2015738 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 835114 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 835114 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304493 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304493 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929316 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391380 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320696 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929316 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391380 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320696 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014303 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250181 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141459 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304353 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304353 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929009 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391082 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320091 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929009 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391082 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320091 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014308 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250214 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141490 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383306 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383306 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014303 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279314 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173191 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014303 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279314 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173191 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79794.217800 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62245.074780 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 63062.939543 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014308 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279367 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173232 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014308 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279367 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173232 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76161.355853 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.928529 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65133.978945 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66467.280086 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66467.280086 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 64051.519976 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 64051.519976 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70182.441426 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70182.441426 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66599.950504 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66599.950504 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,66 +928,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 73955 # number of writebacks -system.cpu.l2cache.writebacks::total 73955 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 73954 # number of writebacks +system.cpu.l2cache.writebacks::total 73954 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271918 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285210 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116708 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116708 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388632 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401924 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388623 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401915 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388632 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401924 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 893093257 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13525299756 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14418393013 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 388623 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401915 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 845706258 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14164824509 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15010530767 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6297401372 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6297401372 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 893093257 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19822701128 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20715794385 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 893093257 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19822701128 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20715794385 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334143500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334143500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229575000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229575000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6731491626 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6731491626 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 845706258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20896316135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21742022393 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 845706258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20896316135 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21742022393 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895642000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895642000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250214 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141490 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383306 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383306 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173191 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173191 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173232 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173232 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63625.207493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52092.839707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52630.302787 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53955.835392 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53955.835392 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57678.065137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -937,79 +995,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390866 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1390568 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14049173 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391080 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099472 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 107298250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978915 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852671 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183038 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183038 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13667738 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13667738 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13667738 # number of overall hits -system.cpu.dcache.overall_hits::total 13667738 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069668 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069668 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304510 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304510 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17219 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17219 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374178 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374178 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374178 # number of overall misses -system.cpu.dcache.overall_misses::total 1374178 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28240934256 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28240934256 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10606589383 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10606589383 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229410500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 229410500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38847523639 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38847523639 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38847523639 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38847523639 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8884735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8884735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157181 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157181 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15041916 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15041916 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15041916 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15041916 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120394 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120394 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085985 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085985 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091357 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091357 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091357 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091357 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26401.588396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26401.588396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34831.661959 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34831.661959 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13323.102387 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13323.102387 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28269.644572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28269.644572 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852326 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182986 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182986 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199222 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199222 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13666948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666948 # number of overall hits +system.cpu.dcache.overall_hits::total 13666948 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069470 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069470 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17259 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373840 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373840 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373840 # number of overall misses +system.cpu.dcache.overall_misses::total 1373840 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28875755759 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28875755759 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11035273137 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11035273137 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228925250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228925250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39911028896 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39911028896 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39911028896 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39911028896 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8884092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8884092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156696 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156696 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199222 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199222 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15040788 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15040788 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15040788 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15040788 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1018,54 +1076,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks -system.cpu.dcache.writebacks::total 835407 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks +system.cpu.dcache.writebacks::total 835114 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,31 +1131,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution +system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 643b5e070..951921c42 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,148 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194884 # Number of seconds simulated -sim_ticks 1194883580500 # Number of ticks simulated -final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.195756 # Number of seconds simulated +sim_ticks 1195756323500 # Number of ticks simulated +final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 298011 # Simulator instruction rate (inst/s) -host_op_rate 379758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5802481089 # Simulator tick rate (ticks/s) -host_mem_usage 399660 # Number of bytes of host memory used -host_seconds 205.93 # Real time elapsed on the host -sim_insts 61368273 # Number of instructions simulated -sim_ops 78202205 # Number of ops (including micro ops) simulated +host_inst_rate 469394 # Simulator instruction rate (inst/s) +host_op_rate 598174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9145402965 # Simulator tick rate (ticks/s) +host_mem_usage 398732 # Number of bytes of host memory used +host_seconds 130.75 # Real time elapsed on the host +sim_insts 61373013 # Number of instructions simulated +sim_ops 78210923 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory +system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory +system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 425896384 # Total number of bytes read from memory -system.physmem.bytesWritten 52573888 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1194879167500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6825 # Categorize read packet sizes -system.physmem.readPktSize::3 6488064 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159742 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64631 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654771 # Number of read requests accepted +system.physmem.writeReqs 821574 # Number of write requests accepted +system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415729 # Per bank write bursts +system.physmem.perBankRdBursts::1 415559 # Per bank write bursts +system.physmem.perBankRdBursts::2 414962 # Per bank write bursts +system.physmem.perBankRdBursts::3 415336 # Per bank write bursts +system.physmem.perBankRdBursts::4 422370 # Per bank write bursts +system.physmem.perBankRdBursts::5 415375 # Per bank write bursts +system.physmem.perBankRdBursts::6 415451 # Per bank write bursts +system.physmem.perBankRdBursts::7 415289 # Per bank write bursts +system.physmem.perBankRdBursts::8 415350 # Per bank write bursts +system.physmem.perBankRdBursts::9 415631 # Per bank write bursts +system.physmem.perBankRdBursts::10 415265 # Per bank write bursts +system.physmem.perBankRdBursts::11 414898 # Per bank write bursts +system.physmem.perBankRdBursts::12 415464 # Per bank write bursts +system.physmem.perBankRdBursts::13 416088 # Per bank write bursts +system.physmem.perBankRdBursts::14 415829 # Per bank write bursts +system.physmem.perBankRdBursts::15 415792 # Per bank write bursts +system.physmem.perBankWrBursts::0 7314 # Per bank write bursts +system.physmem.perBankWrBursts::1 7200 # Per bank write bursts +system.physmem.perBankWrBursts::2 6696 # Per bank write bursts +system.physmem.perBankWrBursts::3 6864 # Per bank write bursts +system.physmem.perBankWrBursts::4 7395 # Per bank write bursts +system.physmem.perBankWrBursts::5 6961 # Per bank write bursts +system.physmem.perBankWrBursts::6 7170 # Per bank write bursts +system.physmem.perBankWrBursts::7 6990 # Per bank write bursts +system.physmem.perBankWrBursts::8 6985 # Per bank write bursts +system.physmem.perBankWrBursts::9 7249 # Per bank write bursts +system.physmem.perBankWrBursts::10 6972 # Per bank write bursts +system.physmem.perBankWrBursts::11 6687 # Per bank write bursts +system.physmem.perBankWrBursts::12 7224 # Per bank write bursts +system.physmem.perBankWrBursts::13 7527 # Per bank write bursts +system.physmem.perBankWrBursts::14 7429 # Per bank write bursts +system.physmem.perBankWrBursts::15 7403 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1195751937000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6825 # Read request sizes (log2) +system.physmem.readPktSize::3 6488064 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 159882 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 64738 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -157,31 +159,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -189,282 +191,423 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 8 0.02% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 11 0.03% 78.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 6 0.02% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 9 0.03% 78.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 11 0.03% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 7 0.02% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 32 0.09% 78.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 3 0.01% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 6 0.02% 78.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 3 0.01% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 3 0.01% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 7 0.02% 78.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 5 0.01% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 6 0.02% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 4 0.01% 78.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 5 0.01% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 2 0.01% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 1 0.00% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 4 0.01% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 2 0.01% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 3 0.01% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 4 0.01% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 1 0.00% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 2 0.01% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 4 0.01% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 5 0.01% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 1 0.00% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 2 0.01% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 2 0.01% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 1 0.00% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 4 0.01% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 78.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 22 0.06% 78.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 5 0.01% 78.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 7 0.02% 78.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 3 0.01% 79.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 79.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 6 0.02% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 7 0.02% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 1 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 9 0.03% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 6 0.02% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 323 0.95% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8319 1 0.00% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 25 0.07% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 138 0.40% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 174 0.51% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 2 0.01% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 1 0.00% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8959 1 0.00% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 3 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 1 0.00% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 2 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 1 0.00% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 4 0.01% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11839 2 0.01% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation -system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests -system.physmem.totBusLat 33270500000 # Total cycles spent in databus access -system.physmem.totBankLat 8590725000 # Total cycles spent in bank access -system.physmem.avgQLat 19013.79 # Average queueing delay per request -system.physmem.avgBankLat 1291.04 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25304.84 # Average memory access latency -system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 14.04 # Average write queue length over time -system.physmem.readRowHits 6636405 # Number of row buffer hits during reads -system.physmem.writeRowHits 97666 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes -system.physmem.avgGap 159826.58 # Average gap between requests +system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 10 0.01% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 12 0.02% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 9 0.01% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 5 0.01% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 168 0.22% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 11 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 9 0.01% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 4 0.01% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 161 0.21% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 30 0.04% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 2 0.00% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 2 0.00% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 144 0.19% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 2 0.00% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 86 0.11% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 18 0.02% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 5 0.01% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 166 0.22% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 24 0.03% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 69 0.09% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 148 0.20% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10311 1 0.00% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 31 0.04% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 9 0.01% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 1 0.00% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 75 0.10% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 96 0.13% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 79 0.11% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 29 0.04% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11975 1 0.00% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 17 0.02% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 176 0.23% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 83 0.11% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 12 0.02% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 24 0.03% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 154 0.21% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 2 0.00% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 30 0.04% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13639 1 0.00% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 90 0.12% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 16 0.02% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 91 0.12% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 14 0.02% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 2 0.00% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 154 0.21% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 12 0.02% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 76 0.10% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 82 0.11% 85.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 16 0.02% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 19 0.03% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 4 0.01% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 270 0.36% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 2 0.00% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 17 0.02% 86.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 84 0.11% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 77 0.10% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 12 0.02% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 2 0.00% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 156 0.21% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 14 0.02% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 92 0.12% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 12 0.02% 86.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 95 0.13% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 30 0.04% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 1 0.00% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 153 0.20% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 23 0.03% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 10 0.01% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 83 0.11% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 180 0.24% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20551 2 0.00% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 18 0.02% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 75 0.10% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 92 0.12% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21959 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 14 0.02% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 35 0.05% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 142 0.19% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 87 0.12% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 1 0.00% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 4 0.01% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 166 0.22% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 23 0.03% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 66 0.09% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 30 0.04% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 147 0.20% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 27 0.04% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 68 0.09% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 24 0.03% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 1 0.00% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 171 0.23% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 5 0.01% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 19 0.03% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 83 0.11% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 139 0.19% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 34 0.05% 89.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 75 0.10% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 2 0.00% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 88 0.12% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 2 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 75 0.10% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 24 0.03% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 21 0.03% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 180 0.24% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 2 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 82 0.11% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 10 0.01% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 24 0.03% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 153 0.20% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 28 0.04% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 92 0.12% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 14 0.02% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 87 0.12% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 12 0.02% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 151 0.20% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 11 0.01% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 72 0.10% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 84 0.11% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 15 0.02% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 273 0.36% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 27 0.04% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 28 0.04% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 83 0.11% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 70 0.09% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 153 0.20% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 13 0.02% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 85 0.11% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 13 0.02% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 90 0.12% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 32 0.04% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 150 0.20% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 9 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 172 0.23% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 19 0.03% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 2 0.00% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 23 0.03% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 70 0.09% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 89 0.12% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 2 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 74 0.10% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 31 0.04% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 140 0.19% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 81 0.11% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 14 0.02% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 5 0.01% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 169 0.23% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 23 0.03% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 29 0.04% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 152 0.20% 94.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 26 0.03% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 66 0.09% 94.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 22 0.03% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 165 0.22% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 4 0.01% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 13 0.02% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42560-42567 1 0.00% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 87 0.12% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 139 0.19% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 32 0.04% 95.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43584-43591 1 0.00% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 72 0.10% 95.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 72 0.10% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 22 0.03% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44736-44743 1 0.00% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 169 0.23% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 83 0.11% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 7 0.01% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 22 0.03% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 150 0.20% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 96 0.13% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 12 0.02% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 92 0.12% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 3 0.00% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 18 0.02% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 2 0.00% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 154 0.21% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 17 0.02% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 94 0.13% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 97 0.13% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 12 0.02% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation +system.physmem.totQLat 159590177750 # Total ticks spent queuing +system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks +system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.83 # Data bus utilization in percentage +system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing +system.physmem.readRowHits 6598517 # Number of row buffer hits during reads +system.physmem.writeRowHits 94894 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes +system.physmem.avgGap 159938.04 # Average gap between requests +system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -483,286 +626,286 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60029719 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703148 # Transaction distribution -system.membus.trans_dist::ReadResp 7703148 # Transaction distribution -system.membus.trans_dist::WriteReq 767203 # Transaction distribution -system.membus.trans_dist::WriteResp 767203 # Transaction distribution -system.membus.trans_dist::Writeback 64631 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution -system.membus.trans_dist::ReadExReq 137763 # Transaction distribution -system.membus.trans_dist::ReadExResp 137302 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes) +system.membus.throughput 59999152 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703168 # Transaction distribution +system.membus.trans_dist::ReadResp 7703168 # Transaction distribution +system.membus.trans_dist::WriteReq 767205 # Transaction distribution +system.membus.trans_dist::WriteResp 767205 # Transaction distribution +system.membus.trans_dist::Writeback 64738 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution +system.membus.trans_dist::ReadExReq 137900 # Transaction distribution +system.membus.trans_dist::ReadExResp 137428 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71728526 # Total data (bytes) +system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71744366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 69624 # number of replacements -system.l2c.tags.tagsinuse 53154.717455 # Cycle average of tags in use -system.l2c.tags.total_refs 1650852 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134785 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.248039 # Average number of references to valid blocks. +system.l2c.tags.replacements 69764 # number of replacements +system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use +system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40039.692381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4638.680952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5789.816440 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1927.067698 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 756.788910 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.610957 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5787.407955 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1927.694562 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 755.712463 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.611034 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.088346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.088309 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011548 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1438 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 483013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 241892 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1869 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 372280 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 110462 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1219260 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576006 # number of Writeback hits -system.l2c.Writeback_hits::total 576006 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1292 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 416 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1708 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65542 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 45349 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110891 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1438 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 483013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 307434 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1869 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 372280 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155811 # number of demand (read+write) hits -system.l2c.demand_hits::total 1330151 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1438 # number of overall hits -system.l2c.overall_hits::cpu0.inst 483013 # number of overall hits -system.l2c.overall_hits::cpu0.data 307434 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1869 # number of overall hits -system.l2c.overall_hits::cpu1.inst 372280 # number of overall hits -system.l2c.overall_hits::cpu1.data 155811 # number of overall hits -system.l2c.overall_hits::total 1330151 # number of overall hits +system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011531 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.811096 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4686 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1510 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 483170 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 242041 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3562 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1809 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110996 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220343 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576824 # number of Writeback hits +system.l2c.Writeback_hits::total 576824 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 452 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1741 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 268 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 366 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65622 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 45295 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110917 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4686 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1510 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 483170 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 307663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3562 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1809 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 372569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 156291 # number of demand (read+write) hits +system.l2c.demand_hits::total 1331260 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4686 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1510 # number of overall hits +system.l2c.overall_hits::cpu0.inst 483170 # number of overall hits +system.l2c.overall_hits::cpu0.data 307663 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3562 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1809 # number of overall hits +system.l2c.overall_hits::cpu1.inst 372569 # number of overall hits +system.l2c.overall_hits::cpu1.data 156291 # number of overall hits +system.l2c.overall_hits::total 1331260 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6832 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9716 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6835 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9720 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22441 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3974 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7345 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 385 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 476 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 95136 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 44603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139739 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 4001 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1892 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22455 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3383 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 7371 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 866 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 95249 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 44598 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139847 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6832 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 104852 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6835 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 104969 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3996 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 46493 # number of demand (read+write) misses -system.l2c.demand_misses::total 162180 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4001 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 46490 # number of demand (read+write) misses +system.l2c.demand_misses::total 162302 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6832 # number of overall misses -system.l2c.overall_misses::cpu0.data 104852 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6835 # number of overall misses +system.l2c.overall_misses::cpu0.data 104969 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3996 # number of overall misses -system.l2c.overall_misses::cpu1.data 46493 # number of overall misses -system.l2c.overall_misses::total 162180 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 687750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 482771250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 688091749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 282183750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 151111000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1605057249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 11611000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12427970 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24038970 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1906918 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117452 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3024370 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6193599427 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2824169884 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9017769311 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 687750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 482771250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6881691176 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 282183750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2975280884 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10622826560 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 687750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 482771250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6881691176 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 282183750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2975280884 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10622826560 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1440 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 489845 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 251608 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1870 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 376276 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 112352 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1241701 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 576006 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 576006 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5266 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3787 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 9053 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 640 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1216 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 160678 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 89952 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 250630 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1440 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 489845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1870 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 376276 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 202304 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492331 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1440 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 489845 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1870 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 376276 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 202304 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492331 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013947 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038616 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010620 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.016822 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018073 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754652 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890151 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.811333 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.601562 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826389 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.708059 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.592091 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.495853 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.557551 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001389 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013947 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.254319 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010620 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.229818 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108676 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001389 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013947 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.254319 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010620 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.229818 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108676 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70663.239169 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 70820.476431 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70616.554054 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 79952.910053 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 71523.428056 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2921.741319 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3686.730940 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3272.834581 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4953.033766 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2347.588235 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3512.624855 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65102.583953 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63317.935655 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 64532.945785 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 65500.225429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 65500.225429 # average overall miss latency +system.l2c.overall_misses::cpu1.inst 4001 # number of overall misses +system.l2c.overall_misses::cpu1.data 46490 # number of overall misses +system.l2c.overall_misses::total 162302 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 302000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 491601250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 735185497 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 283983750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 151633750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1662931247 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11383008 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12410968 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 23793976 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1839921 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117953 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2957874 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6545912193 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3449006386 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9994918579 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 302000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 491601250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 7281097690 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 283983750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3600640136 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11657849826 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 302000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 491601250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 7281097690 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 283983750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3600640136 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11657849826 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4690 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1512 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 490005 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 251761 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 3562 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1810 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 376570 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 112888 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1242798 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 576824 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 576824 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5277 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3835 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9112 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 655 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 577 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1232 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 160871 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 89893 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250764 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4690 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1512 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 490005 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 412632 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 3562 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1810 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 376570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 202781 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1493562 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4690 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1512 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 490005 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 412632 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 3562 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1810 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 376570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 202781 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1493562 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001323 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013949 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038608 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000552 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010625 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.016760 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018068 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.755732 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.882138 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.808933 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.590840 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830156 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.702922 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.592083 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.496123 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.557684 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001323 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013949 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.254389 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000552 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010625 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.229262 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108668 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001323 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013949 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.254389 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000552 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010625 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.229262 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108668 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71924.103877 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75636.368004 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70978.192952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 80144.688161 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 74056.167758 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2854.314945 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3668.627845 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3228.052639 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4754.317829 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2333.931106 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3415.558891 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68724.209105 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77335.449706 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 71470.382482 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71924.103877 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71828.134133 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71924.103877 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71828.134133 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -771,8 +914,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64631 # number of writebacks -system.l2c.writebacks::total 64631 # number of writebacks +system.l2c.writebacks::writebacks 64738 # number of writebacks +system.l2c.writebacks::total 64738 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -781,149 +924,149 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6831 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9716 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6834 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9720 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3996 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22440 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 3974 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3371 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 7345 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 385 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 476 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 95136 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 44603 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139739 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4001 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1892 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22454 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3988 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3383 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 7371 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 387 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 866 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 95249 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 44598 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139847 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6831 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 104852 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6834 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 104969 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3996 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 46493 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162179 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4001 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 46490 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162301 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6831 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 104852 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6834 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 104969 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3996 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 46493 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162179 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 635750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 396501000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 564859249 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 231739250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 127085000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1320993999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39771967 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33821856 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 73593823 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3851884 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768975 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 8620859 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5000986069 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2264195114 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7265181183 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 635750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 396501000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5565845318 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 231739250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2391280114 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8586175182 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 635750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 396501000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5565845318 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 231739250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2391280114 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8586175182 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 323836500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647640494 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4849500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070543500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167046869994 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272049535 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486218500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16758268035 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 323836500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919690029 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4849500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556762000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183805138029 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038616 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016822 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018072 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754652 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890151 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.811333 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601562 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826389 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708059 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592091 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495853 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.557551 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.108675 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.108675 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58137.016159 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67240.740741 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 58867.825267 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.044036 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.181845 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.581076 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.893506 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.855042 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.612079 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52566.705233 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50763.292021 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51991.077530 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 4001 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 46490 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162301 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 254000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 405760500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 614009497 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 233748250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 128083750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1382043497 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39929483 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33964367 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 73893850 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3876386 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4797478 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 8673864 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5351778297 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2889281614 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8241059911 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 254000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 405760500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5965787794 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 233748250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3017365364 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9623103408 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 254000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 405760500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5965787794 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 233748250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3017365364 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9623103408 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344713750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648858491 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5098250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154081373749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167080044240 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272206162 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486212000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16758418162 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344713750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28921064653 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5098250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154567585749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183838462402 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038608 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016760 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018067 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.755732 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.882138 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808933 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.590840 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830156 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702922 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592083 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.496123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557684 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108667 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108667 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -944,64 +1087,64 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118384606 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137140510 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks) +system.toL2Bus.throughput 118413539 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137274438 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45439063 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution +system.iobus.throughput 45405912 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution system.iobus.trans_dist::WriteResp 7946 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) @@ -1021,14 +1164,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) @@ -1048,18 +1191,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294390 # Total data (bytes) +system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294406 # Total data (bytes) system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4039000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1101,32 +1244,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9653247 # DTB read hits -system.cpu0.dtb.read_misses 3738 # DTB read misses -system.cpu0.dtb.write_hits 7597488 # DTB write hits -system.cpu0.dtb.write_misses 1585 # DTB write misses +system.cpu0.dtb.read_hits 9652613 # DTB read hits +system.cpu0.dtb.read_misses 3746 # DTB read misses +system.cpu0.dtb.write_hits 7596890 # DTB write hits +system.cpu0.dtb.write_misses 1582 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9656985 # DTB read accesses -system.cpu0.dtb.write_accesses 7599073 # DTB write accesses +system.cpu0.dtb.read_accesses 9656359 # DTB read accesses +system.cpu0.dtb.write_accesses 7598472 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17250735 # DTB hits -system.cpu0.dtb.misses 5323 # DTB misses -system.cpu0.dtb.accesses 17256058 # DTB accesses -system.cpu0.itb.inst_hits 43297764 # ITB inst hits +system.cpu0.dtb.hits 17249503 # DTB hits +system.cpu0.dtb.misses 5328 # DTB misses +system.cpu0.dtb.accesses 17254831 # DTB accesses +system.cpu0.itb.inst_hits 43298526 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1143,79 +1286,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses -system.cpu0.itb.hits 43297764 # DTB hits +system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses +system.cpu0.itb.hits 43298526 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43299969 # DTB accesses -system.cpu0.numCycles 2389767161 # number of cpu cycles simulated +system.cpu0.itb.accesses 43300731 # DTB accesses +system.cpu0.numCycles 2391512647 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42570861 # Number of instructions committed -system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses +system.cpu0.committedInsts 42571581 # Number of instructions committed +system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403492 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48060351 # number of integer instructions +system.cpu0.num_func_calls 1403638 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48058821 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18020156 # number of memory refs -system.cpu0.num_load_insts 10037111 # Number of load instructions -system.cpu0.num_store_insts 7983045 # Number of store instructions -system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles -system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles +system.cpu0.num_mem_refs 18019009 # number of memory refs +system.cpu0.num_load_insts 10036459 # Number of load instructions +system.cpu0.num_store_insts 7982550 # Number of store instructions +system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles +system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51312 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 490078 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.399401 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42807156 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 490590 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 87.256479 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76013480250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.399401 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994921 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994921 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42807156 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42807156 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42807156 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42807156 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42807156 # number of overall hits -system.cpu0.icache.overall_hits::total 42807156 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490591 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490591 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490591 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490591 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490591 # number of overall misses -system.cpu0.icache.overall_misses::total 490591 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6809993230 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6809993230 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6809993230 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6809993230 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6809993230 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6809993230 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 43297747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43297747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 43297747 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43297747 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 43297747 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43297747 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011331 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011331 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011331 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011331 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011331 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011331 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13881.202937 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13881.202937 # average overall miss latency +system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 490259 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490771 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.225482 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76178400000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.365280 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994854 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994854 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42807737 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42807737 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42807737 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42807737 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42807737 # number of overall hits +system.cpu0.icache.overall_hits::total 42807737 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490772 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490772 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490772 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490772 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490772 # number of overall misses +system.cpu0.icache.overall_misses::total 490772 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6820513233 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6820513233 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6820513233 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6820513233 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6820513233 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6820513233 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298509 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43298509 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43298509 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43298509 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43298509 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43298509 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011335 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011335 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011335 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011335 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011335 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011335 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.519078 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.519078 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13897.519078 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13897.519078 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1224,120 +1367,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490591 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490591 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490591 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490591 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490591 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490591 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5825469770 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5825469770 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5825469770 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5825469770 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5825469770 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5825469770 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 415499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 415499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 415499500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 415499500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490772 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490772 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490772 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490772 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490772 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490772 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5836336767 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5836336767 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5836336767 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5836336767 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5836336767 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5836336767 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011335 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011335 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011335 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11892.155149 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 406634 # number of replacements -system.cpu0.dcache.tags.tagsinuse 471.214045 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 15967998 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 407146 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 39.219341 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 643231250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.214045 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920340 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.920340 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 9137347 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 9137347 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6494912 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6494912 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156532 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156532 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159004 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159004 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 15632259 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 15632259 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 15632259 # number of overall hits -system.cpu0.dcache.overall_hits::total 15632259 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 263669 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 263669 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 176685 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 176685 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9910 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9910 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7384 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7384 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 440354 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 440354 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 440354 # number of overall misses -system.cpu0.dcache.overall_misses::total 440354 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3876875497 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3876875497 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7541622539 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7541622539 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98733750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 98733750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40506385 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 40506385 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11418498036 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11418498036 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11418498036 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11418498036 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401016 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9401016 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671597 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6671597 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166442 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 166442 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166388 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166388 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 16072613 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 16072613 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 16072613 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 16072613 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028047 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028047 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026483 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026483 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059540 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059540 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044378 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044378 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14703.569616 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14703.569616 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42683.999994 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42683.999994 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9963.042381 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9963.042381 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5485.696777 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5485.696777 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25930.269819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819 # average overall miss latency +system.cpu0.dcache.tags.replacements 407019 # number of replacements +system.cpu0.dcache.tags.tagsinuse 470.951702 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 15966189 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 407531 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 39.177852 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.951702 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919828 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.919828 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9136364 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9136364 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6494337 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6494337 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156491 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156491 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158920 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 158920 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15630701 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15630701 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15630701 # number of overall hits +system.cpu0.dcache.overall_hits::total 15630701 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 264039 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 264039 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176698 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176698 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9925 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9925 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7429 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7429 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440737 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440737 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440737 # number of overall misses +system.cpu0.dcache.overall_misses::total 440737 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3925412746 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3925412746 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7893125788 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7893125788 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98805250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98805250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40843887 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 40843887 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11818538534 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11818538534 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11818538534 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11818538534 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400403 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9400403 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671035 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6671035 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166349 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166349 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16071438 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16071438 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16071438 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16071438 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028088 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028088 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026487 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026487 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059640 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059640 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044659 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044659 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027424 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027424 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027424 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027424 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14866.791444 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14866.791444 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44670.147868 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44670.147868 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9955.188917 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9955.188917 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5497.898371 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26815.399057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26815.399057 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1346,66 +1489,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376568 # number of writebacks -system.cpu0.dcache.writebacks::total 376568 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263669 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 263669 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176685 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176685 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9910 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9910 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7379 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7379 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 440354 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 440354 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 440354 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 440354 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3344880503 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3344880503 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7142186461 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7142186461 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78848250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78848250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25751615 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25751615 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 376552 # number of writebacks +system.cpu0.dcache.writebacks::total 376552 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 264039 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 264039 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176698 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176698 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7424 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7424 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440737 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440737 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440737 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440737 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3395057254 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3395057254 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7495344212 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7495344212 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78904750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78904750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25999113 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25999113 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10487066964 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10487066964 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10487066964 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10487066964 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764220500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764220500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807115461 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807115461 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39571335961 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39571335961 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028047 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028047 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026483 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026483 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059540 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059540 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044348 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044348 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1415,26 +1558,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5705173 # DTB read hits -system.cpu1.dtb.read_misses 3576 # DTB read misses -system.cpu1.dtb.write_hits 3872049 # DTB write hits -system.cpu1.dtb.write_misses 645 # DTB write misses +system.cpu1.dtb.read_hits 5708064 # DTB read hits +system.cpu1.dtb.read_misses 3582 # DTB read misses +system.cpu1.dtb.write_hits 3874465 # DTB write hits +system.cpu1.dtb.write_misses 647 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5708749 # DTB read accesses -system.cpu1.dtb.write_accesses 3872694 # DTB write accesses +system.cpu1.dtb.read_accesses 5711646 # DTB read accesses +system.cpu1.dtb.write_accesses 3875112 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9577222 # DTB hits -system.cpu1.dtb.misses 4221 # DTB misses -system.cpu1.dtb.accesses 9581443 # DTB accesses -system.cpu1.itb.inst_hits 19377969 # ITB inst hits +system.cpu1.dtb.hits 9582529 # DTB hits +system.cpu1.dtb.misses 4229 # DTB misses +system.cpu1.dtb.accesses 9586758 # DTB accesses +system.cpu1.itb.inst_hits 19382020 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1451,79 +1594,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses -system.cpu1.itb.hits 19377969 # DTB hits +system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses +system.cpu1.itb.hits 19382020 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19380140 # DTB accesses -system.cpu1.numCycles 2388332817 # number of cpu cycles simulated +system.cpu1.itb.accesses 19384191 # DTB accesses +system.cpu1.numCycles 2390063941 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18797412 # Number of instructions committed -system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses +system.cpu1.committedInsts 18801432 # Number of instructions committed +system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796668 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22263010 # number of integer instructions +system.cpu1.num_func_calls 796781 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22272671 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10012651 # number of memory refs -system.cpu1.num_load_insts 5981805 # Number of load instructions -system.cpu1.num_store_insts 4030846 # Number of store instructions -system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles -system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles -system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles +system.cpu1.num_mem_refs 10017952 # number of memory refs +system.cpu1.num_load_insts 5984754 # Number of load instructions +system.cpu1.num_store_insts 4033198 # Number of store instructions +system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles +system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles +system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 376539 # number of replacements -system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits -system.cpu1.icache.overall_hits::total 19000914 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses -system.cpu1.icache.overall_misses::total 377051 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency +system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376793 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits +system.cpu1.icache.overall_hits::total 19004711 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses +system.cpu1.icache.overall_misses::total 377305 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1532,120 +1675,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377051 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377051 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377051 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377051 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377051 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377051 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398685536 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398685536 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398685536 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4398685536 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398685536 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4398685536 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019458 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019458 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11666.022729 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377305 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377305 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377305 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4403600289 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4403600289 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4403600289 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4403600289 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4403600289 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4403600289 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6432750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6432750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6432750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6432750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019467 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019467 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019467 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.195158 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 220336 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.526784 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8228665 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 220703 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.283884 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106211109000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.526784 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920951 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920951 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 4388185 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4388185 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3672248 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3672248 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73451 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 73451 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73727 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 73727 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8060433 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8060433 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8060433 # number of overall hits -system.cpu1.dcache.overall_hits::total 8060433 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133748 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133748 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 112730 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 112730 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9735 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9735 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9394 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9394 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 246478 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 246478 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 246478 # number of overall misses -system.cpu1.dcache.overall_misses::total 246478 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1649486235 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1649486235 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3739097468 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3739097468 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77937249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 77937249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49168975 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49168975 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5388583703 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5388583703 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5388583703 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5388583703 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4521933 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4521933 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3784978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3784978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 83186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83121 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83121 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8306911 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8306911 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8306911 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8306911 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029578 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.029578 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029784 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029784 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117027 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117027 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113016 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113016 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029671 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029671 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029671 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.029671 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12332.791780 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12332.791780 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33168.610556 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33168.610556 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8005.880740 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8005.880740 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5234.082925 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5234.082925 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21862.331336 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21862.331336 # average overall miss latency +system.cpu1.dcache.tags.replacements 220883 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.477381 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8233318 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 221230 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.216101 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106377423000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.477381 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920854 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920854 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 4390672 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4390672 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3674527 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3674527 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73485 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 73485 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73732 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73732 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8065199 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8065199 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8065199 # number of overall hits +system.cpu1.dcache.overall_hits::total 8065199 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 134090 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 134090 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 112827 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 112827 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9762 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9762 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9429 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9429 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 246917 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 246917 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 246917 # number of overall misses +system.cpu1.dcache.overall_misses::total 246917 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1656976729 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1656976729 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4353399476 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4353399476 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77544499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77544499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49349978 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49349978 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6010376205 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6010376205 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6010376205 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6010376205 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524762 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4524762 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3787354 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 83247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83161 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83161 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8312116 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8312116 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8312116 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8312116 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029635 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029635 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029790 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029790 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117265 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117265 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113382 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113382 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029706 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029706 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029706 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.029706 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12357.198367 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12357.198367 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38584.731279 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 38584.731279 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7943.505327 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7943.505327 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5233.850673 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5233.850673 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24341.686498 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24341.686498 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1654,66 +1797,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 199438 # number of writebacks -system.cpu1.dcache.writebacks::total 199438 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133748 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133748 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112730 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 112730 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9735 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9735 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9393 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9393 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 246478 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 246478 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 246478 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 246478 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1381071765 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1381071765 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3492633532 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3492633532 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58449751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58449751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30384025 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30384025 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 200272 # number of writebacks +system.cpu1.dcache.writebacks::total 200272 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134090 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134090 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112827 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112827 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9762 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9762 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9426 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9426 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246917 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246917 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1388441271 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5506215795 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5506215795 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5506215795 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5506215795 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168382941250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168382941250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531038000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531038000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168913979250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168913979250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029790 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029790 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117265 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117265 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113346 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113346 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029706 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029706 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10354.547476 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10354.547476 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36496.357468 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36496.357468 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5942.993342 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1735,10 +1878,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index efd49eb78..50a428e90 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,130 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.615716 # Number of seconds simulated -sim_ticks 2615716222000 # Number of ticks simulated -final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616536 # Number of seconds simulated +sim_ticks 2616536483000 # Number of ticks simulated +final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250038 # Simulator instruction rate (inst/s) -host_op_rate 318184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10864403710 # Simulator tick rate (ticks/s) -host_mem_usage 394540 # Number of bytes of host memory used -host_seconds 240.76 # Real time elapsed on the host -sim_insts 60199078 # Number of instructions simulated -sim_ops 76605946 # Number of ops (including micro ops) simulated +host_inst_rate 552343 # Simulator instruction rate (inst/s) +host_op_rate 702879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24008008080 # Simulator tick rate (ticks/s) +host_mem_usage 395660 # Number of bytes of host memory used +host_seconds 108.99 # Real time elapsed on the host +sim_insts 60197580 # Number of instructions simulated +sim_ops 76603973 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory -system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 703904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089744 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 703904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 703904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory +system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142061 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494693 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 991665344 # Total number of bytes read from memory -system.physmem.bytesWritten 51967296 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6526 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2615711849000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6652 # Categorize read packet sizes -system.physmem.readPktSize::3 15335424 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152695 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57971 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1137574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 984079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1018155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3783404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2827794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2821787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2781992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 48 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 269021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53199998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494693 # Number of read requests accepted +system.physmem.writeReqs 811927 # Number of write requests accepted +system.physmem.readBursts 15494693 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991555264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue +system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132477488 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 967983 # Per bank write bursts +system.physmem.perBankRdBursts::1 967714 # Per bank write bursts +system.physmem.perBankRdBursts::2 967672 # Per bank write bursts +system.physmem.perBankRdBursts::3 967769 # Per bank write bursts +system.physmem.perBankRdBursts::4 974609 # Per bank write bursts +system.physmem.perBankRdBursts::5 968229 # Per bank write bursts +system.physmem.perBankRdBursts::6 967807 # Per bank write bursts +system.physmem.perBankRdBursts::7 967736 # Per bank write bursts +system.physmem.perBankRdBursts::8 968546 # Per bank write bursts +system.physmem.perBankRdBursts::9 968137 # Per bank write bursts +system.physmem.perBankRdBursts::10 967949 # Per bank write bursts +system.physmem.perBankRdBursts::11 967746 # Per bank write bursts +system.physmem.perBankRdBursts::12 967851 # Per bank write bursts +system.physmem.perBankRdBursts::13 967741 # Per bank write bursts +system.physmem.perBankRdBursts::14 967766 # Per bank write bursts +system.physmem.perBankRdBursts::15 967796 # Per bank write bursts +system.physmem.perBankWrBursts::0 6610 # Per bank write bursts +system.physmem.perBankWrBursts::1 6410 # Per bank write bursts +system.physmem.perBankWrBursts::2 6422 # Per bank write bursts +system.physmem.perBankWrBursts::3 6344 # Per bank write bursts +system.physmem.perBankWrBursts::4 6906 # Per bank write bursts +system.physmem.perBankWrBursts::5 7096 # Per bank write bursts +system.physmem.perBankWrBursts::6 6901 # Per bank write bursts +system.physmem.perBankWrBursts::7 6892 # Per bank write bursts +system.physmem.perBankWrBursts::8 7193 # Per bank write bursts +system.physmem.perBankWrBursts::9 6845 # Per bank write bursts +system.physmem.perBankWrBursts::10 6667 # Per bank write bursts +system.physmem.perBankWrBursts::11 6550 # Per bank write bursts +system.physmem.perBankWrBursts::12 6596 # Per bank write bursts +system.physmem.perBankWrBursts::13 6392 # Per bank write bursts +system.physmem.perBankWrBursts::14 6532 # Per bank write bursts +system.physmem.perBankWrBursts::15 6576 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2616532122000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6652 # Read request sizes (log2) +system.physmem.readPktSize::3 15335424 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 152617 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 57909 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1265330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1118297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1122310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3740106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2667387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2661184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2667924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 54482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -140,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -172,281 +174,478 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 26227.310287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2428.378300 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31656.989485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5540 14.55% 14.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3323 8.73% 23.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2175 5.71% 29.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1668 4.38% 33.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1160 3.05% 36.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1060 2.78% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 828 2.18% 41.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 781 2.05% 43.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 514 1.35% 44.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 493 1.30% 46.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 417 1.10% 47.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 450 1.18% 48.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 283 0.74% 49.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 279 0.73% 49.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 185 0.49% 50.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 195 0.51% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 134 0.35% 51.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 139 0.37% 51.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 114 0.30% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 94 0.25% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 76 0.20% 52.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 792 2.08% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 136 0.36% 55.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 113 0.30% 55.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 85 0.22% 56.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 60 0.16% 56.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 34 0.09% 56.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 44 0.12% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 48 0.13% 56.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 35 0.09% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 24 0.06% 57.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 25 0.07% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 18 0.05% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 21 0.06% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 5 0.01% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 8 0.02% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 15 0.04% 57.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 17 0.04% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 7 0.02% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 18 0.05% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 8 0.02% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 16 0.04% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 11 0.03% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 6 0.02% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 5 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 5 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 7 0.02% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 6 0.02% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 6 0.02% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 9 0.02% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 42 0.11% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 2 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 4 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 8 0.02% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 4 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 5 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 6 0.02% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 1 0.00% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 6 0.02% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 1 0.00% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 10 0.03% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 2 0.01% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 5 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 2 0.01% 58.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 3 0.01% 58.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 3 0.01% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 3 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 1 0.00% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 2 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 2 0.01% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 2 0.01% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 1 0.00% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 4 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 6 0.02% 58.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 16 0.04% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 4 0.01% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 4 0.01% 58.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 4 0.01% 58.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 2 0.01% 58.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 2 0.01% 58.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 5 0.01% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 7 0.02% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 6 0.02% 58.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 8 0.02% 58.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 8 0.02% 58.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 328 0.86% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 24 0.06% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 141 0.37% 59.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 169 0.44% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8831 1 0.00% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 2 0.01% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 3 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 3 0.01% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 4 0.01% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 1 0.00% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11967 1 0.00% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 2 0.01% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12991 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13247 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-14015 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 4 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-15039 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16703 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 2 0.01% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 5 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18687 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19391 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20415 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22207 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23231 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 4 0.01% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24255 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 3 0.01% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25407 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25791 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 4 0.01% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28223 2 0.01% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28863 1 0.00% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30399 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31167 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31423 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 2 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31743 1 0.00% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 6 0.02% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33215 19 0.05% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 23 0.06% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36415 2 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40255 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41279 2 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41791 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46399 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46591 1 0.00% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47167 3 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47935 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48447 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48959 1 0.00% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49727 1 0.00% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 2 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 1 0.00% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56576-56639 1 0.00% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57407 1 0.00% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57600-57663 1 0.00% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58431 2 0.01% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60672-60735 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61247 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61696-61759 1 0.00% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 1 0.00% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 190 0.50% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65151 6 0.02% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65279 6 0.02% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 1 0.00% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 1 0.00% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 14664 38.52% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67392-67455 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69823 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71744-71807 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-74047 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation -system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests -system.physmem.totBusLat 77465575000 # Total cycles spent in databus access -system.physmem.totBankLat 16358058750 # Total cycles spent in bank access -system.physmem.avgQLat 19154.87 # Average queueing delay per request -system.physmem.avgBankLat 1055.83 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25210.70 # Average memory access latency -system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.12 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 13.76 # Average write queue length over time -system.physmem.readRowHits 15468398 # Number of row buffer hits during reads -system.physmem.writeRowHits 93875 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes -system.physmem.avgGap 160406.60 # Average gap between requests +system.physmem.bytesPerActivate::samples 89727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11127.069087 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1028.273701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16706.873806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23194 25.85% 25.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14559 16.23% 42.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2860 3.19% 45.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2118 2.36% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1356 1.51% 49.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1216 1.36% 50.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 947 1.06% 51.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1180 1.32% 52.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 650 0.72% 53.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 587 0.65% 54.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 521 0.58% 54.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 703 0.78% 55.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 336 0.37% 55.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 268 0.30% 56.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 216 0.24% 56.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 509 0.57% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 151 0.17% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 159 0.18% 57.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 138 0.15% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 229 0.26% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 246 0.27% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 69 0.08% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 53 0.06% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 188 0.21% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 32 0.04% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 26 0.03% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 180 0.20% 61.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 16 0.02% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 28 0.03% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 12 0.01% 61.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 150 0.17% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 27 0.03% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 112 0.12% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 11 0.01% 62.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 157 0.17% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 16 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 359 0.40% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 100 0.11% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 89 0.10% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 18 0.02% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 147 0.16% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 177 0.20% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 149 0.17% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 161 0.18% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 11 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 82 0.09% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 497 0.55% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 11 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 18 0.02% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 64 0.07% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 138 0.15% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 89 0.10% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 2 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 276 0.31% 65.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 33 0.04% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 146 0.16% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 83 0.09% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 5 0.01% 65.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 526 0.59% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 79 0.09% 66.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 1 0.00% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 37 0.04% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 1 0.00% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 10 0.01% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 407 0.45% 66.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 12 0.01% 66.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 33 0.04% 66.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 77 0.09% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 527 0.59% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 2 0.00% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 85 0.09% 67.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 150 0.17% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 29 0.03% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 279 0.31% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.09% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 6 0.01% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 13 0.01% 68.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 4 0.00% 68.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 496 0.55% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 2 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 77 0.09% 68.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 4 0.00% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 153 0.17% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 141 0.16% 69.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 1 0.00% 69.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 162 0.18% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 137 0.15% 69.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 74 0.08% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 90 0.10% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 343 0.38% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 145 0.16% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 2 0.00% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 90 0.10% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 2 0.00% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 133 0.15% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 1 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 164 0.18% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 153 0.17% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 1 0.00% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 162 0.18% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 88 0.10% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 278 0.31% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 83 0.09% 71.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 199 0.22% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 2 0.00% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 139 0.15% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 9 0.01% 71.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 416 0.46% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 138 0.15% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 203 0.23% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 87 0.10% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 275 0.31% 73.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 89 0.10% 73.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 73.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 155 0.17% 73.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 155 0.17% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 2 0.00% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 162 0.18% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 2 0.00% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 131 0.15% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18823 2 0.00% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 93 0.10% 74.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 74.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 142 0.16% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 3 0.00% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 2 0.00% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 340 0.38% 74.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 81 0.09% 74.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 77 0.09% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 2 0.00% 74.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 134 0.15% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 2 0.00% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 164 0.18% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 141 0.16% 75.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 1 0.00% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20935 1 0.00% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 149 0.17% 75.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 80 0.09% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 2 0.00% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 3 0.00% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 482 0.54% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 10 0.01% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 5 0.01% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22215 1 0.00% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 92 0.10% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 5 0.01% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 269 0.30% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 35 0.04% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 146 0.16% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 81 0.09% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 4 0.00% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 526 0.59% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 74 0.08% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 36 0.04% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 12 0.01% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 404 0.45% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 7 0.01% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 28 0.03% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 84 0.09% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 7 0.01% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 523 0.58% 78.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 80 0.09% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 152 0.17% 78.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 32 0.04% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 4 0.00% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 274 0.31% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.09% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 3 0.00% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 17 0.02% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 484 0.54% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27719 1 0.00% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 1 0.00% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 77 0.09% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 152 0.17% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 1 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 140 0.16% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 163 0.18% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 2 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 130 0.14% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 75 0.08% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 86 0.10% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 3 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 336 0.37% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 140 0.16% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 1 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 2 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 91 0.10% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30407 1 0.00% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 134 0.15% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 156 0.17% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 152 0.17% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 157 0.17% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 2 0.00% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31431 1 0.00% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 86 0.10% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 272 0.30% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 83 0.09% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 2 0.00% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 202 0.23% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 144 0.16% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 2 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 415 0.46% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 148 0.16% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 208 0.23% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 2 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 85 0.09% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 2 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 270 0.30% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 85 0.09% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 157 0.17% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 152 0.17% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34624-34631 2 0.00% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 147 0.16% 85.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 134 0.15% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 90 0.10% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35392-35399 2 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 4 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35520-35527 1 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 143 0.16% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 337 0.38% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 82 0.09% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 76 0.08% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 131 0.15% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 154 0.17% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 139 0.15% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 153 0.17% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 2 0.00% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 81 0.09% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37760-37767 2 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37824-37831 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 483 0.54% 87.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 87.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 12 0.01% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.09% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 271 0.30% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 30 0.03% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 152 0.17% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 3 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 86 0.10% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 521 0.58% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 2 0.00% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 77 0.09% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 28 0.03% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 10 0.01% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 402 0.45% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 9 0.01% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 35 0.04% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 4 0.00% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 79 0.09% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 523 0.58% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 79 0.09% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 146 0.16% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 34 0.04% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 269 0.30% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 89 0.10% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 3 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 13 0.01% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 1 0.00% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 482 0.54% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 78 0.09% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 151 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 138 0.15% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 3 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 153 0.17% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 2 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 134 0.15% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 77 0.09% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 341 0.38% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 2 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 140 0.16% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 93 0.10% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 133 0.15% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 149 0.17% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 156 0.17% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 157 0.17% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 88 0.10% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 298 0.33% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 110 0.12% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 200 0.22% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 70 0.08% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 136 0.15% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 9 0.01% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5002 5.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89727 # Bytes accessed per row activation +system.physmem.totQLat 373414318500 # Total ticks spent queuing +system.physmem.totMemAccLat 469593144750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18713571250 # Total ticks spent accessing banks +system.physmem.avgQLat 24102.05 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1207.87 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30309.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.98 # Data bus utilization in percentage +system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing +system.physmem.readRowHits 15419103 # Number of row buffer hits during reads +system.physmem.writeRowHits 91153 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.23 # Row buffer hit rate for writes +system.physmem.avgGap 160458.28 # Average gap between requests +system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -459,49 +658,49 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54136917 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546596 # Transaction distribution -system.membus.trans_dist::ReadResp 16546596 # Transaction distribution +system.membus.throughput 54116520 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546551 # Transaction distribution +system.membus.trans_dist::ReadResp 16546551 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution -system.membus.trans_dist::Writeback 57971 # Transaction distribution +system.membus.trans_dist::Writeback 57909 # Transaction distribution system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution -system.membus.trans_dist::ReadExReq 132250 # Transaction distribution -system.membus.trans_dist::ReadExResp 132250 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 132216 # Transaction distribution +system.membus.trans_dist::ReadExResp 132216 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893513 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280361 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951209 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914457 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141606813 # Total data (bytes) +system.membus.tot_pkt_size::total 141597849 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141597849 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910601500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950348835 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34633819250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -509,13 +708,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47816267 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution +system.iobus.throughput 47801275 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution system.iobus.trans_dist::WriteReq 8166 # Transaction distribution system.iobus.trans_dist::WriteResp 8166 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -537,12 +736,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -564,14 +763,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073785 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073781 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -617,32 +816,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42038784500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42037561750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996146 # DTB read hits -system.cpu.dtb.read_misses 7341 # DTB read misses -system.cpu.dtb.write_hits 11230467 # DTB write hits -system.cpu.dtb.write_misses 2217 # DTB write misses +system.cpu.dtb.read_hits 14995644 # DTB read hits +system.cpu.dtb.read_misses 7334 # DTB read misses +system.cpu.dtb.write_hits 11230146 # DTB write hits +system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3498 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 197 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003487 # DTB read accesses -system.cpu.dtb.write_accesses 11232684 # DTB write accesses +system.cpu.dtb.read_accesses 15002978 # DTB read accesses +system.cpu.dtb.write_accesses 11232358 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226613 # DTB hits -system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 26236171 # DTB accesses -system.cpu.itb.inst_hits 61492923 # ITB inst hits +system.cpu.dtb.hits 26225790 # DTB hits +system.cpu.dtb.misses 9546 # DTB misses +system.cpu.dtb.accesses 26235336 # DTB accesses +system.cpu.itb.inst_hits 61491413 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -659,79 +858,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61497394 # ITB inst accesses -system.cpu.itb.hits 61492923 # DTB hits +system.cpu.itb.inst_accesses 61495884 # ITB inst accesses +system.cpu.itb.hits 61491413 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61497394 # DTB accesses -system.cpu.numCycles 5231432444 # number of cpu cycles simulated +system.cpu.itb.accesses 61495884 # DTB accesses +system.cpu.numCycles 5233072966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60199078 # Number of instructions committed -system.cpu.committedOps 76605946 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872726 # Number of integer alu accesses +system.cpu.committedInsts 60197580 # Number of instructions committed +system.cpu.committedOps 76603973 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68871033 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140465 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948429 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872726 # number of integer instructions +system.cpu.num_func_calls 2140403 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948247 # number of instructions that are conditional controls +system.cpu.num_int_insts 68871033 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394779183 # number of times the integer registers were read -system.cpu.num_int_register_writes 74182470 # number of times the integer registers were written +system.cpu.num_int_register_reads 394768801 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180798 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394080 # number of memory refs -system.cpu.num_load_insts 15660200 # Number of load instructions -system.cpu.num_store_insts 11733880 # Number of store instructions -system.cpu.num_idle_cycles 4581975478.612248 # Number of idle cycles -system.cpu.num_busy_cycles 649456965.387752 # Number of busy cycles -system.cpu.not_idle_fraction 0.124145 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875855 # Percentage of idle cycles +system.cpu.num_mem_refs 27393280 # number of memory refs +system.cpu.num_load_insts 15659727 # Number of load instructions +system.cpu.num_store_insts 11733553 # Number of store instructions +system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles +system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles +system.cpu.not_idle_fraction 0.124505 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875495 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856273 # number of replacements -system.cpu.icache.tags.tagsinuse 510.884220 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60636138 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856785 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.771708 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19799760250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.884220 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997821 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60636138 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60636138 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60636138 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60636138 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60636138 # number of overall hits -system.cpu.icache.overall_hits::total 60636138 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856785 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856785 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856785 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856785 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856785 # number of overall misses -system.cpu.icache.overall_misses::total 856785 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11770019500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11770019500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11770019500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11770019500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11770019500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11770019500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61492923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61492923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61492923 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61492923 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61492923 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61492923 # number of overall (read+write) accesses +system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 856254 # number of replacements +system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60634647 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856766 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.771537 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60634647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60634647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60634647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60634647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60634647 # number of overall hits +system.cpu.icache.overall_hits::total 60634647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856766 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856766 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856766 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856766 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856766 # number of overall misses +system.cpu.icache.overall_misses::total 856766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773893500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11773893500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11773893500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11773893500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11773893500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11773893500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491413 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491413 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491413 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13737.424792 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13737.424792 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13737.424792 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13737.424792 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.251093 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13742.251093 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13742.251093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13742.251093 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,174 +939,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856785 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856785 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856785 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856785 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856785 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856785 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051263500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10051263500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051263500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10051263500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051263500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10051263500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 414413750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856766 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856766 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856766 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856766 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856766 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856766 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056315500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10056315500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056315500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10056315500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056315500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056315500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 435321250 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.371931 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.371931 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.528683 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.528683 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.528683 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.528683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.528683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.528683 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62587 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50733.810806 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1683077 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127973 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.151813 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2564904211000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37696.862224 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6998.396772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6034.666541 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 62509 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50754.670173 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1682271 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.153944 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.408308 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.399948 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.976844 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106787 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.092082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.774137 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8720 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3535 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844543 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370162 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226960 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595785 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595785 # number of Writeback hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844545 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 369635 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226417 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595234 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595234 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113425 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113425 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8720 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3535 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844543 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 483587 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340385 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8720 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3535 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844543 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 483587 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340385 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113385 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113385 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 8705 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3532 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 844545 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 483020 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1339802 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 8705 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3532 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 844545 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 483020 # number of overall hits +system.cpu.l2cache.overall_hits::total 1339802 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10601 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9837 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20445 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133893 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133893 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2907 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2907 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10601 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143730 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154338 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10585 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143633 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154225 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10601 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143730 # number of overall misses -system.cpu.l2cache.overall_misses::total 154338 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 390500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747407000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 696870750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1444790750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 470980 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 470980 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8609068107 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8609068107 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 390500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 747407000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9305938857 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10053858857 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 390500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 747407000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9305938857 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10053858857 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8725 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3537 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 855144 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 379999 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247405 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 595785 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 595785 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247318 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247318 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8725 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3537 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 855144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627317 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494723 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8725 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3537 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 855144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627317 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494723 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012397 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016390 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541380 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541380 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012397 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229119 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103255 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012397 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229119 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103255 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78100 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70503.443071 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70841.796279 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70667.192468 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.990251 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.990251 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64298.119446 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64298.119446 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65141.824159 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65141.824159 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143633 # number of overall misses +system.cpu.l2cache.overall_misses::total 154225 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752463500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 738211000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1491129750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9619522392 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9619522392 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 752463500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10357733392 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11110652142 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 752463500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10357733392 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11110652142 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 855130 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 379444 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1246818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 595234 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 595234 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2933 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247209 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247209 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8710 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3534 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 855130 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 626653 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494027 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8710 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3534 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 855130 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 626653 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494027 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025851 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991135 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991135 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541340 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541340 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229207 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103228 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229207 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103228 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71087.718470 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75258.538077 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73091.012695 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.671827 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.671827 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71881.892575 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71881.892575 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71087.718470 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72112.490806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72041.835902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71087.718470 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72112.490806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72041.835902 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -916,92 +1115,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57971 # number of writebacks -system.cpu.l2cache.writebacks::total 57971 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57909 # number of writebacks +system.cpu.l2cache.writebacks::total 57909 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10601 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9837 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20445 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133893 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133893 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10585 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20401 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2907 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2907 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10601 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143730 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154338 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143633 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154225 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10601 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143730 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154338 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 326500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 613945500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 572634250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1187003750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28725872 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28725872 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6933351393 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6933351393 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 326500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 613945500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7505985643 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8120355143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 326500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 613945500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7505985643 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8120355143 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 322980250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657157250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166980137500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702542535 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702542535 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 322980250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359699785 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183682680035 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025887 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016390 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541380 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541380 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103255 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103255 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57913.923215 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58212.285250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58058.388359 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.044568 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.044568 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51782.777240 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51782.777240 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143633 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154225 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619898500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 615330500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1235596750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29079907 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29079907 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7944865608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7944865608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619898500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8560196108 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9180462358 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619898500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8560196108 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9180462358 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 343871250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166656947250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167000818500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702635650 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702635650 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 343871250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359582900 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183703454150 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991135 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991135 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229207 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103228 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229207 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103228 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58563.863958 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62731.216230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60565.499240 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.407981 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.407981 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59368.017755 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59368.017755 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1011,79 +1210,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626805 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.881003 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655596 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 627317 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.709158 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 640871250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.881003 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999768 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195774 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195774 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972821 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972821 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168595 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168595 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168595 # number of overall hits -system.cpu.dcache.overall_hits::total 23168595 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368499 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368499 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250216 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250216 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618715 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618715 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618715 # number of overall misses -system.cpu.dcache.overall_misses::total 618715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5384538000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5384538000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10623511265 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10623511265 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158750500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158750500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16008049265 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16008049265 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16008049265 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16008049265 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564273 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564273 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223037 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223037 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787310 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787310 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787310 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787310 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027167 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027167 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024476 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024476 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14612.083072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14612.083072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42457.361899 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42457.361899 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13804.391304 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13804.391304 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25873.058298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25873.058298 # average overall miss latency +system.cpu.dcache.tags.replacements 626141 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23655438 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.748863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195736 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195736 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972597 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236394 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236394 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168333 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168333 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168333 # number of overall hits +system.cpu.dcache.overall_hits::total 23168333 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368059 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250142 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250142 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11385 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11385 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618201 # number of overall misses +system.cpu.dcache.overall_misses::total 618201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416878250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5416878250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621403015 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11621403015 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158363750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158363750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17038281265 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17038281265 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17038281265 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17038281265 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222739 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23786534 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23786534 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23786534 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23786534 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027135 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045948 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045948 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025990 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025990 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025990 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025990 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14717.418267 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14717.418267 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46459.223221 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46459.223221 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.859464 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.859464 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27561.070372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27561.070372 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1092,54 +1291,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595785 # number of writebacks -system.cpu.dcache.writebacks::total 595785 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250216 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250216 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618715 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618715 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618715 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4642816500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4642816500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10058410735 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10058410735 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135673500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135673500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14701227235 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14701227235 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14701227235 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14701227235 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234094465 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595234 # number of writebacks +system.cpu.dcache.writebacks::total 595234 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250142 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250142 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11385 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11385 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618201 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678465750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678465750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069177985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069177985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135539250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135539250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747643735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15747643735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747643735 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15747643735 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045948 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045948 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025990 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025990 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12711.184212 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12711.184212 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44251.577044 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44251.577044 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11905.072464 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.072464 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1147,37 +1346,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution +system.cpu.toL2Bus.throughput 52965120 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454582 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454582 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5751163 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755700 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83692841 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247209 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514380 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54754804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615077 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138418857 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138418857 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3008581500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295429750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534385915 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use @@ -1193,10 +1392,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1538389615750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1538389615750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index e69bdd504..79d47dc5b 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,131 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.192278 # Number of seconds simulated -sim_ticks 5192277855000 # Number of ticks simulated -final_tick 5192277855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196390 # Number of seconds simulated +sim_ticks 5196390180000 # Number of ticks simulated +final_tick 5196390180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 964497 # Simulator instruction rate (inst/s) -host_op_rate 1859169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39021883302 # Simulator tick rate (ticks/s) -host_mem_usage 587612 # Number of bytes of host memory used -host_seconds 133.06 # Real time elapsed on the host -sim_insts 128336541 # Number of instructions simulated -sim_ops 247382226 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2866368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory +host_inst_rate 893068 # Simulator instruction rate (inst/s) +host_op_rate 1721530 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36161085452 # Simulator tick rate (ticks/s) +host_mem_usage 586592 # Number of bytes of host memory used +host_seconds 143.70 # Real time elapsed on the host +sim_insts 128334813 # Number of instructions simulated +sim_ops 247385808 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2883712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9005696 # Number of bytes read from this memory -system.physmem.bytes_read::total 12698368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8111936 # Number of bytes written to this memory -system.physmem.bytes_written::total 8111936 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8989184 # Number of bytes read from this memory +system.physmem.bytes_read::total 12697856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8110912 # Number of bytes written to this memory +system.physmem.bytes_written::total 8110912 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45058 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140714 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198412 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126749 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126749 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 552044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198404 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126733 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126733 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1734440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2445626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1562308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1562308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1562308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 552044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1729890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2443592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1560874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1734440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4007933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198412 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 126749 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 198412 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 126749 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 12698368 # Total number of bytes read from memory -system.physmem.bytesWritten 8111936 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12698368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8111936 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 1635 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12459 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12489 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12070 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 11839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 11744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12394 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12454 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12175 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8067 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7928 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8252 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7644 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7381 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8073 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8318 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7938 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7649 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 5192277790500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198412 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126749 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1087 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 158670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1729890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4004466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198404 # Number of read requests accepted +system.physmem.writeReqs 126733 # Number of write requests accepted +system.physmem.readBursts 198404 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126733 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12694144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue +system.physmem.bytesWritten 8109888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12697856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8110912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1616 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12580 # Per bank write bursts +system.physmem.perBankRdBursts::1 12146 # Per bank write bursts +system.physmem.perBankRdBursts::2 12820 # Per bank write bursts +system.physmem.perBankRdBursts::3 12639 # Per bank write bursts +system.physmem.perBankRdBursts::4 12420 # Per bank write bursts +system.physmem.perBankRdBursts::5 12033 # Per bank write bursts +system.physmem.perBankRdBursts::6 12032 # Per bank write bursts +system.physmem.perBankRdBursts::7 12154 # Per bank write bursts +system.physmem.perBankRdBursts::8 12328 # Per bank write bursts +system.physmem.perBankRdBursts::9 11842 # Per bank write bursts +system.physmem.perBankRdBursts::10 12289 # Per bank write bursts +system.physmem.perBankRdBursts::11 12385 # Per bank write bursts +system.physmem.perBankRdBursts::12 12618 # Per bank write bursts +system.physmem.perBankRdBursts::13 13039 # Per bank write bursts +system.physmem.perBankRdBursts::14 12508 # Per bank write bursts +system.physmem.perBankRdBursts::15 12513 # Per bank write bursts +system.physmem.perBankWrBursts::0 8180 # Per bank write bursts +system.physmem.perBankWrBursts::1 7837 # Per bank write bursts +system.physmem.perBankWrBursts::2 8283 # Per bank write bursts +system.physmem.perBankWrBursts::3 8150 # Per bank write bursts +system.physmem.perBankWrBursts::4 7961 # Per bank write bursts +system.physmem.perBankWrBursts::5 7589 # Per bank write bursts +system.physmem.perBankWrBursts::6 7480 # Per bank write bursts +system.physmem.perBankWrBursts::7 7728 # Per bank write bursts +system.physmem.perBankWrBursts::8 7696 # Per bank write bursts +system.physmem.perBankWrBursts::9 7447 # Per bank write bursts +system.physmem.perBankWrBursts::10 7846 # Per bank write bursts +system.physmem.perBankWrBursts::11 7788 # Per bank write bursts +system.physmem.perBankWrBursts::12 8080 # Per bank write bursts +system.physmem.perBankWrBursts::13 8539 # Per bank write bursts +system.physmem.perBankWrBursts::14 8032 # Per bank write bursts +system.physmem.perBankWrBursts::15 8081 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 5196390116500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 198404 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 126733 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 155323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 52 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -137,296 +139,310 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 459.065810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.635945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1572.397321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 18574 41.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7178 15.85% 56.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4205 9.28% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2900 6.40% 72.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1973 4.36% 76.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1677 3.70% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1250 2.76% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1043 2.30% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 738 1.63% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 608 1.34% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 523 1.15% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 460 1.02% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 307 0.68% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 311 0.69% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 233 0.51% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 396 0.87% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 152 0.34% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 138 0.30% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 115 0.25% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 132 0.29% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 133 0.29% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 129 0.28% 95.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 607 1.34% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 165 0.36% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 95 0.21% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 80 0.18% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 50 0.11% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 52 0.11% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 21 0.05% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 24 0.05% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 26 0.06% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 33 0.07% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 17 0.04% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 17 0.04% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 9 0.02% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 10 0.02% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 5 0.01% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 8 0.02% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 10 0.02% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 7 0.02% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 2 0.00% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.01% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 4 0.01% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 1 0.00% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 11 0.02% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 3 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 3 0.01% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 12 0.03% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 18 0.04% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 7 0.02% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 3 0.01% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 3 0.01% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 3 0.01% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 10 0.02% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 3 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 3 0.01% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 7 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 244 0.54% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 12 0.03% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17155 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17283 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45297 # Bytes accessed per row activation -system.physmem.totQLat 3410755000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7054990000 # Sum of mem lat for all requests -system.physmem.totBusLat 991695000 # Total cycles spent in databus access -system.physmem.totBankLat 2652540000 # Total cycles spent in bank access -system.physmem.avgQLat 17196.59 # Average queueing delay per request -system.physmem.avgBankLat 13373.77 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35570.36 # Average memory access latency -system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 5072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 20 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 53708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.265063 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.541838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1283.636288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 22377 41.66% 41.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 8801 16.39% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5780 10.76% 68.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3435 6.40% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2322 4.32% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1859 3.46% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1339 2.49% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1034 1.93% 87.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 806 1.50% 88.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 663 1.23% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 546 1.02% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 427 0.80% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 325 0.61% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 307 0.57% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 277 0.52% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 550 1.02% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 185 0.34% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 190 0.35% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 112 0.21% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 109 0.20% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 125 0.23% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 422 0.79% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 149 0.28% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.16% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 55 0.10% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 85 0.16% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 52 0.10% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 36 0.07% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 25 0.05% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 24 0.04% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 18 0.03% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 26 0.05% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 25 0.05% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 20 0.04% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.02% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 14 0.03% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 11 0.02% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 14 0.03% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 11 0.02% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 9 0.02% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 10 0.02% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 13 0.02% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 26 0.05% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 12 0.02% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 9 0.02% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 19 0.04% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 10 0.02% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 9 0.02% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 12 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 12 0.02% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 15 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 10 0.02% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 20 0.04% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 13 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 24 0.04% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 13 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 11 0.02% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 19 0.04% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 10 0.02% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 13 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 7 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 9 0.02% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 11 0.02% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 7 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 9 0.02% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 9 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 10 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 9 0.02% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 7 0.01% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 9 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 7 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 5 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 13 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 8 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 7 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 8 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 10 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 5 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 9 0.02% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 151 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 2 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 4 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 19 0.04% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 4 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 14 0.03% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 4 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 4 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 6 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 7 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 32 0.06% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 178 0.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 53708 # Bytes accessed per row activation +system.physmem.totQLat 5080719250 # Total ticks spent queuing +system.physmem.totMemAccLat 8752324250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 991730000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2679875000 # Total ticks spent accessing banks +system.physmem.avgQLat 25615.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13511.11 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 44126.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.08 # Average write queue length over time -system.physmem.readRowHits 181292 # Number of row buffer hits during reads -system.physmem.writeRowHits 98480 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.70 # Row buffer hit rate for writes -system.physmem.avgGap 15968328.89 # Average gap between requests -system.membus.throughput 4372413 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623536 # Transaction distribution -system.membus.trans_dist::ReadResp 623536 # Transaction distribution -system.membus.trans_dist::WriteReq 13773 # Transaction distribution -system.membus.trans_dist::WriteResp 13773 # Transaction distribution -system.membus.trans_dist::Writeback 126749 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2152 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution -system.membus.trans_dist::ReadExReq 159747 # Transaction distribution -system.membus.trans_dist::ReadExResp 159747 # Transaction distribution -system.membus.trans_dist::MessageReq 1654 # Transaction distribution -system.membus.trans_dist::MessageResp 1654 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.98 # Average write queue length when enqueuing +system.physmem.readRowHits 173438 # Number of row buffer hits during reads +system.physmem.writeRowHits 97917 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.26 # Row buffer hit rate for writes +system.physmem.avgGap 15982155.57 # Average gap between requests +system.physmem.pageHitRate 83.47 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.27 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 4365247 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623514 # Transaction distribution +system.membus.trans_dist::ReadResp 623514 # Transaction distribution +system.membus.trans_dist::WriteReq 13775 # Transaction distribution +system.membus.trans_dist::WriteResp 13775 # Transaction distribution +system.membus.trans_dist::Writeback 126733 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1634 # Transaction distribution +system.membus.trans_dist::ReadExReq 159484 # Transaction distribution +system.membus.trans_dist::ReadExResp 159484 # Transaction distribution +system.membus.trans_dist::MessageReq 1655 # Transaction distribution +system.membus.trans_dist::MessageResp 1655 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391769 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1582207 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 139016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1724531 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 139281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1724207 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14957248 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16623909 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5853056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5853056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22483581 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22483581 # Total data (bytes) -system.membus.snoop_data_through_bus 219200 # Total snoop data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14938368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16605037 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5870400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5870400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22482057 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22482057 # Total data (bytes) +system.membus.snoop_data_through_bus 201472 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 256796500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 359311000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 359316000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1350436000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1352149000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2614907754 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2612327754 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 428881000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 428873750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47507 # number of replacements -system.iocache.tags.tagsinuse 0.110729 # Cycle average of tags in use +system.iocache.tags.replacements 47501 # number of replacements +system.iocache.tags.tagsinuse 0.113099 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5049641350000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.110729 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006921 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006921 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses -system.iocache.ReadReq_misses::total 842 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5049776837000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.113099 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007069 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007069 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses -system.iocache.demand_misses::total 47562 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses -system.iocache.overall_misses::total 47562 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 148613936 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 148613936 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10808111078 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10808111078 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10956725014 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10956725014 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10956725014 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10956725014 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses +system.iocache.demand_misses::total 47556 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses +system.iocache.overall_misses::total 47556 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144134686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144134686 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12487439330 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12487439330 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 12631574016 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12631574016 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 12631574016 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12631574016 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -435,40 +451,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 176501.111639 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 176501.111639 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 231337.993964 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 231337.993964 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 230367.205206 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 230367.205206 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 230367.205206 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 230367.205206 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 172843 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 172409.911483 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 172409.911483 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267282.519906 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 267282.519906 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 265614.728236 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 265614.728236 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 216457 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 15866 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11594 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.893924 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 18.669743 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104797436 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104797436 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8377057578 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8377057578 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8481855014 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8481855014 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8481855014 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8481855014 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100637686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100637686 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 10056284830 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10056284830 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10156922516 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10156922516 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -477,14 +493,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 124462.513064 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 124462.513064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 179303.458433 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 179303.458433 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 178332.597746 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 178332.597746 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 178332.597746 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 178332.597746 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120380.007177 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 120380.007177 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215245.822560 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 215245.822560 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -498,13 +514,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 631773 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230147 # Transaction distribution -system.iobus.trans_dist::ReadResp 230147 # Transaction distribution +system.iobus.throughput 631264 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230141 # Transaction distribution +system.iobus.trans_dist::ReadResp 230141 # Transaction distribution system.iobus.trans_dist::WriteReq 57579 # Transaction distribution system.iobus.trans_dist::WriteResp 57579 # Transaction distribution -system.iobus.trans_dist::MessageReq 1654 # Transaction distribution -system.iobus.trans_dist::MessageResp 1654 # Transaction distribution +system.iobus.trans_dist::MessageReq 1655 # Transaction distribution +system.iobus.trans_dist::MessageResp 1655 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -524,11 +540,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578750 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -548,13 +564,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280340 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280340 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3946566 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3280296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280296 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3948164 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -590,87 +606,87 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424359014 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424033266 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53490000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52989250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.numCycles 10384555710 # number of cpu cycles simulated +system.cpu.numCycles 10392780360 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128336541 # Number of instructions committed -system.cpu.committedOps 247382226 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231975048 # Number of integer alu accesses +system.cpu.committedInsts 128334813 # Number of instructions committed +system.cpu.committedOps 247385808 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231978567 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299863 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23167946 # number of instructions that are conditional controls -system.cpu.num_int_insts 231975048 # number of integer instructions +system.cpu.num_func_calls 2299773 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23169265 # number of instructions that are conditional controls +system.cpu.num_int_insts 231978567 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434515715 # number of times the integer registers were read -system.cpu.num_int_register_writes 197846848 # number of times the integer registers were written +system.cpu.num_int_register_reads 434513747 # number of times the integer registers were read +system.cpu.num_int_register_writes 197852200 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132806307 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95529498 # number of times the CC registers were written -system.cpu.num_mem_refs 22249600 # number of memory refs -system.cpu.num_load_insts 13881232 # Number of load instructions -system.cpu.num_store_insts 8368368 # Number of store instructions -system.cpu.num_idle_cycles 9777359201.998117 # Number of idle cycles -system.cpu.num_busy_cycles 607196508.001883 # Number of busy cycles -system.cpu.not_idle_fraction 0.058471 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941529 # Percentage of idle cycles +system.cpu.num_cc_register_reads 132813019 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95534921 # number of times the CC registers were written +system.cpu.num_mem_refs 22245363 # number of memory refs +system.cpu.num_load_insts 13878746 # Number of load instructions +system.cpu.num_store_insts 8366617 # Number of store instructions +system.cpu.num_idle_cycles 9785238216.998117 # Number of idle cycles +system.cpu.num_busy_cycles 607542143.001883 # Number of busy cycles +system.cpu.not_idle_fraction 0.058458 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941542 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 792807 # number of replacements -system.cpu.icache.tags.tagsinuse 510.358419 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144581557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 793319 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.248953 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161241203250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.358419 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996794 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996794 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144581557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144581557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144581557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144581557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144581557 # number of overall hits -system.cpu.icache.overall_hits::total 144581557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 793326 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 793326 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 793326 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 793326 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 793326 # number of overall misses -system.cpu.icache.overall_misses::total 793326 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11210417756 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11210417756 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11210417756 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11210417756 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11210417756 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11210417756 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145374883 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145374883 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145374883 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145374883 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145374883 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145374883 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005457 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005457 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005457 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005457 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005457 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005457 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14130.909306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14130.909306 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14130.909306 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14130.909306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14130.909306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14130.909306 # average overall miss latency +system.cpu.icache.tags.replacements 788090 # number of replacements +system.cpu.icache.tags.tagsinuse 510.351939 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144584753 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 788602 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 183.343122 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161436066250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.351939 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996781 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144584753 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144584753 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144584753 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144584753 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144584753 # number of overall hits +system.cpu.icache.overall_hits::total 144584753 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 788609 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 788609 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 788609 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 788609 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 788609 # number of overall misses +system.cpu.icache.overall_misses::total 788609 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11107362758 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11107362758 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11107362758 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11107362758 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11107362758 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11107362758 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145373362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145373362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145373362 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145373362 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145373362 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145373362 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005425 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005425 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005425 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005425 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005425 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005425 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14084.752720 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14084.752720 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14084.752720 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14084.752720 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -679,80 +695,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793326 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793326 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793326 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793326 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793326 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793326 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9617488244 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9617488244 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9617488244 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9617488244 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9617488244 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9617488244 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005457 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005457 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005457 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12122.996402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12122.996402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12122.996402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12122.996402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12122.996402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12122.996402 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788609 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 788609 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 788609 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 788609 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 788609 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 788609 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9525299242 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9525299242 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9525299242 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9525299242 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9525299242 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9525299242 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005425 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005425 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005425 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12078.608337 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12078.608337 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3898 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.066238 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7439 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3908 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.903531 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5166941674000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066238 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191640 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191640 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7461 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7461 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 3741 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.069761 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7617 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3752 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.030117 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069761 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191860 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191860 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7617 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7617 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7463 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7463 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7463 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7463 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4754 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4754 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4754 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4754 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4754 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4754 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48555250 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48555250 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48555250 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 48555250 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48555250 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 48555250 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12215 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12215 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7619 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7619 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7619 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7619 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4604 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4604 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4604 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4604 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4604 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4604 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 44886750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 44886750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12217 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12217 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12217 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12217 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.389194 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.389194 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.389130 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.389130 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.389130 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.389130 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10213.557005 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10213.557005 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10213.557005 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376729 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376729 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376667 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.376667 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376667 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.376667 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9749.511295 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9749.511295 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9749.511295 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,78 +777,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 837 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 837 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4754 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4754 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4754 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4754 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4754 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4754 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39044750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39044750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39044750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39044750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39044750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39044750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.389194 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.389194 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.389130 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.389130 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.389130 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.389130 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8213.031132 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8213.031132 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 621 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 621 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4604 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4604 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4604 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4604 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4604 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4604 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35677750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35677750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35677750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35677750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35677750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35677750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376729 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376729 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376667 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376667 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7749.294092 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7667 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.048611 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13083 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7683 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.702850 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163398099000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.048611 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315538 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315538 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13083 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13083 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13083 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13083 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13083 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13083 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8874 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8874 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8874 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8874 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8874 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8874 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95939000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95939000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95939000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 95939000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95939000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 95939000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21957 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21957 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21957 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21957 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21957 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21957 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404154 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404154 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404154 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404154 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404154 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404154 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10811.246338 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10811.246338 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10811.246338 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 7948 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052475 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12793 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7961 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.606959 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052475 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315780 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315780 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12806 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12806 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12806 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12806 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12806 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12806 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9138 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9138 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9138 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9138 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9138 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9138 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97347500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97347500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97347500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 97347500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97347500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 97347500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21944 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21944 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21944 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21944 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21944 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21944 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.416424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.416424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.416424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.416424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.416424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.416424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10653.042241 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10653.042241 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10653.042241 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -841,90 +857,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2999 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2999 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8874 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8874 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8874 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8874 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8874 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 78190500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 78190500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 78190500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 78190500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 78190500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 78190500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404154 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404154 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404154 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8811.189993 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8811.189993 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8811.189993 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9138 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9138 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9138 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9138 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9138 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9138 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 79071000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 79071000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 79071000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 79071000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 79071000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 79071000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.416424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.416424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.416424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8652.987525 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622533 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997176 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20039030 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623045 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.346565 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 49459250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997176 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1621547 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997026 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20035701 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622059 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.352017 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 50992250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997026 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11994437 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11994437 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8042382 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8042382 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20036819 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20036819 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20036819 # number of overall hits -system.cpu.dcache.overall_hits::total 20036819 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309601 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309601 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315672 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315672 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1625273 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1625273 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1625273 # number of overall misses -system.cpu.dcache.overall_misses::total 1625273 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18886188795 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18886188795 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10748063695 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10748063695 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29634252490 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29634252490 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29634252490 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29634252490 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13304038 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13304038 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8358054 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8358054 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21662092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21662092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21662092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21662092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037769 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037769 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075028 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075028 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075028 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075028 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14421.330462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14421.330462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34048.200965 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34048.200965 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18233.399860 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18233.399860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18233.399860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18233.399860 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11993197 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11993197 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8040328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8040328 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20033525 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20033525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20033525 # number of overall hits +system.cpu.dcache.overall_hits::total 20033525 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308312 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308312 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315974 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315974 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624286 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624286 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624286 # number of overall misses +system.cpu.dcache.overall_misses::total 1624286 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18913909300 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18913909300 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11002078938 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11002078938 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29915988238 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29915988238 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29915988238 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29915988238 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13301509 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13301509 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8356302 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8356302 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21657811 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21657811 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21657811 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21657811 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098358 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098358 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14456.726912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14456.726912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34819.570401 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34819.570401 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18417.931471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18417.931471 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -933,46 +949,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539374 # number of writebacks -system.cpu.dcache.writebacks::total 1539374 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309601 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309601 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315672 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315672 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1625273 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1625273 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625273 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625273 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16253560205 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16253560205 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10061381305 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10061381305 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26314941510 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26314941510 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26314941510 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26314941510 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537247000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537247000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098436 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098436 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037769 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037769 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12411.078034 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12411.078034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31872.897517 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31872.897517 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16191.090057 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16191.090057 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16191.090057 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16191.090057 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1538973 # number of writebacks +system.cpu.dcache.writebacks::total 1538973 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308312 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308312 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315974 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315974 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1624286 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1624286 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624286 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624286 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16288101700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16288101700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10316379062 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10316379062 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26604480762 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26604480762 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26604480762 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26604480762 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214673000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214673000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537491500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537491500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752164500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752164500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098358 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098358 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12449.707486 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12449.707486 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32649.455531 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32649.455531 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -980,175 +996,175 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49299027 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2698843 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2698315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543210 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 360181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313477 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1586639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7593504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50772032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204036453 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 621184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 255690853 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255669733 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 304512 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3835424500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 49185341 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2692945 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2692419 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 360518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313820 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5977035 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8133 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7581359 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50470144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203948077 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 225856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 630272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 255274349 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 255253101 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 333120 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3831866500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 498000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1193127756 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1185336258 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3058413490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3054054238 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 7132250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6906500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13311250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13707250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 86950 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64733.250589 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3493106 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151616 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.039165 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86910 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64731.196890 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3488433 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151626 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.006826 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50239.194329 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.026648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3379.223326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11114.665027 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.766589 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50120.476905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.033461 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141258 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3445.447212 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.098054 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764778 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.051563 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169596 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987751 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6706 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 780407 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280531 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2070883 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543210 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543210 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 301 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 301 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200188 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200188 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6706 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3239 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 780407 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1480719 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2271071 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6706 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3239 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 780407 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1480719 # number of overall hits -system.cpu.l2cache.overall_hits::total 2271071 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052573 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.170366 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987720 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6740 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2903 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 775712 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1279207 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2064562 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1542700 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1542700 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 304 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 304 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6740 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2903 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 775712 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1479959 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2265314 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6740 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2903 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 775712 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1479959 # number of overall hits +system.cpu.l2cache.overall_hits::total 2265314 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12906 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28336 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41248 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1410 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1410 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113269 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113269 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12884 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28341 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41232 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1356 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1356 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113042 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113042 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12906 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141605 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154517 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12884 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141383 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154274 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12906 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141605 # number of overall misses -system.cpu.l2cache.overall_misses::total 154517 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 390250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1020078744 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2137913705 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3158471949 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16387856 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16387856 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7707092698 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7707092698 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 390250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1020078744 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9845006403 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10865564647 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 390250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1020078744 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9845006403 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10865564647 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6707 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3244 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 793313 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308867 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2112131 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1543210 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1543210 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1711 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1711 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313457 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313457 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6707 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3244 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 793313 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1622324 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2425588 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6707 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 793313 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1622324 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2425588 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000149 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001541 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016268 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021649 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019529 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.824079 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.824079 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361354 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.361354 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000149 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001541 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016268 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087285 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063703 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000149 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001541 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016268 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087285 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063703 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78050 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79039.109252 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75448.676772 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76572.729563 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11622.592908 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11622.592908 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68042.383159 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68042.383159 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78050 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79039.109252 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69524.426419 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70319.541843 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79039.109252 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69524.426419 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70319.541843 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 12884 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141383 # number of overall misses +system.cpu.l2cache.overall_misses::total 154274 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 136750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 347500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 979557242 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2186954200 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3166995692 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16260363 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 16260363 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7957275400 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7957275400 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 136750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 347500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 979557242 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10144229600 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11124271092 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 136750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 347500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 979557242 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10144229600 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11124271092 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6742 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2908 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 788596 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307548 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2105794 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1542700 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1542700 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1660 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1660 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313794 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313794 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6742 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2908 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 788596 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621342 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2419588 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6742 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2908 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 788596 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621342 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2419588 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000297 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001719 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016338 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021675 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019580 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.816867 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.816867 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360243 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.360243 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000297 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001719 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016338 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087201 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063760 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000297 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001719 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016338 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087201 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063760 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76028.969419 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77165.738682 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76809.169868 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11991.418142 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11991.418142 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70392.202898 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70392.202898 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76028.969419 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71749.995403 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72107.231886 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76028.969419 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71749.995403 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72107.231886 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1157,90 +1173,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80082 # number of writebacks -system.cpu.l2cache.writebacks::total 80082 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 80066 # number of writebacks +system.cpu.l2cache.writebacks::total 80066 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12906 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28336 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41248 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1410 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1410 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113269 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 113269 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12884 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28341 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41232 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1356 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1356 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113042 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113042 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12906 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141605 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154517 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12884 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141383 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154274 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12906 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141605 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154517 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 857244756 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1780461295 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2638108551 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14985893 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14985893 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6290141302 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6290141302 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 857244756 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8070602597 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8928249853 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 857244756 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8070602597 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8928249853 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026503500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026503500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021649 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019529 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.824079 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.824079 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087285 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063703 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087285 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063703 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66422.187820 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62833.896633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63957.247648 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10628.292908 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10628.292908 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55532.769796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55532.769796 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66422.187820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56993.768560 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57781.667085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66422.187820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56993.768560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57781.667085 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12884 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141383 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154274 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 111250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 818022758 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1831787800 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2650206808 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14478338 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14478338 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6543285600 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6543285600 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 111250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 285000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 818022758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8375073400 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9193492408 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 111250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 285000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 818022758 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8375073400 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9193492408 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370854000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370854000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026723500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026723500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816867 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816867 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087201 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063760 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087201 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063760 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63491.365880 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64633.844960 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64275.485254 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10677.240413 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10677.240413 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.668017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.668017 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63491.365880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59236.778113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59591.975369 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63491.365880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59236.778113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59591.975369 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index dde2aed4b..3b67933ac 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25046000 # Number of ticks simulated -final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25485000 # Number of ticks simulated +final_tick 25485000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22373 # Simulator instruction rate (inst/s) -host_op_rate 22372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87684145 # Simulator tick rate (ticks/s) -host_mem_usage 225308 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 27492 # Simulator instruction rate (inst/s) +host_op_rate 27490 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 109632626 # Simulator tick rate (ticks/s) +host_mem_usage 225100 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 29952 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25031500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 469 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 753384344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 421895232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1175279576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 753384344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 753384344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 753384344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 421895232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1175279576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65 # Per bank write bursts +system.physmem.perBankRdBursts::1 29 # Per bank write bursts +system.physmem.perBankRdBursts::2 27 # Per bank write bursts +system.physmem.perBankRdBursts::3 47 # Per bank write bursts +system.physmem.perBankRdBursts::4 41 # Per bank write bursts +system.physmem.perBankRdBursts::5 19 # Per bank write bursts +system.physmem.perBankRdBursts::6 1 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 19 # Per bank write bursts +system.physmem.perBankRdBursts::11 25 # Per bank write bursts +system.physmem.perBankRdBursts::12 15 # Per bank write bursts +system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::14 46 # Per bank write bursts +system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 25470500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 469 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -150,48 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation -system.physmem.totQLat 1857500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests -system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 7617500 # Total cycles spent in bank access -system.physmem.avgQLat 3960.55 # Average queueing delay per request -system.physmem.avgBankLat 16242.00 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25202.56 # Average memory access latency -system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.34 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.47 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 402 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.095238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.496730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.391602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 37 44.05% 44.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 14 16.67% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 5.95% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 5.95% 72.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 4.76% 77.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 5.95% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.19% 84.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.19% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.38% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.19% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.19% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 2 2.38% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.19% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 2 2.38% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 1.19% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.19% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 1.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation +system.physmem.totQLat 2272250 # Total ticks spent queuing +system.physmem.totMemAccLat 12262250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7645000 # Total ticks spent accessing banks +system.physmem.avgQLat 4844.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16300.64 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26145.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1177.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1177.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.20 # Data bus utilization in percentage +system.physmem.busUtilRead 9.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 385 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53372.07 # Average gap between requests -system.membus.throughput 1195879582 # Throughput (bytes/s) +system.physmem.avgGap 54308.10 # Average gap between requests +system.physmem.pageHitRate 82.09 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1175279576 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -202,10 +210,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 4374750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.2 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -248,7 +256,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 50093 # number of cpu cycles simulated +system.cpu.numCycles 50971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). @@ -270,12 +278,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11614 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43595 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. -system.cpu.activity 14.724612 # Percentage of cycles cpu is active +system.cpu.activity 14.470974 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -287,36 +295,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.976682 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.976682 # CPI: Total CPI of All Threads +system.cpu.ipc 0.125365 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.125365 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46047 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.660395 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47078 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.637676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46810 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.163465 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 49637 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.617174 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46513 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 8.746150 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.311081 # Cycle average of tags in use system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.311081 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069488 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -329,12 +337,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24550250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24550250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24550250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24550250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24550250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24550250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -347,12 +355,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69155.633803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69155.633803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69155.633803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69155.633803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69155.633803 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -373,26 +381,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20718250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20718250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20718250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20718250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20718250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20718250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68603.476821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68603.476821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68603.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68603.476821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1177790857 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -407,21 +415,21 @@ system.cpu.toL2Bus.data_through_bus 30016 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 508750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.093004 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.347593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.745411 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004344 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006076 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -439,17 +447,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20399750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27865000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4857750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4857750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20399750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12323000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32722750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20399750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12323000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32722750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -472,17 +480,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67773.255814 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78581.578947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70366.161616 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66544.520548 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66544.520548 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69771.321962 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67773.255814 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73351.190476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69771.321962 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,17 +510,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16625250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6283250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3954250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3954250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16625250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10237500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26862750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16625250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10237500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26862750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -524,27 +532,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55233.388704 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66139.473684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57849.747475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54167.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54167.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55233.388704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60937.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57276.652452 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.493430 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.493430 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025267 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025267 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -561,14 +569,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7909250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7909250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21376500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21376500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29285750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29285750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29285750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29285750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -585,19 +593,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81538.659794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81538.659794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61075.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61075.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65516.219239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65516.219239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65516.219239 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -617,14 +625,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7566750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7566750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4935250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4935250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12502000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12502000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12502000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12502000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -633,14 +641,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67606.164384 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67606.164384 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74416.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74416.666667 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 31fc74f80..0ff2f61a7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20671000 # Number of ticks simulated -final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21065000 # Number of ticks simulated +final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10783 # Simulator instruction rate (inst/s) -host_op_rate 10783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34979840 # Simulator tick rate (ticks/s) -host_mem_usage 229184 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host +host_inst_rate 31290 # Simulator instruction rate (inst/s) +host_op_rate 31288 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103426086 # Simulator tick rate (ticks/s) +host_mem_usage 226120 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 969087127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 538725751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1507812878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 969087127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 969087127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 31168 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20638000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 488 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 286 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 950961310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 528649418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479610729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950961310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950961310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950961310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 528649418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479610729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 488 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 69 # Per bank write bursts +system.physmem.perBankRdBursts::1 34 # Per bank write bursts +system.physmem.perBankRdBursts::2 32 # Per bank write bursts +system.physmem.perBankRdBursts::3 47 # Per bank write bursts +system.physmem.perBankRdBursts::4 43 # Per bank write bursts +system.physmem.perBankRdBursts::5 21 # Per bank write bursts +system.physmem.perBankRdBursts::6 1 # Per bank write bursts +system.physmem.perBankRdBursts::7 3 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 24 # Per bank write bursts +system.physmem.perBankRdBursts::12 14 # Per bank write bursts +system.physmem.perBankRdBursts::13 119 # Per bank write bursts +system.physmem.perBankRdBursts::14 45 # Per bank write bursts +system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21032000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 488 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,47 +152,54 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation -system.physmem.totQLat 2449250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12424250 # Sum of mem lat for all requests -system.physmem.totBusLat 2440000 # Total cycles spent in databus access -system.physmem.totBankLat 7535000 # Total cycles spent in bank access -system.physmem.avgQLat 5018.95 # Average queueing delay per request -system.physmem.avgBankLat 15440.57 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25459.53 # Average memory access latency -system.physmem.avgRdBW 1507.81 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1507.81 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.78 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.60 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 419 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 85 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.023529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.928934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 483.454089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 37 43.53% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 9.41% 52.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 10 11.76% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7 8.24% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 3.53% 76.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 2.35% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 2.35% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 4.71% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.18% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.18% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 2.35% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.18% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.18% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 3 3.53% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.18% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 1.18% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85 # Bytes accessed per row activation +system.physmem.totQLat 3258750 # Total ticks spent queuing +system.physmem.totMemAccLat 13288750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7590000 # Total ticks spent accessing banks +system.physmem.avgQLat 6677.77 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15553.28 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27231.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1482.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1482.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.58 # Data bus utilization in percentage +system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 403 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42290.98 # Average gap between requests -system.membus.throughput 1507812878 # Throughput (bytes/s) +system.physmem.avgGap 43098.36 # Average gap between requests +system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1479610729 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -201,39 +210,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4561500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu.branchPred.lookups 2888 # Number of BP lookups -system.cpu.branchPred.condPredicted 1700 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 619000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.cpu.branchPred.lookups 2884 # Number of BP lookups +system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups -system.cpu.branchPred.BTBHits 757 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups +system.cpu.branchPred.BTBHits 756 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.393458 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 418 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.363636 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2082 # DTB read hits +system.cpu.dtb.read_hits 2076 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2129 # DTB read accesses +system.cpu.dtb.read_accesses 2123 # DTB read accesses system.cpu.dtb.write_hits 1063 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1094 # DTB write accesses -system.cpu.dtb.data_hits 3145 # DTB hits +system.cpu.dtb.data_hits 3139 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3223 # DTB accesses -system.cpu.itb.fetch_hits 2387 # ITB hits +system.cpu.dtb.data_accesses 3217 # DTB accesses +system.cpu.itb.fetch_hits 2382 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2426 # ITB accesses +system.cpu.itb.fetch_accesses 2421 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -247,178 +256,178 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41343 # number of cpu cycles simulated +system.cpu.numCycles 42131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16592 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2888 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1175 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1903 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1523 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.100776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.497742 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12103 80.30% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.11% 82.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 215 1.43% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 257 1.71% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.60% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 184 1.22% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1257 8.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.069855 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.401325 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9323 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1686 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2764 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1220 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 1219 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15336 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15308 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1220 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9534 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 784 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.SquashCycles 1219 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 808 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2623 # Number of cycles rename is running system.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14625 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 14604 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18241 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18225 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18216 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6381 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 808 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2766 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12962 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12953 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10771 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6234 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3598 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15073 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.715651 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.357561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.712698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.354769 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10531 69.87% 69.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1674 11.11% 80.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1174 7.79% 88.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 731 4.85% 93.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 498 3.30% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 271 1.80% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10572 69.95% 69.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1678 11.10% 81.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1174 7.77% 88.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 728 4.82% 93.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 498 3.30% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 1.79% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 15 13.27% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 60 53.10% 66.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 33.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7249 67.20% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2400 22.25% 89.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1133 10.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7236 67.18% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2397 22.25% 89.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1133 10.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10787 # Type of FU issued -system.cpu.iq.rate 0.260915 # Inst issue rate -system.cpu.iq.fu_busy_cnt 113 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36793 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19230 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10771 # Type of FU issued +system.cpu.iq.rate 0.255655 # Inst issue rate +system.cpu.iq.fu_busy_cnt 112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010398 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19167 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9598 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10887 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10870 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1583 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed @@ -427,57 +436,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1220 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1219 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 264 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 13071 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2766 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 700 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 381 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10067 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 704 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3236 # number of memory reference insts executed -system.cpu.iew.exec_branches 1591 # Number of branches executed +system.cpu.iew.exec_refs 3230 # number of memory reference insts executed +system.cpu.iew.exec_branches 1588 # Number of branches executed system.cpu.iew.exec_stores 1096 # Number of stores executed -system.cpu.iew.exec_rate 0.243983 # Inst execution rate -system.cpu.iew.wb_sent 9767 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9625 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5058 # num instructions producing a value -system.cpu.iew.wb_consumers 6775 # num instructions consuming a value +system.cpu.iew.exec_rate 0.238945 # Inst execution rate +system.cpu.iew.wb_sent 9751 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9608 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5048 # num instructions producing a value +system.cpu.iew.wb_consumers 6764 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.232808 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.746568 # average fanout of values written-back +system.cpu.iew.wb_rate 0.228051 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.746304 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6689 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6680 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13853 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.461200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13894 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.459839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11035 79.66% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1522 10.99% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 530 3.83% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 235 1.70% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.06% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.78% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 103 0.74% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.20% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 145 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11073 79.70% 79.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1524 10.97% 90.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 530 3.81% 94.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.69% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.07% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 0.79% 98.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 103 0.74% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.20% 98.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13894 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -488,26 +497,26 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26435 # The number of ROB reads -system.cpu.rob.rob_writes 27385 # The number of ROB writes -system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26469 # The number of ROB reads +system.cpu.rob.rob_writes 27366 # The number of ROB writes +system.cpu.timesIdled 271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27018 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.488230 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.488230 # CPI: Total CPI of All Threads -system.cpu.ipc 0.154125 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.154125 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12801 # number of integer regfile reads -system.cpu.int_regfile_writes 7277 # number of integer regfile writes +system.cpu.cpi 6.611896 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.611896 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12780 # number of integer regfile reads +system.cpu.int_regfile_writes 7264 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1510909003 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1482648944 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -522,55 +531,55 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 531250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 278500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.548856 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1893 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.028662 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits -system.cpu.icache.overall_hits::total 1898 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 159.548856 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077905 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1893 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1893 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1893 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1893 # number of overall hits +system.cpu.icache.overall_hits::total 1893 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses system.cpu.icache.overall_misses::total 489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30301750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30301750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30301750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30301750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30301750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30301750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61966.768916 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61966.768916 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61966.768916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61966.768916 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31381500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31381500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31381500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31381500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31381500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31381500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2382 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2382 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2382 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2382 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2382 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205290 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.205290 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.205290 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.205290 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.205290 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.205290 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64174.846626 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64174.846626 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64174.846626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64174.846626 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,36 +600,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21363250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21363250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21363250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21363250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21363250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21363250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67819.841270 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67819.841270 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22109000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22109000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22109000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22109000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22109000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22109000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132242 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.132242 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.132242 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70187.301587 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70187.301587 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.420292 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.632644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.787647 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006696 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -638,17 +647,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21037250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7945250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28982500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5109500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5109500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21037250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13054750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34092000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21037250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13054750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34092000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21783000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29501750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5390750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5390750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21783000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13109500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21783000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13109500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34892500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -671,17 +680,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66997.611465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78665.841584 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69837.349398 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69993.150685 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69993.150685 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69860.655738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69860.655738 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69372.611465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76423.267327 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71088.554217 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73845.890411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73845.890411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71501.024590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71501.024590 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -701,17 +710,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17080250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6700750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23781000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17080250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10908750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27989000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17080250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10908750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27989000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17830500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6478250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4491250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4491250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17830500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10969500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17830500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -723,35 +732,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54395.700637 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66344.059406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57303.614458 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56785.031847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64141.089109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58575.301205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61523.972603 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61523.972603 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.351368 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 107.351368 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026209 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits -system.cpu.dcache.overall_hits::total 2236 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits +system.cpu.dcache.overall_hits::total 2230 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -760,43 +769,43 @@ system.cpu.dcache.demand_misses::cpu.data 529 # n system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses system.cpu.dcache.overall_misses::total 529 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11600250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11600250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21979228 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21979228 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33579478 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33579478 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33579478 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33579478 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1900 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1900 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11435000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11435000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23196228 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23196228 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34631228 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34631228 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34631228 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34631228 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2765 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2765 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2765 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2765 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089474 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.089474 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.089757 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191320 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.191320 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191320 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.191320 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68236.764706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68236.764706 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61223.476323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61223.476323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63477.274102 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63477.274102 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1567 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.191736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67264.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67264.705882 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64613.448468 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64613.448468 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65465.459357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65465.459357 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.484848 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.030303 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -816,30 +825,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8053750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8053750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13239250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13239250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13239250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13239250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053158 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053158 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7827250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7827250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13294000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13294000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79740.099010 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79740.099010 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71034.246575 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71034.246575 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77497.524752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77497.524752 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74886.986301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74886.986301 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 2906fdf0c..5e19e4b84 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11933500 # Number of ticks simulated -final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11990500 # Number of ticks simulated +final_tick 11990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3639 # Simulator instruction rate (inst/s) -host_op_rate 3638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18189727 # Simulator tick rate (ticks/s) -host_mem_usage 227880 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host +host_inst_rate 47015 # Simulator instruction rate (inst/s) +host_op_rate 46988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 235942636 # Simulator tick rate (ticks/s) +host_mem_usage 225832 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1008254075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455859555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1464113630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1008254075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1008254075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 273 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 273 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 17472 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 11844000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 273 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.bw_read::cpu.inst 1003461073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 453692507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1457153580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1003461073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1003461073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1003461073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 453692507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1457153580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 273 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 17472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 17472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 2 # Per bank write bursts +system.physmem.perBankRdBursts::3 24 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 24 # Per bank write bursts +system.physmem.perBankRdBursts::7 37 # Per bank write bursts +system.physmem.perBankRdBursts::8 61 # Per bank write bursts +system.physmem.perBankRdBursts::9 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 14 # Per bank write bursts +system.physmem.perBankRdBursts::11 9 # Per bank write bursts +system.physmem.perBankRdBursts::12 17 # Per bank write bursts +system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::14 12 # Per bank write bursts +system.physmem.perBankRdBursts::15 1 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 11901000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 273 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,43 +152,51 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation -system.physmem.totQLat 1190000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6735000 # Sum of mem lat for all requests -system.physmem.totBusLat 1365000 # Total cycles spent in databus access -system.physmem.totBankLat 4180000 # Total cycles spent in bank access -system.physmem.avgQLat 4358.97 # Average queueing delay per request -system.physmem.avgBankLat 15311.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24670.33 # Average memory access latency -system.physmem.avgRdBW 1464.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1464.11 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.44 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.56 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 240 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 42 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.809524 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.784505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 471.889985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 23 54.76% 54.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 1 2.38% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 3 7.14% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 1 2.38% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 4.76% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 4.76% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 2.38% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 4.76% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 2.38% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1 2.38% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 2.38% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 2.38% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 2.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42 # Bytes accessed per row activation +system.physmem.totQLat 1695750 # Total ticks spent queuing +system.physmem.totMemAccLat 7213250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1365000 # Total ticks spent in databus transfers +system.physmem.totBankLat 4152500 # Total ticks spent accessing banks +system.physmem.avgQLat 6211.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15210.62 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26422.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1457.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1457.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.38 # Data bus utilization in percentage +system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.60 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 231 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43384.62 # Average gap between requests -system.membus.throughput 1464113630 # Throughput (bytes/s) +system.physmem.avgGap 43593.41 # Average gap between requests +system.physmem.pageHitRate 84.62 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.18 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1457153580 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 249 # Transaction distribution system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution @@ -199,10 +209,10 @@ system.membus.data_through_bus 17472 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) -system.cpu.branchPred.lookups 1175 # Number of BP lookups -system.cpu.branchPred.condPredicted 618 # Number of conditional branches predicted +system.membus.respLayer1.occupancy 2551500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.3 # Layer utilization (%) +system.cpu.branchPred.lookups 1176 # Number of BP lookups +system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups system.cpu.branchPred.BTBHits 253 # Number of BTB hits @@ -218,18 +228,18 @@ system.cpu.dtb.read_hits 707 # DT system.cpu.dtb.read_misses 31 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations system.cpu.dtb.read_accesses 738 # DTB read accesses -system.cpu.dtb.write_hits 371 # DTB write hits +system.cpu.dtb.write_hits 368 # DTB write hits system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 391 # DTB write accesses -system.cpu.dtb.data_hits 1078 # DTB hits +system.cpu.dtb.write_accesses 388 # DTB write accesses +system.cpu.dtb.data_hits 1075 # DTB hits system.cpu.dtb.data_misses 51 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1129 # DTB accesses -system.cpu.itb.fetch_hits 1067 # ITB hits +system.cpu.dtb.data_accesses 1126 # DTB accesses +system.cpu.itb.fetch_hits 1065 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1097 # ITB accesses +system.cpu.itb.fetch_accesses 1095 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -243,96 +253,96 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23868 # number of cpu cycles simulated +system.cpu.numCycles 23982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4327 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7029 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1175 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 4347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1212 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1118 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 189 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.900807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.307084 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.908161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.314945 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6591 84.47% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.68% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 115 1.47% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.22% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 179 2.29% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 74 0.95% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 64 0.82% 91.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.83% 92.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 567 7.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6511 84.34% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.69% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.49% 86.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.23% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 2.28% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 76 0.98% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.83% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.84% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049229 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.294495 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5563 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1156 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 7720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049037 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.292344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 579 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1153 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 498 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6218 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5662 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5584 # Number of cycles rename is idle system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1065 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1062 # Number of cycles rename is running system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5911 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 5897 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6679 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 4276 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6670 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6663 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2508 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 955 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 468 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4973 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4960 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4046 # Number of instructions issued +system.cpu.iq.iqInstsIssued 4040 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2348 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1391 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1384 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.518519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.233664 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.523316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.238697 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6178 79.17% 79.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 567 7.27% 86.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 400 5.13% 91.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.37% 94.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 2.55% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.55% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47 0.60% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6098 78.99% 78.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 566 7.33% 86.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 399 5.17% 91.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 262 3.39% 94.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 2.58% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 1.57% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7720 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available @@ -368,69 +378,69 @@ system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2864 70.79% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 783 19.35% 90.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 398 9.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2861 70.82% 70.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 783 19.38% 90.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 395 9.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4046 # Type of FU issued -system.cpu.iq.rate 0.169516 # Inst issue rate +system.cpu.iq.FU_type_0::total 4040 # Type of FU issued +system.cpu.iq.rate 0.168460 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010875 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15980 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7325 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15885 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7299 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3649 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4083 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4077 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 540 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 177 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 174 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 498 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5317 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 5302 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 955 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 468 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -438,43 +448,43 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 3849 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1130 # number of memory reference insts executed -system.cpu.iew.exec_branches 644 # Number of branches executed -system.cpu.iew.exec_stores 391 # Number of stores executed -system.cpu.iew.exec_rate 0.161513 # Inst execution rate -system.cpu.iew.wb_sent 3741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3661 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1709 # num instructions producing a value -system.cpu.iew.wb_consumers 2209 # num instructions consuming a value +system.cpu.iew.exec_nop 336 # number of nop insts executed +system.cpu.iew.exec_refs 1127 # number of memory reference insts executed +system.cpu.iew.exec_branches 643 # Number of branches executed +system.cpu.iew.exec_stores 388 # Number of stores executed +system.cpu.iew.exec_rate 0.160495 # Inst execution rate +system.cpu.iew.wb_sent 3735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1708 # num instructions producing a value +system.cpu.iew.wb_consumers 2206 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.153385 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.773653 # average fanout of values written-back +system.cpu.iew.wb_rate 0.152406 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.774252 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2732 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2720 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7305 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.352635 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.192667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 7226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.356490 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.198597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6436 88.10% 88.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204 2.79% 90.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 308 4.22% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 114 1.56% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 0.99% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 51 0.70% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.44% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 25 0.34% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 63 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6357 87.97% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.82% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.26% 95.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.58% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.00% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 51 0.71% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 25 0.35% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7305 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7226 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,23 +497,23 @@ system.cpu.commit.int_insts 2367 # Nu system.cpu.commit.function_calls 71 # Number of function calls committed. system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12303 # The number of ROB reads -system.cpu.rob.rob_writes 11127 # The number of ROB writes -system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16065 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12212 # The number of ROB reads +system.cpu.rob.rob_writes 11099 # The number of ROB writes +system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16262 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 9.999162 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.999162 # CPI: Total CPI of All Threads -system.cpu.ipc 0.100008 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.100008 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4674 # number of integer regfile reads -system.cpu.int_regfile_writes 2826 # number of integer regfile writes +system.cpu.cpi 10.046921 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.046921 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099533 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099533 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4665 # number of integer regfile reads +system.cpu.int_regfile_writes 2823 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1464113630 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1457153580 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -518,55 +528,55 @@ system.cpu.toL2Bus.data_through_bus 17472 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 318000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 316000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.523450 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 93.236237 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.340426 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.523450 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044689 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044689 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 816 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 816 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 816 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 816 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 816 # number of overall hits -system.cpu.icache.overall_hits::total 816 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 251 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 251 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 251 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 251 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 251 # number of overall misses -system.cpu.icache.overall_misses::total 251 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16843749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16843749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16843749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16843749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16843749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16843749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235239 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.235239 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.235239 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.235239 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.235239 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.235239 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67106.569721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67106.569721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67106.569721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67106.569721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67106.569721 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 93.236237 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.045526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.045526 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 815 # number of overall hits +system.cpu.icache.overall_hits::total 815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17655999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17655999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17655999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17655999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17655999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17655999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1065 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1065 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1065 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234742 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234742 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70623.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70623.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70623.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70623.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70623.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -575,48 +585,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 56 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12795749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12795749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12795749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12795749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12795749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12795749 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176195 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.176195 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176195 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.176195 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68062.494681 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68062.494681 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68062.494681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68062.494681 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13162749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13162749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13162749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13162749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13162749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13162749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70014.622340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70014.622340 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70014.622340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70014.622340 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 119.912589 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 122.122128 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.722261 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.190328 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002799 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000860 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003659 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.433851 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.688277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002851 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003727 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -628,17 +638,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12607000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4547250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17154250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1720750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1720750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12607000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6268000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18875000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12607000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6268000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18875000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4692750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17666750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1665750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1665750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6358500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19332500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6358500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19332500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -661,17 +671,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67058.510638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74545.081967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68892.570281 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71697.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71697.916667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69139.194139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67058.510638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73741.176471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69139.194139 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69010.638298 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76930.327869 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70950.803213 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69406.250000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69406.250000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70815.018315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.638298 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74805.882353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70815.018315 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,17 +701,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10234500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3797750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14032250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1425250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1425250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10234500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15457500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10234500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15457500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10604500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3946250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14550750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1371750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1371750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10604500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10604500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5318000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15922500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -713,27 +723,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54438.829787 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62258.196721 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56354.417671 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59385.416667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59385.416667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56406.914894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64692.622951 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58436.746988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57156.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57156.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.914894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62564.705882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58324.175824 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.667407 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.667407 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011149 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011149 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits @@ -750,14 +760,14 @@ system.cpu.dcache.demand_misses::cpu.data 194 # n system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses system.cpu.dcache.overall_misses::total 194 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7467750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7467750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5336000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5336000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12803750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12803750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12803750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12803750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7226000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7226000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5211250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5211250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12437250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12437250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12437250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12437250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -774,14 +784,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66086.283186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66086.283186 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65876.543210 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65876.543210 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65998.711340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65998.711340 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63946.902655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63946.902655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64336.419753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64336.419753 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64109.536082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64109.536082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64109.536082 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -806,14 +816,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4608250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4608250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1746250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1746250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6354500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6354500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6354500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6354500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4753750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4753750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1691250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1691250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6445000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6445000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6445000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6445000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -822,14 +832,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75545.081967 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75545.081967 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72760.416667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72760.416667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77930.327869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77930.327869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75823.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75823.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ca5a55de6..6f535bcb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16494000 # Number of ticks simulated -final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16981000 # Number of ticks simulated +final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19652 # Simulator instruction rate (inst/s) -host_op_rate 24522 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70593484 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 41552 # Simulator instruction rate (inst/s) +host_op_rate 51840 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153628168 # Simulator tick rate (ticks/s) +host_mem_usage 240508 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 25152 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16436500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 393 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.num_reads::total 392 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::2 20 # Per bank write bursts +system.physmem.perBankRdBursts::3 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 17 # Per bank write bursts +system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::6 35 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 28 # Per bank write bursts +system.physmem.perBankRdBursts::11 42 # Per bank write bursts +system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 16923500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -150,68 +152,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2047500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests -system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5445000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.92 # Average queueing delay per request -system.physmem.avgBankLat 13854.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24064.89 # Average memory access latency -system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.91 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 3153000 # Total ticks spent queuing +system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5403750 # Total ticks spent accessing banks +system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41823.16 # Average gap between requests -system.membus.throughput 1524918152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 352 # Transaction distribution -system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.physmem.avgGap 43172.19 # Average gap between requests +system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1473647017 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.3 # Layer utilization (%) -system.cpu.branchPred.lookups 2479 # Number of BP lookups -system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2481 # Number of BP lookups +system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits @@ -302,179 +312,179 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32989 # number of cpu cycles simulated +system.cpu.numCycles 33963 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2221 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2227 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8917 # Type of FU issued -system.cpu.iq.rate 0.270302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.262668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -482,55 +492,55 @@ system.cpu.iew.lsq.thread0.cacheBlocked 3 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_refs 3299 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.258268 # Inst execution rate -system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8067 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3881 # num instructions producing a value -system.cpu.iew.wb_consumers 7779 # num instructions consuming a value +system.cpu.iew.exec_rate 0.250950 # Inst execution rate +system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3883 # num instructions producing a value +system.cpu.iew.wb_consumers 7788 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -541,93 +551,93 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23271 # The number of ROB reads -system.cpu.rob.rob_writes 23399 # The number of ROB writes -system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23234 # The number of ROB reads +system.cpu.rob.rob_writes 23415 # The number of ROB writes +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39193 # number of integer regfile reads -system.cpu.int_regfile_writes 7983 # number of integer regfile writes +system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2975 # number of misc regfile reads +system.cpu.misc_regfile_reads 2977 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits -system.cpu.icache.overall_hits::total 1583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits +system.cpu.icache.overall_hits::total 1584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -637,42 +647,42 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 73 system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -682,61 +692,61 @@ system.cpu.l2cache.demand_hits::total 40 # nu system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses +system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 397 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,124 +761,124 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses +system.cpu.dcache.overall_misses::total 496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -877,16 +887,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -895,30 +905,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index add5a91d0..1007daea2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16494000 # Number of ticks simulated -final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16981000 # Number of ticks simulated +final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22159 # Simulator instruction rate (inst/s) -host_op_rate 27650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79599293 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 59313 # Simulator instruction rate (inst/s) +host_op_rate 73997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219275591 # Simulator tick rate (ticks/s) +host_mem_usage 240508 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 25152 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16436500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 393 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.num_reads::total 392 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::2 20 # Per bank write bursts +system.physmem.perBankRdBursts::3 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 17 # Per bank write bursts +system.physmem.perBankRdBursts::5 34 # Per bank write bursts +system.physmem.perBankRdBursts::6 35 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 28 # Per bank write bursts +system.physmem.perBankRdBursts::11 42 # Per bank write bursts +system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 16923500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -150,68 +152,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2047500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests -system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5445000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.92 # Average queueing delay per request -system.physmem.avgBankLat 13854.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24064.89 # Average memory access latency -system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.91 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 3153000 # Total ticks spent queuing +system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5403750 # Total ticks spent accessing banks +system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41823.16 # Average gap between requests -system.membus.throughput 1524918152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 352 # Transaction distribution -system.membus.trans_dist::ReadResp 352 # Transaction distribution +system.physmem.avgGap 43172.19 # Average gap between requests +system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1473647017 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.3 # Layer utilization (%) -system.cpu.branchPred.lookups 2479 # Number of BP lookups -system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2481 # Number of BP lookups +system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -257,179 +267,179 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32989 # number of cpu cycles simulated +system.cpu.numCycles 33963 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2426 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2221 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2227 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8917 # Type of FU issued -system.cpu.iq.rate 0.270302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8921 # Type of FU issued +system.cpu.iq.rate 0.262668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -437,55 +447,55 @@ system.cpu.iew.lsq.thread0.cacheBlocked 3 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_refs 3299 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.258268 # Inst execution rate -system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8067 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3881 # num instructions producing a value -system.cpu.iew.wb_consumers 7779 # num instructions consuming a value +system.cpu.iew.exec_rate 0.250950 # Inst execution rate +system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3883 # num instructions producing a value +system.cpu.iew.wb_consumers 7788 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -496,93 +506,93 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23271 # The number of ROB reads -system.cpu.rob.rob_writes 23399 # The number of ROB writes -system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23234 # The number of ROB reads +system.cpu.rob.rob_writes 23415 # The number of ROB writes +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39193 # number of integer regfile reads -system.cpu.int_regfile_writes 7983 # number of integer regfile writes +system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2975 # number of misc regfile reads +system.cpu.misc_regfile_reads 2977 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits -system.cpu.icache.overall_hits::total 1583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits +system.cpu.icache.overall_hits::total 1584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -592,42 +602,42 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 73 system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -637,61 +647,61 @@ system.cpu.l2cache.demand_hits::total 40 # nu system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses +system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 397 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -706,124 +716,124 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits -system.cpu.dcache.overall_hits::total 2369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses +system.cpu.dcache.overall_misses::total 496 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -832,16 +842,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -850,30 +860,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index aeb0e2e25..3c2a96518 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24587000 # Number of ticks simulated -final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24975000 # Number of ticks simulated +final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52979 # Simulator instruction rate (inst/s) -host_op_rate 52966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 223940501 # Simulator tick rate (ticks/s) -host_mem_usage 224928 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 84511 # Simulator instruction rate (inst/s) +host_op_rate 84494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 362882134 # Simulator tick rate (ticks/s) +host_mem_usage 254488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,77 +19,79 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 825151503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359214219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1184365722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 825151503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 825151503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 455 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 455 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 29120 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24519000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 455 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 455 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 29120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 29120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 0 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 8 # Per bank write bursts +system.physmem.perBankRdBursts::5 3 # Per bank write bursts +system.physmem.perBankRdBursts::6 12 # Per bank write bursts +system.physmem.perBankRdBursts::7 51 # Per bank write bursts +system.physmem.perBankRdBursts::8 59 # Per bank write bursts +system.physmem.perBankRdBursts::9 75 # Per bank write bursts +system.physmem.perBankRdBursts::10 36 # Per bank write bursts +system.physmem.perBankRdBursts::11 19 # Per bank write bursts +system.physmem.perBankRdBursts::12 52 # Per bank write bursts +system.physmem.perBankRdBursts::13 28 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24894000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 455 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,48 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation -system.physmem.totQLat 2305250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12775250 # Sum of mem lat for all requests -system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 8195000 # Total cycles spent in bank access -system.physmem.avgQLat 5066.48 # Average queueing delay per request -system.physmem.avgBankLat 18010.99 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28077.47 # Average memory access latency -system.physmem.avgRdBW 1184.37 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1184.37 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.25 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.52 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 361 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.831776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.727359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.380874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 36 33.64% 33.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 20 18.69% 52.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 15 14.02% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 8.41% 74.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 3.74% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 8 7.48% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 0.93% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 3.74% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.87% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.87% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.87% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 0.93% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.93% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.93% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 0.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 107 # Bytes accessed per row activation +system.physmem.totQLat 3167500 # Total ticks spent queuing +system.physmem.totMemAccLat 13555000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8112500 # Total ticks spent accessing banks +system.physmem.avgQLat 6961.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 17829.67 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29791.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.11 # Data bus utilization in percentage +system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.54 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53887.91 # Average gap between requests -system.membus.throughput 1184365722 # Throughput (bytes/s) +system.physmem.avgGap 54712.09 # Average gap between requests +system.physmem.pageHitRate 76.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1165965966 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -202,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4266000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.4 # Layer utilization (%) -system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.membus.respLayer1.occupancy 4260750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.1 # Layer utilization (%) +system.cpu.branchPred.lookups 1156 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 879 # Number of BTB lookups system.cpu.branchPred.BTBHits 339 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.566553 # BTB Hit Percentage system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -234,14 +240,14 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49175 # number of cpu cycles simulated +system.cpu.numCycles 49951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 724 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5088 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8484 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File @@ -256,12 +262,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43792 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.946619 # Percentage of cycles cpu is active +system.cpu.activity 10.776561 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -273,36 +279,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.458032 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.458032 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118231 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads +system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.118231 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45525 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.422471 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46361 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.722420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46410 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.622776 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47937 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 47185 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 5.537427 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.517539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47060 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2891 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.787672 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.636983 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.636983 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073553 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073553 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -315,12 +321,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25010250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25010250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25010250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25010250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25010250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25010250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25425500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25425500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25425500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25425500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25425500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -333,12 +339,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71457.857143 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71457.857143 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71457.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71457.857143 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72644.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72644.285714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,26 +365,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22679000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22679000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23091000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23091000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23091000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23091000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71094.043887 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71094.043887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1189571725 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -393,21 +399,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 543000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 538500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 225750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.420638 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.318425 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.102213 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004648 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006360 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -425,17 +431,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6742000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29075500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3650000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3650000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22333500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32725500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22333500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32725500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22745500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6874750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29620250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3847000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3847000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22745500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10721750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33467250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22745500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10721750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33467250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -458,17 +464,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70452.681388 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77494.252874 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71969.059406 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71568.627451 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71568.627451 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71924.175824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71924.175824 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,17 +494,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18342000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5661000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24003000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18342000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8667000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27009000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18342000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8667000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27009000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18763000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5795250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24558250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18763000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8999750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27762750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18763000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8999750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27762750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -510,27 +516,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57861.198738 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59413.366337 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.339752 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.339752 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022056 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022056 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits @@ -547,14 +553,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7523000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7523000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21590750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21590750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29113750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29113750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29113750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29113750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7659250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7659250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21762250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21762250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29421500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29421500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29421500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -571,14 +577,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77556.701031 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77556.701031 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61163.597734 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61163.597734 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64697.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64697.222222 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65381.111111 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65381.111111 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -603,14 +609,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3704000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3704000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10539500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10539500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10539500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10539500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6968250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6968250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3901000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3901000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10869250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10869250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10869250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10869250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -619,14 +625,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78568.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78568.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72627.450980 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 423a70e1a..1c2de0612 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21805500 # Number of ticks simulated -final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21898500 # Number of ticks simulated +final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31004 # Simulator instruction rate (inst/s) -host_op_rate 31001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131093072 # Simulator tick rate (ticks/s) -host_mem_usage 229800 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 64871 # Simulator instruction rate (inst/s) +host_op_rate 64859 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 275425114 # Simulator tick rate (ticks/s) +host_mem_usage 255508 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30528 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 21726000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 477 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 979062493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 415005594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1394068087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 979062493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 979062493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 979062493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 415005594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1394068087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 477 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 30 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 1 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 7 # Per bank write bursts +system.physmem.perBankRdBursts::5 3 # Per bank write bursts +system.physmem.perBankRdBursts::6 13 # Per bank write bursts +system.physmem.perBankRdBursts::7 54 # Per bank write bursts +system.physmem.perBankRdBursts::8 63 # Per bank write bursts +system.physmem.perBankRdBursts::9 77 # Per bank write bursts +system.physmem.perBankRdBursts::10 44 # Per bank write bursts +system.physmem.perBankRdBursts::11 20 # Per bank write bursts +system.physmem.perBankRdBursts::12 51 # Per bank write bursts +system.physmem.perBankRdBursts::13 29 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts +system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21819000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 477 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,47 +152,52 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.708738 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.390708 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.503517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 2.91% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3 2.91% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 2353250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13414500 # Sum of mem lat for all requests -system.physmem.totBusLat 2385000 # Total cycles spent in databus access -system.physmem.totBankLat 8676250 # Total cycles spent in bank access -system.physmem.avgQLat 4933.44 # Average queueing delay per request -system.physmem.avgBankLat 18189.20 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28122.64 # Average memory access latency -system.physmem.avgRdBW 1400.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1400.01 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.94 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.62 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 374 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.508475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.858901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.434070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 46 38.98% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 20 16.95% 55.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 19 16.10% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 8 6.78% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 7 5.93% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.54% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 3.39% 90.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 1.69% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 1.69% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.85% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 0.85% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 0.85% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.69% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 0.85% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 118 # Bytes accessed per row activation +system.physmem.totQLat 2620250 # Total ticks spent queuing +system.physmem.totMemAccLat 13667750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8662500 # Total ticks spent accessing banks +system.physmem.avgQLat 5493.19 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18160.38 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28653.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1394.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1394.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.89 # Data bus utilization in percentage +system.physmem.busUtilRead 10.89 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45547.17 # Average gap between requests -system.membus.throughput 1400013758 # Throughput (bytes/s) +system.physmem.avgGap 45742.14 # Average gap between requests +system.physmem.pageHitRate 75.26 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1394068087 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 426 # Transaction distribution system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -201,17 +208,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.5 # Layer utilization (%) -system.cpu.branchPred.lookups 2187 # Number of BP lookups +system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1664 # Number of BTB lookups -system.cpu.branchPred.BTBHits 502 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups +system.cpu.branchPred.BTBHits 492 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.168269 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -233,94 +240,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43612 # number of cpu cycles simulated +system.cpu.numCycles 43798 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13212 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2187 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1384 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1326 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8822 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1344 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1985 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.912746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.223376 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.913456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.225567 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11245 77.69% 77.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1331 9.20% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.91% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.11% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.82% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 150 1.04% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 933 6.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11219 77.74% 77.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1317 9.13% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.91% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 115 0.80% 91.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 150 1.04% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 933 6.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14475 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050147 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.302944 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8926 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1578 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3043 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3026 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 875 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12329 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 875 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9108 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 901 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2916 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2899 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11899 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13887 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2460 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8306 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3428 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2082 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14475 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.573817 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.241522 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14432 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.574626 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.242806 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10881 75.17% 75.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1431 9.89% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 893 6.17% 91.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 3.82% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.46% 97.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.55% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.61% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10849 75.17% 75.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1422 9.85% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 6.17% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.83% 95.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 355 2.46% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.57% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 89 0.62% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14432 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available @@ -356,68 +363,68 @@ system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4943 59.51% 59.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2250 27.09% 86.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8306 # Type of FU issued -system.cpu.iq.rate 0.190452 # Inst issue rate +system.cpu.iq.FU_type_0::total 8293 # Type of FU issued +system.cpu.iq.rate 0.189347 # Inst issue rate system.cpu.iq.fu_busy_cnt 160 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019263 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31282 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12675 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7463 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31213 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8464 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1297 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 875 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10763 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2460 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall @@ -426,43 +433,43 @@ system.cpu.iew.memOrderViolationEvents 12 # Nu system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7925 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1525 # number of nop insts executed -system.cpu.iew.exec_refs 3189 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_nop 1512 # number of nop insts executed +system.cpu.iew.exec_refs 3186 # number of memory reference insts executed +system.cpu.iew.exec_branches 1344 # Number of branches executed system.cpu.iew.exec_stores 1079 # Number of stores executed -system.cpu.iew.exec_rate 0.181716 # Inst execution rate -system.cpu.iew.wb_sent 7555 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7465 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.180648 # Inst execution rate +system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7455 # cumulative count of insts written-back system.cpu.iew.wb_producers 2921 # num instructions producing a value system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.171168 # insts written-back per cycle +system.cpu.iew.wb_rate 0.170213 # insts written-back per cycle system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4943 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13600 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.427426 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.207995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13564 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.428561 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.209396 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11198 82.34% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 7.35% 89.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 630 4.63% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 315 2.32% 96.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.10% 97.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11162 82.29% 82.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 7.37% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 630 4.64% 94.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 315 2.32% 96.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 149 1.10% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13600 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13564 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,23 +482,23 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24237 # The number of ROB reads -system.cpu.rob.rob_writes 22398 # The number of ROB writes +system.cpu.rob.rob_reads 24172 # The number of ROB reads +system.cpu.rob.rob_writes 22333 # The number of ROB writes system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29137 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 29366 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.458495 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.458495 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118224 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.118224 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10746 # number of integer regfile reads -system.cpu.int_regfile_writes 5233 # number of integer regfile writes +system.cpu.cpi 8.494569 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.494569 # CPI: Total CPI of All Threads +system.cpu.ipc 0.117722 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.117722 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10743 # number of integer regfile reads +system.cpu.int_regfile_writes 5234 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1402835811 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -506,55 +513,55 @@ system.cpu.toL2Bus.data_through_bus 30720 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 227500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.632436 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits -system.cpu.icache.overall_hits::total 1531 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses -system.cpu.icache.overall_misses::total 454 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31019250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31019250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31019250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31019250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31019250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31019250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1985 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1985 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1985 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1985 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228715 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228715 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228715 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228715 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228715 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228715 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68324.339207 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68324.339207 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68324.339207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68324.339207 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 161.632436 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078922 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078922 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits +system.cpu.icache.overall_hits::total 1514 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses +system.cpu.icache.overall_misses::total 451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -563,48 +570,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 47 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23858000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23858000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23858000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23858000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23858000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23858000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170277 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.170277 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170277 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -622,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23490000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7101750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30591750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3862250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3862250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34454000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23490000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34454000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -655,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70119.402985 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78041.208791 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71811.619718 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75730.392157 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75730.392157 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72230.607966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70119.402985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77211.267606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72230.607966 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,17 +692,17 @@ system.cpu.l2cache.demand_mshr_misses::total 477 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19249000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5981750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25230750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3228750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3228750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19249000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9210500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28459500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19249000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9210500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28459500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19597750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5909750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25507500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19597750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9093000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28690750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19597750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9093000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28690750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses @@ -707,27 +714,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57459.701493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65733.516484 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59227.112676 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63308.823529 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63308.823529 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58500.746269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64942.307692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.760563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 91.712882 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.712882 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022391 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits @@ -744,14 +751,14 @@ system.cpu.dcache.demand_misses::cpu.data 510 # n system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10243000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10243000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22828749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22828749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33071749 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33071749 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33071749 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33071749 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10190250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10190250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22575249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22575249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32765499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32765499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32765499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32765499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -768,19 +775,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69209.459459 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69209.459459 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63062.842541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63062.842541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64846.566667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64846.566667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68853.040541 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68853.040541 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62362.566298 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62362.566298 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64246.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64246.076471 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.727273 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -800,14 +807,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7196250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7196250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3914249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3914249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11110499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11110499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11110499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11110499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10987499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10987499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10987499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10987499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -816,14 +823,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79079.670330 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79079.670330 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76749.980392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76749.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78255.494505 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78255.494505 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75808.803922 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75808.803922 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index bf93774ff..800440e86 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18469500 # Number of ticks simulated -final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18905500 # Number of ticks simulated +final_tick 18905500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33738 # Simulator instruction rate (inst/s) -host_op_rate 33735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107564291 # Simulator tick rate (ticks/s) -host_mem_usage 225768 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 83485 # Simulator instruction rate (inst/s) +host_op_rate 83467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272386071 # Simulator tick rate (ticks/s) +host_mem_usage 250488 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 446 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28544 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18341000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 446 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 1167914099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 341911084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1509825183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1167914099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1167914099 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1167914099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 341911084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1509825183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 446 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 70 # Per bank write bursts +system.physmem.perBankRdBursts::1 42 # Per bank write bursts +system.physmem.perBankRdBursts::2 54 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts +system.physmem.perBankRdBursts::4 53 # Per bank write bursts +system.physmem.perBankRdBursts::5 61 # Per bank write bursts +system.physmem.perBankRdBursts::6 52 # Per bank write bursts +system.physmem.perBankRdBursts::7 13 # Per bank write bursts +system.physmem.perBankRdBursts::8 8 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 2 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 4 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 18777000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 446 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation -system.physmem.totQLat 1996500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests -system.physmem.totBusLat 2230000 # Total cycles spent in databus access -system.physmem.totBankLat 6765000 # Total cycles spent in bank access -system.physmem.avgQLat 4476.46 # Average queueing delay per request -system.physmem.avgBankLat 15168.16 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24644.62 # Average memory access latency -system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.07 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.60 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 380 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.846154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.491272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 472.454851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 36 46.15% 46.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 8 10.26% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 8 10.26% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 5.13% 71.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.56% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 3.85% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.28% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.56% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 2.56% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.56% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 1.28% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.28% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 2.56% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1 1.28% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.28% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.28% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 1 1.28% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 2 2.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 3018500 # Total ticks spent queuing +system.physmem.totMemAccLat 11958500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6710000 # Total ticks spent accessing banks +system.physmem.avgQLat 6767.94 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15044.84 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26812.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1509.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1509.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.80 # Data bus utilization in percentage +system.physmem.busUtilRead 11.80 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 368 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41123.32 # Average gap between requests -system.membus.throughput 1545466851 # Throughput (bytes/s) +system.physmem.avgGap 42100.90 # Average gap between requests +system.physmem.pageHitRate 82.51 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1509825183 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -202,10 +211,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 566000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) system.cpu.branchPred.lookups 2238 # Number of BP lookups system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect @@ -234,10 +243,10 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 36940 # number of cpu cycles simulated +system.cpu.numCycles 37812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7436 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken @@ -245,27 +254,27 @@ system.cpu.fetch.Cycles 2263 # Nu system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.117612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.534017 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9513 80.78% 80.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.51% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.49% 83.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.21% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.93% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.13% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.18% 90.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 11776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059188 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.348064 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7513 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2098 # Number of cycles decode is running system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking @@ -275,7 +284,7 @@ system.cpu.decode.BranchMispred 154 # Nu system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1987 # Number of cycles rename is running @@ -298,66 +307,66 @@ system.cpu.memDep0.conflictingLoads 52 # Nu system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8904 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3486 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.756114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.487258 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8416 71.47% 71.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.70% 87.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 501 4.25% 91.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.87% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11776 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 61.52% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued @@ -384,21 +393,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1628 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8903 # Type of FU issued -system.cpu.iq.rate 0.241012 # Inst issue rate -system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8904 # Type of FU issued +system.cpu.iq.rate 0.235481 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019429 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29936 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14577 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8131 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9043 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -425,43 +434,43 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8503 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3201 # number of memory reference insts executed +system.cpu.iew.exec_refs 3202 # number of memory reference insts executed system.cpu.iew.exec_branches 1351 # Number of branches executed -system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.230157 # Inst execution rate -system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8157 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4221 # num instructions producing a value -system.cpu.iew.wb_consumers 6683 # num instructions consuming a value +system.cpu.iew.exec_stores 1524 # Number of stores executed +system.cpu.iew.exec_rate 0.224876 # Inst execution rate +system.cpu.iew.wb_sent 8273 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4220 # num instructions producing a value +system.cpu.iew.wb_consumers 6682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back +system.cpu.iew.wb_rate 0.215752 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631547 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11067 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.523358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.324283 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8688 78.50% 78.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1007 9.10% 87.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 608 5.49% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 271 2.45% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.54% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.98% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11067 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,22 +483,22 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21366 # The number of ROB reads +system.cpu.rob.rob_reads 21334 # The number of ROB reads system.cpu.rob.rob_writes 21446 # The number of ROB writes system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 26036 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13474 # number of integer regfile reads +system.cpu.cpi 6.528315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.528315 # CPI: Total CPI of All Threads +system.cpu.ipc 0.153179 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.153179 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13476 # number of integer regfile reads system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1533521991 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -504,19 +513,19 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 587000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.362417 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.362417 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082696 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082696 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits @@ -529,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 442 # n system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses system.cpu.icache.overall_misses::total 442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28917500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28917500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28917500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28917500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28917500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28917500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30183750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30183750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30183750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30183750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30183750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30183750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses @@ -547,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65424.208145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65424.208145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65424.208145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68289.027149 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68289.027149 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68289.027149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68289.027149 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68289.027149 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -573,36 +582,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23457750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23457750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23457750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23457750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23457750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23457750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24475000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24475000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66831.196581 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66831.196581 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.344729 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.344729 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.344729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.344729 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.747174 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.225208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521966 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006096 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -623,17 +632,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23046250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4132250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27178500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3637250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3637250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23046250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7769500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30815750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23046250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7769500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30815750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24063500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3590250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3590250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24063500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7664750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31728250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24063500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7664750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31728250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -656,17 +665,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66800.724638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76523.148148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68116.541353 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77388.297872 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77388.297872 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69093.609865 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69093.609865 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69749.275362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70521.303258 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76388.297872 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76388.297872 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71139.573991 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69749.275362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75888.613861 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71139.573991 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,17 +695,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18694250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3059750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3059750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18694250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6525500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25219750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18694250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6525500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23130500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6423750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26143750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6423750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26143750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -708,51 +717,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57159.420290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57971.177945 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64111.702128 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64111.702128 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57159.420290 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.485149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58618.273543 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.784946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.784946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015572 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits -system.cpu.dcache.overall_hits::total 2192 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits +system.cpu.dcache.overall_hits::total 2188 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 431 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 431 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 431 # number of overall misses -system.cpu.dcache.overall_misses::total 431 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7388000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7388000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19896996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19896996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27284996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27284996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27284996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27284996 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses +system.cpu.dcache.overall_misses::total 435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7365250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7365250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19851746 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19851746 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27216996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27216996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27216996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27216996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -763,20 +772,20 @@ system.cpu.dcache.overall_accesses::cpu.data 2623 system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164316 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164316 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164316 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164316 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71038.461538 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60847.082569 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63306.255220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70819.711538 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70819.711538 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59975.063444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59975.063444 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62567.806897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62567.806897 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62567.806897 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -787,12 +796,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -801,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3640248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3640248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7780248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7780248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7780248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7780248 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -817,14 +826,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76276.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76276.941176 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 68c96c714..b34a38ab7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20802500 # Number of ticks simulated -final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20892500 # Number of ticks simulated +final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86492 # Simulator instruction rate (inst/s) -host_op_rate 86452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337526822 # Simulator tick rate (ticks/s) -host_mem_usage 231936 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 70791 # Simulator instruction rate (inst/s) +host_op_rate 70777 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 277537926 # Simulator tick rate (ticks/s) +host_mem_usage 260788 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 889123903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 412258142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1301382045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 889123903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 889123903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 423 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 27072 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20733000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 423 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 252 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 885293766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 410482230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1295775996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 885293766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 885293766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 885293766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 410482230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1295775996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24 # Per bank write bursts +system.physmem.perBankRdBursts::1 7 # Per bank write bursts +system.physmem.perBankRdBursts::2 1 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 78 # Per bank write bursts +system.physmem.perBankRdBursts::6 80 # Per bank write bursts +system.physmem.perBankRdBursts::7 62 # Per bank write bursts +system.physmem.perBankRdBursts::8 35 # Per bank write bursts +system.physmem.perBankRdBursts::9 18 # Per bank write bursts +system.physmem.perBankRdBursts::10 10 # Per bank write bursts +system.physmem.perBankRdBursts::11 52 # Per bank write bursts +system.physmem.perBankRdBursts::12 12 # Per bank write bursts +system.physmem.perBankRdBursts::13 21 # Per bank write bursts +system.physmem.perBankRdBursts::14 7 # Per bank write bursts +system.physmem.perBankRdBursts::15 8 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 20823000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 423 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -150,48 +152,53 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation -system.physmem.totQLat 2859500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11464500 # Sum of mem lat for all requests -system.physmem.totBusLat 2115000 # Total cycles spent in databus access -system.physmem.totBankLat 6490000 # Total cycles spent in bank access -system.physmem.avgQLat 6760.05 # Average queueing delay per request -system.physmem.avgBankLat 15342.79 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27102.84 # Average memory access latency -system.physmem.avgRdBW 1301.38 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1301.38 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.55 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 358 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 80 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.400000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.623207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.187934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 31 38.75% 38.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 11 13.75% 52.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 4 5.00% 57.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 6 7.50% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 1 1.25% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 6 7.50% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 5.00% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 3 3.75% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 6 7.50% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 2.50% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.25% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.25% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 1.25% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.25% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 1 1.25% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 80 # Bytes accessed per row activation +system.physmem.totQLat 3229250 # Total ticks spent queuing +system.physmem.totMemAccLat 11834250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6490000 # Total ticks spent accessing banks +system.physmem.avgQLat 7634.16 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15342.79 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27976.95 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1295.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1295.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.12 # Data bus utilization in percentage +system.physmem.busUtilRead 10.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 343 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49014.18 # Average gap between requests -system.membus.throughput 1301382045 # Throughput (bytes/s) +system.physmem.avgGap 49226.95 # Average gap between requests +system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1295775996 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -204,8 +211,8 @@ system.membus.data_through_bus 27072 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3938750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -216,7 +223,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41606 # number of cpu cycles simulated +system.cpu.numCycles 41786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -238,12 +245,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9660 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9664 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35361 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35541 # Number of cycles cpu's stages were not processed system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 15.009854 # Percentage of cycles cpu is active +system.cpu.activity 14.945197 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -255,36 +262,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.810400 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.844190 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.810400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128034 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.844190 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127483 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.128034 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36966 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127483 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37146 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.152238 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38411 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.104198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38591 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.679181 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38573 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.646102 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38753 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.289814 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40631 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.258412 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40811 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.343412 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.333317 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38629 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.555162 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.907558 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -297,12 +304,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25692750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25692750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25692750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25692750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25692750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25692750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25613500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25613500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25613500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25613500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25613500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25613500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -315,12 +322,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70198.770492 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70198.770492 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70198.770492 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70198.770492 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69982.240437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69982.240437 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,26 +348,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20948250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20948250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20948250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20948250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20948250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20948250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20868000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20868000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20868000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20868000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20868000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20868000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71987.113402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71987.113402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1310611705 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1304965897 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -375,21 +382,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 217250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.400750 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.324573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -410,17 +417,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20629750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3759250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24389000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5820750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5820750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20629750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9580000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30209750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20629750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9580000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30209750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20549500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3769000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24318500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6227750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6227750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9996750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30546250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20549500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9996750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30546250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -443,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71383.217993 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70929.245283 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71312.865497 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71861.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71861.111111 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71417.848700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71417.848700 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +480,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17007250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20108500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4823250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4823250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17007250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7924500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24931750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17007250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7924500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24931750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16936000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3114000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20050000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5232250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5232250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16936000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8346250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25282250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16936000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8346250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25282250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -495,27 +502,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58848.615917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58514.150943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58796.783626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59546.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59546.296296 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.407936 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -532,14 +539,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4325500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4325500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26675750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26675750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31001250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31001250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31001250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31001250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4332750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4332750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29231250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29231250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33564000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33564000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33564000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33564000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -556,14 +563,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70909.836066 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70909.836066 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64590.193705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64590.193705 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65403.481013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65403.481013 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70810.126582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70810.126582 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked @@ -588,14 +595,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3825750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3825750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5904250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5904250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9730000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9730000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9730000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9730000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6311250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6311250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10146750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10146750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10146750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10146750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -604,14 +611,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70847.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70847.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72891.975309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72891.975309 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 45776fad9..b42a03bbb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19639500 # Number of ticks simulated -final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19970500 # Number of ticks simulated +final_tick 19970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27608 # Simulator instruction rate (inst/s) -host_op_rate 50013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100764572 # Simulator tick rate (ticks/s) -host_mem_usage 247304 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 37809 # Simulator instruction rate (inst/s) +host_op_rate 68492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140319695 # Simulator tick rate (ticks/s) +host_mem_usage 243588 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 26624 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19591000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 417 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory +system.physmem.bytes_read::total 26496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 414 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 874890463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451866503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1326756967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 874890463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451866503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1326756967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 415 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 33 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 5 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 50 # Per bank write bursts +system.physmem.perBankRdBursts::5 44 # Per bank write bursts +system.physmem.perBankRdBursts::6 20 # Per bank write bursts +system.physmem.perBankRdBursts::7 36 # Per bank write bursts +system.physmem.perBankRdBursts::8 23 # Per bank write bursts +system.physmem.perBankRdBursts::9 73 # Per bank write bursts +system.physmem.perBankRdBursts::10 63 # Per bank write bursts +system.physmem.perBankRdBursts::11 17 # Per bank write bursts +system.physmem.perBankRdBursts::12 2 # Per bank write bursts +system.physmem.perBankRdBursts::13 17 # Per bank write bursts +system.physmem.perBankRdBursts::14 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 17 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 19922000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 415 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,300 +152,305 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation -system.physmem.totQLat 1395750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests -system.physmem.totBusLat 2085000 # Total cycles spent in databus access -system.physmem.totBankLat 7645000 # Total cycles spent in bank access -system.physmem.avgQLat 3347.12 # Average queueing delay per request -system.physmem.avgBankLat 18333.33 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26680.46 # Average memory access latency -system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 329 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 226.174757 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.685606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.474459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 47 45.63% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 17 16.50% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 14 13.59% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 4.85% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 5 4.85% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.91% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 3.88% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.94% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 0.97% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 1.94% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.97% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.97% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 2039250 # Total ticks spent queuing +system.physmem.totMemAccLat 11731750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7617500 # Total ticks spent accessing banks +system.physmem.avgQLat 4913.86 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18355.42 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28269.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1329.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1329.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.39 # Data bus utilization in percentage +system.physmem.busUtilRead 10.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 312 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46980.82 # Average gap between requests -system.membus.throughput 1355635327 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 340 # Transaction distribution -system.membus.trans_dist::ReadResp 339 # Transaction distribution +system.physmem.avgGap 48004.82 # Average gap between requests +system.physmem.pageHitRate 75.18 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1326756967 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 338 # Transaction distribution +system.membus.trans_dist::ReadResp 337 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26624 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26496 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu.branchPred.lookups 3060 # Number of BP lookups -system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups -system.cpu.branchPred.BTBHits 719 # Number of BTB hits +system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3871500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.4 # Layer utilization (%) +system.cpu.branchPred.lookups 3084 # Number of BP lookups +system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39280 # number of cpu cycles simulated +system.cpu.numCycles 39942 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10287 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5300 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.153353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669079 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18006 82.43% 82.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 216 0.99% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 142 0.65% 84.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.03% 85.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 181 0.83% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 0.92% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 1.26% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 159 0.73% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2442 11.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3343 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 31469 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077212 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.353863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11079 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3583 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11444 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.654421 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16359 74.89% 74.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1539 7.05% 81.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1092 5.00% 86.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 724 3.31% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 698 3.20% 93.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 576 2.64% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 581 2.66% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21845 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17094 # Type of FU issued -system.cpu.iq.rate 0.435183 # Inst issue rate -system.cpu.iq.fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17027 # Type of FU issued +system.cpu.iq.rate 0.426293 # Inst issue rate +system.cpu.iq.fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3034 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3125 # number of memory reference insts executed -system.cpu.iew.exec_branches 1615 # Number of branches executed -system.cpu.iew.exec_stores 1277 # Number of stores executed -system.cpu.iew.exec_rate 0.411965 # Inst execution rate -system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15703 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10139 # num instructions producing a value -system.cpu.iew.wb_consumers 15623 # num instructions consuming a value +system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_branches 1623 # Number of branches executed +system.cpu.iew.exec_stores 1273 # Number of stores executed +system.cpu.iew.exec_rate 0.403685 # Inst execution rate +system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15646 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10128 # num instructions producing a value +system.cpu.iew.wb_consumers 15579 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back +system.cpu.iew.wb_rate 0.391718 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 19988 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.344274 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16420 82.15% 82.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1360 6.80% 88.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 589 2.95% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 713 3.57% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 364 1.82% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19988 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -456,138 +463,138 @@ system.cpu.commit.int_insts 9653 # Nu system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40219 # The number of ROB reads -system.cpu.rob.rob_writes 42582 # The number of ROB writes -system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40049 # The number of ROB reads +system.cpu.rob.rob_writes 42426 # The number of ROB writes +system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18097 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20780 # number of integer regfile reads -system.cpu.int_regfile_writes 12385 # number of integer regfile writes +system.cpu.cpi 7.424164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.424164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.134695 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.134695 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20727 # number of integer regfile reads +system.cpu.int_regfile_writes 12358 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8044 # number of cc regfile reads -system.cpu.cc_regfile_writes 4852 # number of cc regfile writes -system.cpu.misc_regfile_reads 7122 # number of misc regfile reads +system.cpu.cc_regfile_reads 8004 # number of cc regfile reads +system.cpu.cc_regfile_writes 4850 # number of cc regfile writes +system.cpu.misc_regfile_reads 7135 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution +system.cpu.toL2Bus.throughput 1333166420 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 463250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 458500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.946729 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1608 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1608 # number of overall hits -system.cpu.icache.overall_hits::total 1608 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses -system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24439500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24439500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24439500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24439500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1977 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1977 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1977 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1977 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186646 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186646 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186646 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 130.946729 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063939 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits +system.cpu.icache.overall_hits::total 1609 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses +system.cpu.icache.overall_misses::total 371 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25087750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25087750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25087750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25087750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67621.967655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67621.967655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67621.967655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67621.967655 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 70 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19054250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19054250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139100 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.139100 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.139100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.139100 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69288.181818 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69288.181818 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 97 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 97 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 97 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19639000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71675.182482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71675.182482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71675.182482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71675.182482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71675.182482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71675.182482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.561658 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.766589 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005900 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.812999 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.748659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003992 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.016356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.750233 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004992 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits @@ -597,61 +604,61 @@ system.cpu.l2cache.demand_hits::total 2 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 340 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 338 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses -system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18767750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5075750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23843500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5461000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5461000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18767750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10536750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29304500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18767750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10536750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29304500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 275 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 67 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 342 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses +system.cpu.l2cache.overall_misses::total 415 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19353500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24357500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5417000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5417000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10421000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29774500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10421000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29774500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 275 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 419 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 275 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 419 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996364 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.985075 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.994152 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 274 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996350 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.984848 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994118 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996364 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.993056 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995227 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996364 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.993056 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995227 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68495.437956 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76905.303030 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70127.941176 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70922.077922 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70922.077922 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70274.580336 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70274.580336 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70891.941392 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76984.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.609467 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70350.649351 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70350.649351 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71745.783133 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71745.783133 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -660,113 +667,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4265250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19588500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4500500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4500500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15323250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8765750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24089000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15323250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8765750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24089000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.985075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15927500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4205500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20133000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4457500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4457500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15927500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8663000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15927500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8663000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24590500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55924.270073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57613.235294 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58448.051948 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58448.051948 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58342.490842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64700 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59565.088757 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.722336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2341 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.370629 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 83.239431 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.722336 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020196 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 83.239431 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020322 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020322 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2341 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2341 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2341 # number of overall hits -system.cpu.dcache.overall_hits::total 2341 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2337 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2337 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2337 # number of overall hits +system.cpu.dcache.overall_hits::total 2337 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 210 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses -system.cpu.dcache.overall_misses::total 210 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9610000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9610000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5723000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5723000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15333000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15333000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15333000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15333000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1616 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses +system.cpu.dcache.overall_misses::total 209 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9408000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9408000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5676000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5676000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15084000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15084000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15084000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15084000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082302 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082302 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72255.639098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72255.639098 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74324.675325 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 163 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71272.727273 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71272.727273 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73714.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73714.285714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,38 +783,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 66 system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5151750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5151750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5538000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10689750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10689750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10689750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10689750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 12317fca2..15c806f18 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24404000 # Number of ticks simulated -final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24229500 # Number of ticks simulated +final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12749 # Simulator instruction rate (inst/s) -host_op_rate 12749 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24410850 # Simulator tick rate (ticks/s) -host_mem_usage 229776 # Number of bytes of host memory used -host_seconds 1.00 # Real time elapsed on the host +host_inst_rate 81251 # Simulator instruction rate (inst/s) +host_op_rate 81244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154440285 # Simulator tick rate (ticks/s) +host_mem_usage 227736 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory +system.physmem.bytes_read::total 62400 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 974 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1636453040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 917882314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2554335355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1636453040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1636453040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 974 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 974 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 62336 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 77 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 87 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24245500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 974 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory +system.physmem.num_reads::total 975 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1648238717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 927134278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2575372996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1648238717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1648238717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1648238717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 927134278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2575372996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 975 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 82 # Per bank write bursts +system.physmem.perBankRdBursts::1 153 # Per bank write bursts +system.physmem.perBankRdBursts::2 77 # Per bank write bursts +system.physmem.perBankRdBursts::3 60 # Per bank write bursts +system.physmem.perBankRdBursts::4 87 # Per bank write bursts +system.physmem.perBankRdBursts::5 49 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 49 # Per bank write bursts +system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::9 39 # Per bank write bursts +system.physmem.perBankRdBursts::10 30 # Per bank write bursts +system.physmem.perBankRdBursts::11 33 # Per bank write bursts +system.physmem.perBankRdBursts::12 15 # Per bank write bursts +system.physmem.perBankRdBursts::13 121 # Per bank write bursts +system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24081000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 975 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,101 +152,101 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.957672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.277128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 472.297416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 80 42.33% 42.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 30 15.87% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 19 10.05% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 20 10.58% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 1.59% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 2.65% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 2.12% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 3 1.59% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1 0.53% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 6 3.17% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 0.53% 91.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 0.53% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 0.53% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 1.06% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 0.53% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 1.06% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 1 0.53% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 1 0.53% 95.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 0.53% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 1 0.53% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 1.06% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 0.53% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 1 0.53% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 1 0.53% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 1 0.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 189 # Bytes accessed per row activation -system.physmem.totQLat 8948500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 30593500 # Sum of mem lat for all requests -system.physmem.totBusLat 4870000 # Total cycles spent in databus access -system.physmem.totBankLat 16775000 # Total cycles spent in bank access -system.physmem.avgQLat 9187.37 # Average queueing delay per request -system.physmem.avgBankLat 17222.79 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31410.16 # Average memory access latency -system.physmem.avgRdBW 2554.34 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2554.34 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.96 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.25 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 785 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 271.926267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.688517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.951821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 92 42.40% 42.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 33 15.21% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 21 9.68% 67.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 20 9.22% 76.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 1.38% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 8 3.69% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3 1.38% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 4 1.84% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 4 1.84% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 1.84% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 5 2.30% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 4 1.84% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 0.92% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 2 0.92% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 3 1.38% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.46% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 2 0.92% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 2 0.92% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 0.46% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 0.92% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation +system.physmem.totQLat 9442250 # Total ticks spent queuing +system.physmem.totMemAccLat 31257250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers +system.physmem.totBankLat 16940000 # Total ticks spent accessing banks +system.physmem.avgQLat 9684.36 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 17374.36 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32058.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2575.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2575.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 20.12 # Data bus utilization in percentage +system.physmem.busUtilRead 20.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 758 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 24892.71 # Average gap between requests -system.membus.throughput 2554335355 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 828 # Transaction distribution -system.membus.trans_dist::ReadResp 828 # Transaction distribution +system.physmem.avgGap 24698.46 # Average gap between requests +system.physmem.pageHitRate 77.74 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.09 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2575372996 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 829 # Transaction distribution +system.membus.trans_dist::ReadResp 829 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 62336 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 62336 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 62400 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 9049000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 37.1 # Layer utilization (%) -system.cpu.branchPred.lookups 6717 # Number of BP lookups -system.cpu.branchPred.condPredicted 3814 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4787 # Number of BTB lookups -system.cpu.branchPred.BTBHits 874 # Number of BTB hits +system.membus.reqLayer0.occupancy 1237000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 37.4 # Layer utilization (%) +system.cpu.branchPred.lookups 6676 # Number of BP lookups +system.cpu.branchPred.condPredicted 3773 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4746 # Number of BTB lookups +system.cpu.branchPred.BTBHits 873 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.257781 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 896 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 177 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 18.394437 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4630 # DTB read hits -system.cpu.dtb.read_misses 109 # DTB read misses +system.cpu.dtb.read_hits 4588 # DTB read hits +system.cpu.dtb.read_misses 111 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4739 # DTB read accesses -system.cpu.dtb.write_hits 2007 # DTB write hits -system.cpu.dtb.write_misses 95 # DTB write misses +system.cpu.dtb.read_accesses 4699 # DTB read accesses +system.cpu.dtb.write_hits 2013 # DTB write hits +system.cpu.dtb.write_misses 87 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2102 # DTB write accesses -system.cpu.dtb.data_hits 6637 # DTB hits -system.cpu.dtb.data_misses 204 # DTB misses +system.cpu.dtb.write_accesses 2100 # DTB write accesses +system.cpu.dtb.data_hits 6601 # DTB hits +system.cpu.dtb.data_misses 198 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6841 # DTB accesses -system.cpu.itb.fetch_hits 5430 # ITB hits -system.cpu.itb.fetch_misses 55 # ITB misses +system.cpu.dtb.data_accesses 6799 # DTB accesses +system.cpu.itb.fetch_hits 5373 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5485 # ITB accesses +system.cpu.itb.fetch_accesses 5430 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -259,316 +261,316 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 48809 # number of cpu cycles simulated +system.cpu.numCycles 48460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1620 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 37306 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6717 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1770 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6254 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5430 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 908 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28676 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.300949 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.721933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 37136 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5373 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 29553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.256590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.686803 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22422 78.19% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 547 1.91% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 376 1.31% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 432 1.51% 82.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 434 1.51% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 433 1.51% 85.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 459 1.60% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 528 1.84% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3045 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23330 78.94% 78.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 457 1.55% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 520 1.76% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3046 10.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28676 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137618 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.764326 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 39987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8556 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5391 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2766 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 575 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 354 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 32748 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 724 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2766 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40726 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5410 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 972 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5017 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2276 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30111 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2293 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22579 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37089 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37071 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 29553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.766323 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40475 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9887 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5338 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 491 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2736 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2736 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41176 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6161 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5023 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2246 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30191 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37141 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13439 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 57 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6273 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3023 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6118 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3003 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1402 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 3035 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26482 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21796 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12686 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8147 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28676 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.760078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.341515 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 26321 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 29553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.731770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.328577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19237 67.08% 67.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3397 11.85% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2648 9.23% 88.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1591 5.55% 93.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1050 3.66% 97.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 477 1.66% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 210 0.73% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 43 0.15% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20214 68.40% 68.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3351 11.34% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2621 8.87% 88.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1590 5.38% 93.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1011 3.42% 97.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 29553 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 4.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 102 58.29% 62.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66 37.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 107 57.84% 62.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69 37.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7221 65.66% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2635 23.96% 89.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1137 10.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7076 65.52% 65.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2585 23.94% 89.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1134 10.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10998 # Type of FU issued +system.cpu.iq.FU_type_0::total 10800 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7106 65.81% 65.83% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.84% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.84% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2582 23.91% 89.77% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7137 65.92% 65.94% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.95% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.95% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2587 23.90% 89.87% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10798 # Type of FU issued -system.cpu.iq.FU_type::total 21796 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.446557 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 175 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004083 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.003946 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008029 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 72523 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 39256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18760 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 10826 # Type of FU issued +system.cpu.iq.FU_type::total 21626 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.446265 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 88 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 97 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 185 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73079 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18683 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21945 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21785 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1840 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1787 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 481 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1820 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 537 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1852 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 408 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2766 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 26762 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 628 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6026 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2758 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 225 # Number of branches that were predicted taken incorrectly +system.cpu.iew.iewSquashCycles 2736 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20286 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2395 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2362 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1510 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20164 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2366 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4717 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1462 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 112 # number of nop insts executed -system.cpu.iew.exec_nop::1 87 # number of nop insts executed +system.cpu.iew.exec_nop::0 109 # number of nop insts executed +system.cpu.iew.exec_nop::1 90 # number of nop insts executed system.cpu.iew.exec_nop::total 199 # number of nop insts executed -system.cpu.iew.exec_refs::0 3467 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3404 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6871 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1580 # Number of branches executed -system.cpu.iew.exec_branches::1 1582 # Number of branches executed -system.cpu.iew.exec_branches::total 3162 # Number of branches executed -system.cpu.iew.exec_stores::0 1072 # Number of stores executed -system.cpu.iew.exec_stores::1 1042 # Number of stores executed +system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3414 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6831 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1584 # Number of branches executed +system.cpu.iew.exec_branches::1 1595 # Number of branches executed +system.cpu.iew.exec_branches::total 3179 # Number of branches executed +system.cpu.iew.exec_stores::0 1066 # Number of stores executed +system.cpu.iew.exec_stores::1 1048 # Number of stores executed system.cpu.iew.exec_stores::total 2114 # Number of stores executed -system.cpu.iew.exec_rate 0.415620 # Inst execution rate -system.cpu.iew.wb_sent::0 9597 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9491 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19088 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9418 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9362 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18780 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4881 # num instructions producing a value -system.cpu.iew.wb_producers::1 4800 # num instructions producing a value -system.cpu.iew.wb_producers::total 9681 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6383 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6247 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12630 # num instructions consuming a value +system.cpu.iew.exec_rate 0.416096 # Inst execution rate +system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9370 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18703 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4798 # num instructions producing a value +system.cpu.iew.wb_producers::1 4829 # num instructions producing a value +system.cpu.iew.wb_producers::total 9627 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6319 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12566 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.192956 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.191809 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.384765 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.764687 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.768369 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.766508 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.193355 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.385947 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.764203 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.766115 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 13991 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1133 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.446662 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.213615 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.196069 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22891 80.01% 80.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3017 10.55% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1097 3.83% 94.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 546 1.91% 96.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 330 1.15% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 253 0.88% 98.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 201 0.70% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 61 0.21% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 214 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23745 80.53% 80.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3040 10.31% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1123 3.81% 94.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 504 1.71% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 341 1.16% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 269 0.91% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 187 0.63% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.22% 99.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 211 0.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29486 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6390 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -599,102 +601,102 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131690 # The number of ROB reads -system.cpu.rob.rob_writes 56322 # The number of ROB writes -system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132694 # The number of ROB reads +system.cpu.rob.rob_writes 55968 # The number of ROB writes +system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18907 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6373 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 7.658716 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.659918 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.829659 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.130570 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.130550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.261120 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25473 # number of integer regfile reads -system.cpu.int_regfile_writes 14213 # number of integer regfile writes +system.cpu.cpi::0 7.603954 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.605148 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.802275 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.131511 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.131490 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25291 # number of integer regfile reads +system.cpu.int_regfile_writes 14128 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.throughput 2559580397 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution +system.cpu.toL2Bus.throughput 2580655812 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1029500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 562500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.cpu.icache.tags.replacements::0 6 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 6 # number of replacements -system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 312.493120 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4319 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.899361 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4375 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4375 # number of overall hits -system.cpu.icache.overall_hits::total 4375 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4319 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4319 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4319 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4319 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4319 # number of overall hits +system.cpu.icache.overall_hits::total 4319 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses system.cpu.icache.overall_misses::total 1049 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69677745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69677745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69677745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69677745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69677745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69677745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5424 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5424 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5424 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5424 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5424 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5424 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193400 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193400 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193400 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193400 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193400 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193400 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66423.017159 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66423.017159 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66423.017159 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66423.017159 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66423.017159 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66423.017159 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2785 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69934495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69934495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69934495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69934495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69934495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69934495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5368 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5368 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5368 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5368 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5368 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195417 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195417 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195417 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195417 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195417 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195417 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66667.774071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66667.774071 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2561 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 57 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.859649 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.155172 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -710,38 +712,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 626 system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46998246 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46998246 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46998246 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46998246 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46998246 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46998246 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115413 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115413 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115413 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75077.070288 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75077.070288 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46953746 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46953746 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46953746 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46953746 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46953746 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46953746 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116617 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116617 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116617 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75005.984026 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75005.984026 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 428.856997 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 433.166095 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 829 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002413 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 310.126222 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 118.730775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009464 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003623 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 313.001767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 120.164328 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009552 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003667 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013219 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -749,60 +751,60 @@ system.cpu.l2cache.demand_hits::total 2 # nu system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 828 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 205 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 829 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 974 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 351 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses -system.cpu.l2cache.overall_misses::total 974 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46348500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16213750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 62562250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11913750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11913750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46348500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28127500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 74476000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46348500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28127500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 74476000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 351 # number of overall misses +system.cpu.l2cache.overall_misses::total 975 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46304000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16910000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 63214000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11874500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11874500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46304000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28784500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 75088500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46304000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28784500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 75088500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 830 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 205 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 831 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 350 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 976 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 351 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 976 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 351 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997593 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74276.442308 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79479.166667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75558.272947 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81601.027397 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81601.027397 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74276.442308 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80364.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76464.065708 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74276.442308 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80364.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76464.065708 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74205.128205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82487.804878 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76253.317250 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81332.191781 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81332.191781 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82007.122507 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77013.846154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82007.122507 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77013.846154 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -812,157 +814,157 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 829 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 974 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 974 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38573000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13696250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52269250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10103750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10103750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38573000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 62373000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38573000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 62373000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38522500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14387500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52910000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10067500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10067500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38522500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24455000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 62977500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38522500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24455000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 62977500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61815.705128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67138.480392 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63127.113527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69203.767123 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69203.767123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61815.705128 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61815.705128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64037.987680 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61734.775641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70182.926829 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63823.884198 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68955.479452 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68955.479452 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 211.884963 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.837143 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 214.018929 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4470 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.735043 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 211.884963 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.051730 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.051730 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3469 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3469 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1024 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1024 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4493 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4493 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4493 # number of overall hits -system.cpu.dcache.overall_hits::total 4493 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 706 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1030 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1030 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1030 # number of overall misses -system.cpu.dcache.overall_misses::total 1030 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22955250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22955250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 48876949 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 48876949 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 71832199 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 71832199 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 71832199 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 71832199 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3793 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3793 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 214.018929 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052251 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052251 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3448 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3448 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4470 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4470 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4470 # number of overall hits +system.cpu.dcache.overall_hits::total 4470 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 329 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 329 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1037 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1037 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1037 # number of overall misses +system.cpu.dcache.overall_misses::total 1037 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23849750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23849750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 50904202 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 50904202 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74753952 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74753952 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74753952 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74753952 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3777 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3777 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5523 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5523 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085421 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085421 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.408092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.186493 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.186493 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.186493 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.186493 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70849.537037 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70849.537037 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69230.805949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69230.805949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69739.999029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69739.999029 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4722 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087106 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087106 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188306 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188306 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188306 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188306 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72491.641337 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72491.641337 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71898.590395 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71898.590395 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72086.742527 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72086.742527 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4541 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 118 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.358974 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.483051 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 560 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 686 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 686 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 686 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 686 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16427250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16427250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12061996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12061996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28489246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28489246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28489246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28489246 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053783 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053783 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12022996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12022996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29145996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29145996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29145996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29145996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054276 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054276 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063371 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063371 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80525.735294 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80525.735294 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82616.410959 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82616.410959 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063737 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063737 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83526.829268 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83526.829268 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82349.287671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82349.287671 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 0c812fe4f..9f174a09c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27282000 # Number of ticks simulated -final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27705000 # Number of ticks simulated +final_tick 27705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96636 # Simulator instruction rate (inst/s) -host_op_rate 96628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173854426 # Simulator tick rate (ticks/s) -host_mem_usage 231852 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 72386 # Simulator instruction rate (inst/s) +host_op_rate 72381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132251643 # Simulator tick rate (ticks/s) +host_mem_usage 260736 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,75 +19,77 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 436 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 436 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 27904 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 58 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 33 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27248500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 436 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 116 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 688395596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 318787223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1007182819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 688395596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 688395596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 688395596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 318787223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1007182819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 436 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 97 # Per bank write bursts +system.physmem.perBankRdBursts::1 28 # Per bank write bursts +system.physmem.perBankRdBursts::2 38 # Per bank write bursts +system.physmem.perBankRdBursts::3 20 # Per bank write bursts +system.physmem.perBankRdBursts::4 16 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 29 # Per bank write bursts +system.physmem.perBankRdBursts::7 32 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 31 # Per bank write bursts +system.physmem.perBankRdBursts::14 58 # Per bank write bursts +system.physmem.perBankRdBursts::15 33 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 27671500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 436 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 117 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -150,48 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.816327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.016062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 498.456939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 18 36.73% 36.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 9 18.37% 55.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 3 6.12% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 10.20% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 6.12% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 1 2.04% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 1 2.04% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 4.08% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 2.04% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 2.04% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 2.04% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 1 2.04% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation -system.physmem.totQLat 1525500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests -system.physmem.totBusLat 2180000 # Total cycles spent in databus access -system.physmem.totBankLat 6325000 # Total cycles spent in bank access -system.physmem.avgQLat 3498.85 # Average queueing delay per request -system.physmem.avgBankLat 14506.88 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23005.73 # Average memory access latency -system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.37 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 387 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.743118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 502.320204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 21 32.81% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 10 15.62% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5 7.81% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 8 12.50% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 3.12% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 3.12% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2 3.12% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.56% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 1.56% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.56% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.56% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.56% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 3.12% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 2 3.12% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.56% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 1.56% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 3.12% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 1 1.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation +system.physmem.totQLat 2393750 # Total ticks spent queuing +system.physmem.totMemAccLat 10830000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6256250 # Total ticks spent accessing banks +system.physmem.avgQLat 5490.25 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14349.20 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24839.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1007.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1007.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.87 # Data bus utilization in percentage +system.physmem.busUtilRead 7.87 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.39 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 372 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 62496.56 # Average gap between requests -system.membus.throughput 1020453046 # Throughput (bytes/s) +system.physmem.avgGap 63466.74 # Average gap between requests +system.physmem.pageHitRate 85.32 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.29 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1004872767 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -204,8 +213,8 @@ system.membus.data_through_bus 27840 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4048750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.6 # Layer utilization (%) system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect @@ -216,7 +225,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54565 # number of cpu cycles simulated +system.cpu.numCycles 55411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -238,12 +247,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21832 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 436 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37843 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 32.196463 # Percentage of cycles cpu is active +system.cpu.activity 31.704896 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -255,36 +264,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.654597 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads -system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.654597 # CPI: Total CPI of All Threads +system.cpu.ipc 0.273628 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.273628 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41985 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.229846 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46058 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 16.879320 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46608 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 15.886737 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 52533 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.193915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46102 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 16.799913 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.234439 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.234439 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082634 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -297,12 +306,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26803000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26803000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26803000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26803000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26803000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26803000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -315,12 +324,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70349.081365 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70349.081365 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70349.081365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70349.081365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70349.081365 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,26 +350,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20772000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20772000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20772000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20772000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20772000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20772000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69009.966777 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69009.966777 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69009.966777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69009.966777 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1009492871 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -375,21 +384,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 501000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 200.306060 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.564740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.741320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005144 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006113 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -407,17 +416,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20448500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3701250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24149750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5902500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5902500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20448500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9603750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30052250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20448500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9603750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30052250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -440,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68389.632107 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69834.905660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68607.244318 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69441.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69441.176471 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68769.450801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68389.632107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69592.391304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68769.450801 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,17 +479,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16729000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3042250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19771250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4860000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16729000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7902250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24631250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16729000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7902250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24631250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -492,27 +501,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55949.832776 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57400.943396 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56168.323864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57176.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57176.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55949.832776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57262.681159 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56364.416476 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.671839 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.671839 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024090 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024090 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -531,14 +540,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4274250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4274250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25400750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25400750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29675000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29675000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29675000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29675000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -557,14 +566,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73693.965517 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73693.965517 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60191.350711 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60191.350711 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61822.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61822.916667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61822.916667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -589,14 +598,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3755750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3755750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5990500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5990500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9746250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9746250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9746250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9746250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -605,14 +614,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70863.207547 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70863.207547 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70476.470588 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70476.470588 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70625 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 6e72806cb..dcf709c59 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26524500 # Number of ticks simulated -final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26616500 # Number of ticks simulated +final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19767 # Simulator instruction rate (inst/s) -host_op_rate 19766 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36317578 # Simulator tick rate (ticks/s) -host_mem_usage 236084 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host +host_inst_rate 75478 # Simulator instruction rate (inst/s) +host_op_rate 75473 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139143595 # Simulator tick rate (ticks/s) +host_mem_usage 260732 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,76 +19,78 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 30848 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26363500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 482 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes +system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 482 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 102 # Per bank write bursts +system.physmem.perBankRdBursts::1 29 # Per bank write bursts +system.physmem.perBankRdBursts::2 50 # Per bank write bursts +system.physmem.perBankRdBursts::3 24 # Per bank write bursts +system.physmem.perBankRdBursts::4 19 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 35 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 1 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 57 # Per bank write bursts +system.physmem.perBankRdBursts::13 31 # Per bank write bursts +system.physmem.perBankRdBursts::14 61 # Per bank write bursts +system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 26455500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 482 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -150,47 +152,55 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation -system.physmem.totQLat 1755500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests -system.physmem.totBusLat 2410000 # Total cycles spent in databus access -system.physmem.totBankLat 6765000 # Total cycles spent in bank access -system.physmem.avgQLat 3642.12 # Average queueing delay per request -system.physmem.avgBankLat 14035.27 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22677.39 # Average memory access latency -system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 430 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation +system.physmem.totQLat 2423000 # Total ticks spent queuing +system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6778750 # Total ticks spent accessing banks +system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 9.05 # Data bus utilization in percentage +system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 413 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54696.06 # Average gap between requests -system.membus.throughput 1163000245 # Throughput (bytes/s) +system.physmem.avgGap 54886.93 # Average gap between requests +system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1158980332 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution @@ -201,63 +211,63 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.0 # Layer utilization (%) -system.cpu.branchPred.lookups 6716 # Number of BP lookups -system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted +system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 16.9 # Layer utilization (%) +system.cpu.branchPred.lookups 6713 # Number of BP lookups +system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 53050 # number of cpu cycles simulated +system.cpu.numCycles 53234 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8344 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8343 # Number of cycles decode is running system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 7952 # Number of cycles rename is running system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename @@ -282,15 +292,15 @@ system.cpu.iq.iqSquashedInstsIssued 97 # Nu system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle @@ -298,7 +308,7 @@ system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -368,10 +378,10 @@ system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 21122 # Type of FU issued -system.cpu.iq.rate 0.398153 # Inst issue rate +system.cpu.iq.rate 0.396776 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads @@ -412,35 +422,35 @@ system.cpu.iew.exec_nop 1134 # nu system.cpu.iew.exec_refs 5224 # number of memory reference insts executed system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.378398 # Inst execution rate +system.cpu.iew.exec_rate 0.377090 # Inst execution rate system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19522 # cumulative count of insts written-back system.cpu.iew.wb_producers 9120 # num instructions producing a value system.cpu.iew.wb_consumers 11235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle +system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -453,22 +463,22 @@ system.cpu.commit.int_insts 12174 # Nu system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54596 # The number of ROB reads +system.cpu.rob.rob_reads 54530 # The number of ROB reads system.cpu.rob.rob_writes 50298 # The number of ROB writes -system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads -system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads +system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads +system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 32043 # number of integer regfile reads system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -483,55 +493,55 @@ system.cpu.toL2Bus.data_through_bus 30976 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits -system.cpu.icache.overall_hits::total 4873 # number of overall hits +system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits +system.cpu.icache.overall_hits::total 4872 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses system.cpu.icache.overall_misses::total 507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -552,36 +562,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 337 system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -599,17 +609,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 482 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4600000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26577500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10317750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32295250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) @@ -632,17 +642,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -662,17 +672,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses @@ -684,27 +694,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -723,14 +733,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -749,14 +759,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked @@ -781,14 +791,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -797,14 +807,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 1df87c21b..b78a3e4ce 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 110804500 # Number of ticks simulated -final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 111025500 # Number of ticks simulated +final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91896 # Simulator instruction rate (inst/s) -host_op_rate 91896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9765210 # Simulator tick rate (ticks/s) -host_mem_usage 250112 # Number of bytes of host memory used -host_seconds 11.35 # Real time elapsed on the host -sim_insts 1042724 # Number of instructions simulated -sim_ops 1042724 # Number of ops (including micro ops) simulated +host_inst_rate 119782 # Simulator instruction rate (inst/s) +host_op_rate 119782 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12747983 # Simulator tick rate (ticks/s) +host_mem_usage 275656 # Number of bytes of host memory used +host_seconds 8.71 # Real time elapsed on the host +sim_insts 1043212 # Number of instructions simulated +sim_ops 1043212 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -34,92 +34,94 @@ system.physmem.num_reads::cpu2.data 20 # Nu system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 42176 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 110776500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 660 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see +system.physmem.bw_read::cpu0.inst 205214117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96842617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 5764442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7493774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42080423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11528883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3458665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7493774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 379876695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205214117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 5764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42080423 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3458665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 256517647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205214117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96842617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5764442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7493774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42080423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11528883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3458665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7493774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 379876695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 660 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 115 # Per bank write bursts +system.physmem.perBankRdBursts::1 39 # Per bank write bursts +system.physmem.perBankRdBursts::2 29 # Per bank write bursts +system.physmem.perBankRdBursts::3 60 # Per bank write bursts +system.physmem.perBankRdBursts::4 65 # Per bank write bursts +system.physmem.perBankRdBursts::5 27 # Per bank write bursts +system.physmem.perBankRdBursts::6 18 # Per bank write bursts +system.physmem.perBankRdBursts::7 24 # Per bank write bursts +system.physmem.perBankRdBursts::8 7 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 12 # Per bank write bursts +system.physmem.perBankRdBursts::12 60 # Per bank write bursts +system.physmem.perBankRdBursts::13 38 # Per bank write bursts +system.physmem.perBankRdBursts::14 17 # Per bank write bursts +system.physmem.perBankRdBursts::15 98 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 110997500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 660 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 191 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -180,100 +182,104 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation -system.physmem.totQLat 3818750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests -system.physmem.totBusLat 3300000 # Total cycles spent in databus access -system.physmem.totBankLat 11000000 # Total cycles spent in bank access -system.physmem.avgQLat 5785.98 # Average queueing delay per request -system.physmem.avgBankLat 16666.67 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27452.65 # Average memory access latency -system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 260.662252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.685653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.368727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 56 37.09% 37.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 15 9.93% 47.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 26 17.22% 64.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 5.96% 70.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 10 6.62% 76.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 7 4.64% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 2.65% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 6 3.97% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 3 1.99% 90.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 3 1.99% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.32% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 1.32% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 3 1.99% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.32% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation +system.physmem.totQLat 4010250 # Total ticks spent queuing +system.physmem.totMemAccLat 18159000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers +system.physmem.totBankLat 10848750 # Total ticks spent accessing banks +system.physmem.avgQLat 6076.14 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27513.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.97 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 532 # Number of row buffer hits during reads +system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 509 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 167843.18 # Average gap between requests -system.membus.throughput 380634361 # Throughput (bytes/s) +system.physmem.avgGap 168178.03 # Average gap between requests +system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.34 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 379876695 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution -system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeReq 289 # Transaction distribution system.membus.trans_dist::UpgradeResp 76 # Transaction distribution -system.membus.trans_dist::ReadExReq 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 164 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1717 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1717 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 931500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6289925 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use -system.l2c.tags.total_refs 1443 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 417.165472 # Cycle average of tags in use +system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 285.088059 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.417692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.409300 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3.063366 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.732215 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000115 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000846 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000047 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006365 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits @@ -284,18 +290,18 @@ system.l2c.demand_hits::cpu1.inst 412 # nu system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1443 # number of demand (read+write) hits +system.l2c.demand_hits::total 1442 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 229 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 412 # number of overall hits system.l2c.overall_hits::cpu1.data 11 # number of overall hits system.l2c.overall_hits::cpu2.inst 349 # number of overall hits system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 421 # number of overall hits +system.l2c.overall_hits::cpu3.inst 420 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1443 # number of overall hits +system.l2c.overall_hits::total 1442 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses @@ -305,10 +311,10 @@ system.l2c.ReadReq_misses::cpu2.data 7 # nu system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 543 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses @@ -333,53 +339,53 @@ system.l2c.overall_misses::cpu2.data 20 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 674 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 24801500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 1162500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 5361500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 584250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 38166000 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6725000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 958250 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9622500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 24801500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 12337000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1162500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 5361500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 584250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1032750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 47788500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 24801500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 12337000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 1162500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 5361500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 584250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1032750 # number of overall miss cycles +system.l2c.overall_miss_latency::total 47788500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) @@ -392,28 +398,28 @@ system.l2c.demand_accesses::cpu1.inst 428 # nu system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 429 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 429 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.020930 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.020979 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.273552 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses @@ -429,50 +435,50 @@ system.l2c.demand_miss_rate::cpu1.inst 0.037383 # mi system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.020930 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.020979 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.318526 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.020930 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.020979 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67862.116992 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 76662.162162 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75343.750000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69259.868421 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 74821.428571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 63361.111111 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 69569.521179 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77920.212766 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68645.833333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82096.076923 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 73520.833333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 77082.053435 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71029.672107 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71029.672107 # average overall miss latency +system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69084.958217 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 70287.292818 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79854.166667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73454.198473 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70902.818991 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70902.818991 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,10 +511,10 @@ system.l2c.ReadReq_mshr_misses::cpu2.data 7 # n system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 18 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses @@ -533,53 +539,53 @@ system.l2c.overall_mshr_misses::cpu2.data 20 # n system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19789750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4760500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 695750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4180000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 327500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 30342250 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177515 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20238250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4701500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 676500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4287250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 30807000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 210021 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 217519 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 170017 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 180018 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6148500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 672250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 907249 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 731250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8459249 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5552000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7989500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 20238250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 10253500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 676500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 4287250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 369750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 870250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 38796500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 20238250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 10253500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 676500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 4287250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 369750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 870250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 38796500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266499 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses @@ -595,410 +601,411 @@ system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.311909 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013986 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.311909 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67650 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 58236.294896 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10875.950000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59063.829787 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67312.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60988.549618 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution +system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2541 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 292 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 292 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 591 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 348 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5418 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27456 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 135488 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) +system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 135424 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 52160 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1628974 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2704748 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1475514 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1928994 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1199245 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1926995 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1183748 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1932245 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1115744 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 82992 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits +system.cpu0.branchPred.lookups 83087 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80860 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1219 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 80377 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78332 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.455740 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 221610 # number of cpu cycles simulated +system.cpu0.numCycles 222052 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17258 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161829 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3807 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13993 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 489 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 197037 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503043 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216869 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35208 17.87% 17.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 452 0.23% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76210 38.68% 98.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 578 0.29% 98.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364 0.18% 98.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 733333 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued +system.cpu0.fetch.rateDist::total 197037 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17850 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18506 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 561 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 487444 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 187 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 333388 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 972038 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 734246 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 320411 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 872 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 895 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3641 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155927 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78789 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 76026 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 405049 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle +system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 197037 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055700 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097210 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34075 17.29% 17.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77366 39.26% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1557 0.79% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 197037 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 27.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 42 19.91% 46.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 53.08% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 171308 42.29% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155510 38.39% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued -system.cpu0.iq.rate 1.824931 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 405049 # Type of FU issued +system.cpu0.iq.rate 1.824118 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1007474 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 403236 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 405260 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2132 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2440 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 371 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 485139 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewDispLoadInsts 155927 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78789 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed +system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 328 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1114 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76515 # number of nop insts executed -system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed -system.cpu0.iew.exec_branches 80132 # Number of branches executed -system.cpu0.iew.exec_stores 78029 # Number of stores executed -system.cpu0.iew.exec_rate 1.820098 # Inst execution rate -system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238549 # num instructions producing a value -system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value +system.cpu0.iew.exec_nop 76577 # number of nop insts executed +system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80250 # Number of branches executed +system.cpu0.iew.exec_stores 78134 # Number of stores executed +system.cpu0.iew.exec_rate 1.819295 # Inst execution rate +system.cpu0.iew.wb_sent 403577 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 403236 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238895 # num instructions producing a value +system.cpu0.iew.wb_consumers 241362 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.815953 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 194597 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430500 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136019 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34534 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75417 38.76% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 472284 # Number of instructions committed -system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194597 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472968 # Number of instructions committed +system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 230857 # Number of memory references committed -system.cpu0.commit.loads 153567 # Number of loads committed +system.cpu0.commit.refs 231199 # Number of memory references committed +system.cpu0.commit.loads 153795 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79177 # Number of branches committed +system.cpu0.commit.branches 79291 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 318286 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318742 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 677374 # The number of ROB reads -system.cpu0.rob.rob_writes 971507 # The number of ROB writes -system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 396291 # Number of Instructions Simulated -system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated -system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 721592 # number of integer regfile reads -system.cpu0.int_regfile_writes 325227 # number of integer regfile writes +system.cpu0.rob.rob_reads 678234 # The number of ROB reads +system.cpu0.rob.rob_writes 972657 # The number of ROB writes +system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25015 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396861 # Number of Instructions Simulated +system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated +system.cpu0.cpi 0.559521 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559521 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 722661 # number of integer regfile reads +system.cpu0.int_regfile_writes 325773 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads +system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.313735 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits -system.cpu0.icache.overall_hits::total 5079 # number of overall hits +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.313735 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471316 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471316 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5113 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5113 # number of overall hits +system.cpu0.icache.overall_hits::total 5113 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35940245 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35940245 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35940245 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35940245 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35940245 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35940245 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5869 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5869 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5869 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.128812 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.128812 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47540.006614 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47540.006614 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1019,94 +1026,94 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27250252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27250252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686252 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686252 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27686252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686252 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27686252 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.026994 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026994 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 76817 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155698 # number of overall hits -system.cpu0.dcache.overall_hits::total 155698 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 410 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 410 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 155902 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155902 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155902 # number of overall hits +system.cpu0.dcache.overall_hits::total 155902 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 420 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 420 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 955 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 955 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 955 # number of overall misses -system.cpu0.dcache.overall_misses::total 955 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13319205 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13319205 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35150505 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35150505 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 418750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 418750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48469710 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48469710 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48469710 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48469710 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79405 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 79405 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77248 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77248 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 965 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 965 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 965 # number of overall misses +system.cpu0.dcache.overall_misses::total 965 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13542707 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13542707 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32279504 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32279504 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 45822211 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 45822211 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 45822211 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 45822211 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 79505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77362 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156653 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 156867 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156867 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 156867 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 156867 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005283 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005283 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007045 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007045 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006152 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006152 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006152 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006152 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32244.540476 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32244.540476 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59228.447706 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 59228.447706 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47484.156477 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47484.156477 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47484.156477 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -1117,365 +1124,365 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 227 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 600 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 600 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 600 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 600 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 365 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6251507 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6251507 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7188729 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7188729 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13440236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13440236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13440236 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13440236 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002428 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002428 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002223 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002223 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002327 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002327 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002327 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32391.227979 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32391.227979 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41794.936047 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41794.936047 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36822.564384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36822.564384 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 43495 # Number of BP lookups -system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits +system.cpu1.branchPred.lookups 47485 # Number of BP lookups +system.cpu1.branchPred.condPredicted 44754 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1270 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 41396 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 40599 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.074693 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 177681 # number of cpu cycles simulated +system.cpu1.numCycles 177933 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 31734 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 260080 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 47485 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 41253 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 95164 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3727 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 37889 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 23379 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 175722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.480065 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.059330 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 80558 45.84% 45.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 49339 28.08% 73.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7969 4.54% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3191 1.82% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 687 0.39% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 28723 16.35% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1207 0.69% 97.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 759 0.43% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3289 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 330316 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 175722 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.266870 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.461674 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 38713 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 32553 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 87468 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6833 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2380 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 256418 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2380 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 39395 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 20083 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11723 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 80903 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 13463 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 254199 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 175957 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 477753 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 373133 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 162997 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12960 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1085 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 16072 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 69810 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 31966 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 34021 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 211924 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10911 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.206019 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.291588 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 32801 18.67% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3291 1.87% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175722 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 104746 49.43% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 75900 35.81% 85.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued -system.cpu1.iq.rate 1.067177 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 211924 # Type of FU issued +system.cpu1.iq.rate 1.191033 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 599908 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 210080 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 212190 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2449 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2380 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 699 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 251202 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 69810 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 31966 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1044 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 30958 # number of nop insts executed -system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed -system.cpu1.iew.exec_branches 40129 # Number of branches executed -system.cpu1.iew.exec_stores 26101 # Number of stores executed -system.cpu1.iew.exec_rate 1.060603 # Inst execution rate -system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 102456 # num instructions producing a value -system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value +system.cpu1.iew.exec_nop 34927 # number of nop insts executed +system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed +system.cpu1.iew.exec_branches 44131 # Number of branches executed +system.cpu1.iew.exec_stores 31196 # Number of stores executed +system.cpu1.iew.exec_rate 1.184317 # Inst execution rate +system.cpu1.iew.wb_sent 210404 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 210080 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 116723 # num instructions producing a value +system.cpu1.iew.wb_consumers 121388 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.180669 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.961570 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1270 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 165567 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.441743 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.939965 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77636 46.89% 46.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42274 25.53% 72.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6096 3.68% 76.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8474 5.12% 81.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1557 0.94% 82.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 27207 16.43% 98.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1010 0.61% 99.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 803 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 212432 # Number of instructions committed -system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165567 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 238705 # Number of instructions committed +system.cpu1.commit.committedOps 238705 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 83673 # Number of memory references committed -system.cpu1.commit.loads 58239 # Number of loads committed -system.cpu1.commit.membars 7917 # Number of memory barriers committed -system.cpu1.commit.branches 39308 # Number of branches committed +system.cpu1.commit.refs 97880 # Number of memory references committed +system.cpu1.commit.loads 67361 # Number of loads committed +system.cpu1.commit.membars 6845 # Number of memory barriers committed +system.cpu1.commit.branches 43327 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 145097 # Number of committed integer instructions. +system.cpu1.commit.int_insts 163326 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 803 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 388816 # The number of ROB reads -system.cpu1.rob.rob_writes 452512 # The number of ROB writes -system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 174425 # Number of Instructions Simulated -system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated -system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 315718 # number of integer regfile reads -system.cpu1.int_regfile_writes 148477 # number of integer regfile writes +system.cpu1.rob.rob_reads 415361 # The number of ROB reads +system.cpu1.rob.rob_writes 504754 # The number of ROB writes +system.cpu1.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2211 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 44117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 197745 # Number of Instructions Simulated +system.cpu1.committedOps 197745 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 197745 # Number of Instructions Simulated +system.cpu1.cpi 0.899810 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.899810 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 358439 # number of integer regfile reads +system.cpu1.int_regfile_writes 167816 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads +system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 76.730522 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits -system.cpu1.icache.overall_hits::total 25178 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses -system.cpu1.icache.overall_misses::total 478 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730522 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22903 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22903 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22903 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22903 # number of overall hits +system.cpu1.icache.overall_hits::total 22903 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses +system.cpu1.icache.overall_misses::total 476 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7185993 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7185993 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7185993 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7185993 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7185993 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7185993 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23379 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23379 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23379 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.020360 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.020360 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15096.623950 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15096.623950 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1484,106 +1491,106 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5726006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726006 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5726006 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 36646 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1263.655172 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits -system.cpu1.dcache.overall_hits::total 62948 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses -system.cpu1.dcache.overall_misses::total 451 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.664777 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046220 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.046220 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 41736 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41736 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 30310 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 30310 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 72046 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 72046 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 72046 # number of overall hits +system.cpu1.dcache.overall_hits::total 72046 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 491 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 491 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 491 # number of overall misses +system.cpu1.dcache.overall_misses::total 491 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4404095 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4404095 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2802760 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2802760 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 563508 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 563508 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7206855 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7206855 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7206855 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7206855 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 42088 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 42088 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 30449 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 30449 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 72537 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 72537 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 72537 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 72537 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008363 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008363 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004565 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004565 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.814286 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006769 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006769 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006769 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006769 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12511.633523 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12511.633523 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20163.741007 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20163.741007 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9886.105263 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9886.105263 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14677.912424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14677.912424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14677.912424 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1592,365 +1599,364 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 187 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 187 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1130523 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1130523 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1329240 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1329240 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 449492 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 449492 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2459763 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2459763 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2459763 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2459763 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003920 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003920 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003514 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003514 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.814286 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003750 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003750 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003750 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6851.654545 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6851.654545 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12422.803738 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7885.824561 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7885.824561 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51236 # Number of BP lookups -system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits +system.cpu2.branchPred.lookups 51290 # Number of BP lookups +system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 45092 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 98.465360 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 177316 # number of cpu cycles simulated +system.cpu2.numCycles 177568 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 28807 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 286591 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51290 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 100996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 31176 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 19752 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.666178 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.140016 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 71009 41.28% 41.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51379 29.87% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3272 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 418050 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288847 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.613979 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 27885 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 95101 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283083 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12251 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90316 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280840 # Number of instructions processed by rename +system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 538434 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 418653 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1241 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12535 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79329 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37643 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37867 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234909 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10823 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.365710 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313889 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38461 22.36% 97.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3256 1.89% 99.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172005 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 6.01% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 56 19.79% 25.80% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 74.20% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114350 48.68% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83601 35.59% 84.27% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued -system.cpu2.iq.rate 1.322842 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234909 # Type of FU issued +system.cpu2.iq.rate 1.322924 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 642198 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 233108 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 235192 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2477 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2417 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 878 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 278010 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 351 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79329 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37643 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1071 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 457 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 973 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1144 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 38706 # number of nop insts executed -system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed -system.cpu2.iew.exec_branches 47927 # Number of branches executed -system.cpu2.iew.exec_stores 36792 # Number of stores executed -system.cpu2.iew.exec_rate 1.316311 # Inst execution rate -system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 131730 # num instructions producing a value -system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value +system.cpu2.iew.exec_nop 38771 # number of nop insts executed +system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed +system.cpu2.iew.exec_branches 48001 # Number of branches executed +system.cpu2.iew.exec_stores 36873 # Number of stores executed +system.cpu2.iew.exec_rate 1.316482 # Inst execution rate +system.cpu2.iew.wb_sent 233421 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 233108 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131942 # num instructions producing a value +system.cpu2.iew.wb_consumers 136650 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.312782 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965547 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1303 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 161811 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.639889 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.021157 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 66196 40.91% 40.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46128 28.51% 69.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6098 3.77% 73.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6657 4.11% 77.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1558 0.96% 78.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32865 20.31% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 486 0.30% 98.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1000 0.62% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 264916 # Number of instructions committed -system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 161811 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 265352 # Number of instructions committed +system.cpu2.commit.committedOps 265352 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 112806 # Number of memory references committed -system.cpu2.commit.loads 76707 # Number of loads committed -system.cpu2.commit.membars 5024 # Number of memory barriers committed -system.cpu2.commit.branches 47088 # Number of branches committed +system.cpu2.commit.refs 113027 # Number of memory references committed +system.cpu2.commit.loads 76852 # Number of loads committed +system.cpu2.commit.membars 5022 # Number of memory barriers committed +system.cpu2.commit.branches 47160 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 182014 # Number of committed integer instructions. +system.cpu2.commit.int_insts 182307 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 823 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 437936 # The number of ROB reads -system.cpu2.rob.rob_writes 557643 # The number of ROB writes -system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 222015 # Number of Instructions Simulated -system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated -system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 403571 # number of integer regfile reads -system.cpu2.int_regfile_writes 188531 # number of integer regfile writes +system.cpu2.rob.rob_reads 438409 # The number of ROB reads +system.cpu2.rob.rob_writes 558438 # The number of ROB writes +system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5563 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44482 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 222382 # Number of Instructions Simulated +system.cpu2.committedOps 222382 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 222382 # Number of Instructions Simulated +system.cpu2.cpi 0.798482 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.798482 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 404230 # number of integer regfile reads +system.cpu2.int_regfile_writes 188808 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 82.236622 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19259 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.315294 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits -system.cpu2.icache.overall_hits::total 19274 # number of overall hits +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236622 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 19259 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19259 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19259 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19259 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19259 # number of overall hits +system.cpu2.icache.overall_hits::total 19259 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses system.cpu2.icache.overall_misses::total 493 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11521742 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19767 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19767 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19767 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19767 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11620241 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11620241 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11620241 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11620241 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11620241 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11620241 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19752 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19752 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19752 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19752 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19752 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19752 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024959 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024959 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024959 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024959 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024959 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024959 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23570.468560 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23570.468560 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1971,94 +1977,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9201754 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 9201754 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9201754 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 9201754 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9201754 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 9201754 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021500 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021500 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021500 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9299505 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 9299505 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9299505 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 9299505 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9299505 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 9299505 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021517 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021517 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021517 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21881.188235 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 26.142582 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 35887 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 81436 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 81436 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 81436 # number of overall hits -system.cpu2.dcache.overall_hits::total 81436 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 344 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 344 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 143 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 143 # number of WriteReq misses +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142582 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 45613 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 35966 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 35966 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 81579 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 81579 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 81579 # number of overall hits +system.cpu2.dcache.overall_hits::total 81579 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 346 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 346 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 487 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 487 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 487 # number of overall misses -system.cpu2.dcache.overall_misses::total 487 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5599802 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5599802 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3105260 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3105260 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 575007 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 575007 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8705062 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8705062 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8705062 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8705062 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 45893 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 45893 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 36030 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 36030 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 81923 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 81923 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 81923 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 81923 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007496 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.007496 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003969 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003969 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005945 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005945 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005945 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005945 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 21715.104895 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10087.842105 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 10087.842105 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17874.870637 # average overall miss latency +system.cpu2.dcache.demand_misses::cpu2.data 485 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses +system.cpu2.dcache.overall_misses::total 485 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5531640 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5531640 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8662651 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8662651 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8662651 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8662651 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 36105 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 70 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 82064 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 82064 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 82064 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 82064 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007528 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.007528 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003850 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.814286 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.814286 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15987.398844 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 15987.398844 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17861.136082 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17861.136082 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2067,365 +2073,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 184 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 217 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 217 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1488769 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1488769 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1526989 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1526989 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 440994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 440994 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3015758 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3015758 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3015758 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3015758 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003525 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003525 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002936 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002936 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.814286 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.814286 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003266 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003266 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003266 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9189.932099 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9189.932099 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14405.556604 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14405.556604 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7736.736842 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7736.736842 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11252.828358 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11252.828358 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 56317 # Number of BP lookups -system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits +system.cpu3.branchPred.lookups 52302 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49590 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1266 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 46219 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 45467 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.372963 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 176970 # number of cpu cycles simulated +system.cpu3.numCycles 177222 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 28850 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 32602 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 20565 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 250 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 175820 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.658463 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.129406 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 72377 41.17% 41.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 52818 30.04% 71.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6573 3.74% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3193 1.82% 76.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 659 0.37% 77.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 35007 19.91% 97.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1204 0.68% 97.73% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 759 0.43% 98.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3230 1.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 468076 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 34476 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28632 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 35171 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11805 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 199357 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 546724 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 424837 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 186591 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12766 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1226 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 13474 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 80900 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 38213 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 38893 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 239002 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10694 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.359356 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.308484 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 39034 22.20% 97.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3259 1.85% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175820 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 6.20% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 47 17.15% 23.36% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 76.64% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 115815 48.46% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 85680 35.85% 84.31% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued -system.cpu3.iq.rate 1.478471 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 239002 # Type of FU issued +system.cpu3.iq.rate 1.348602 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 654188 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 237209 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 239276 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2413 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1461 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2346 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 674 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 283043 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 80900 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 38213 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 43769 # number of nop insts executed -system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed -system.cpu3.iew.exec_branches 53091 # Number of branches executed -system.cpu3.iew.exec_stores 42613 # Number of stores executed -system.cpu3.iew.exec_rate 1.471764 # Inst execution rate -system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 148532 # num instructions producing a value -system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value +system.cpu3.iew.exec_nop 39788 # number of nop insts executed +system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed +system.cpu3.iew.exec_branches 49028 # Number of branches executed +system.cpu3.iew.exec_stores 37424 # Number of stores executed +system.cpu3.iew.exec_rate 1.342091 # Inst execution rate +system.cpu3.iew.wb_sent 237529 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 237209 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 134044 # num instructions producing a value +system.cpu3.iew.wb_consumers 138720 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.338485 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.966292 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1266 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165699 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.633836 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.016583 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 68017 41.05% 41.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 47143 28.45% 69.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6068 3.66% 73.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7148 4.31% 77.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1577 0.95% 78.43% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 33420 20.17% 98.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 508 0.31% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 998 0.60% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 820 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 297438 # Number of instructions committed -system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165699 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 270725 # Number of instructions committed +system.cpu3.commit.committedOps 270725 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 129728 # Number of memory references committed -system.cpu3.commit.loads 87775 # Number of loads committed -system.cpu3.commit.membars 4366 # Number of memory barriers committed -system.cpu3.commit.branches 52284 # Number of branches committed +system.cpu3.commit.refs 115239 # Number of memory references committed +system.cpu3.commit.loads 78487 # Number of loads committed +system.cpu3.commit.membars 5499 # Number of memory barriers committed +system.cpu3.commit.branches 48212 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 204138 # Number of committed integer instructions. +system.cpu3.commit.int_insts 185574 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 473500 # The number of ROB reads -system.cpu3.rob.rob_writes 621006 # The number of ROB writes -system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 249993 # Number of Instructions Simulated -system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated -system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 453881 # number of integer regfile reads -system.cpu3.int_regfile_writes 211087 # number of integer regfile writes +system.cpu3.rob.rob_reads 447315 # The number of ROB reads +system.cpu3.rob.rob_writes 568397 # The number of ROB writes +system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1402 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 226224 # Number of Instructions Simulated +system.cpu3.committedOps 226224 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 226224 # Number of Instructions Simulated +system.cpu3.cpi 0.783392 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.783392 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 410473 # number of integer regfile reads +system.cpu3.int_regfile_writes 191401 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads +system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 79.942849 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits -system.cpu3.icache.overall_hits::total 17724 # number of overall hits +system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942849 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 20090 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 20090 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 20090 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 20090 # number of overall hits +system.cpu3.icache.overall_hits::total 20090 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449245 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6449245 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6449245 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6449245 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6449245 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6449245 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 20565 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 20565 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 20565 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023097 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023097 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13577.357895 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13577.357895 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2434,106 +2440,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223255 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223255 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223255 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5223255 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223255 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5223255 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.692253 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 92475 # number of overall hits -system.cpu3.dcache.overall_hits::total 92475 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 346 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 346 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 484 # number of overall misses -system.cpu3.dcache.overall_misses::total 484 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4449419 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4449419 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2879011 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2879011 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 478509 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 478509 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7328430 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7328430 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7328430 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7328430 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 51069 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692253 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 46656 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 36553 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 36553 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 83209 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 83209 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 83209 # number of overall hits +system.cpu3.dcache.overall_hits::total 83209 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 333 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 333 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 464 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses +system.cpu3.dcache.overall_misses::total 464 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4249100 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4249100 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3352512 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3352512 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7601612 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7601612 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7601612 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7601612 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 36684 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 83673 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 83673 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 83673 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 83673 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007087 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.007087 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003571 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003571 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2542,54 +2548,54 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1003763 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1003763 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1322239 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1322239 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 376491 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 376491 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2326002 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2326002 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2326002 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 181 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 212 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 212 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 212 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 212 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 252 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408738 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408738 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2411262 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2411262 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2411262 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2411262 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003012 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt index 4e4b75a44..9c1ab67e5 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 12102739985 # Simulator tick rate (ticks/s) -host_mem_usage 228608 # Number of bytes of host memory used -host_seconds 8.26 # Real time elapsed on the host +host_tick_rate 20181472495 # Simulator tick rate (ticks/s) +host_mem_usage 192916 # Number of bytes of host memory used +host_seconds 4.96 # Real time elapsed on the host system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory @@ -15,77 +15,79 @@ system.physmem.bw_read::cpu 2133311360 # To system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 213331136 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 217600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 210100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.readReqs 3333300 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3333300 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 213331200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 213331200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 217600 # Per bank write bursts +system.physmem.perBankRdBursts::1 217600 # Per bank write bursts +system.physmem.perBankRdBursts::2 217600 # Per bank write bursts +system.physmem.perBankRdBursts::3 217600 # Per bank write bursts +system.physmem.perBankRdBursts::4 210100 # Per bank write bursts +system.physmem.perBankRdBursts::5 204800 # Per bank write bursts +system.physmem.perBankRdBursts::6 204800 # Per bank write bursts +system.physmem.perBankRdBursts::7 204800 # Per bank write bursts +system.physmem.perBankRdBursts::8 204800 # Per bank write bursts +system.physmem.perBankRdBursts::9 204800 # Per bank write bursts +system.physmem.perBankRdBursts::10 204800 # Per bank write bursts +system.physmem.perBankRdBursts::11 204800 # Per bank write bursts +system.physmem.perBankRdBursts::12 204800 # Per bank write bursts +system.physmem.perBankRdBursts::13 204800 # Per bank write bursts +system.physmem.perBankRdBursts::14 204800 # Per bank write bursts +system.physmem.perBankRdBursts::15 204800 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 99999960000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3333300 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3301421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 26232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3333300 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3150208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 17179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 12820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4489 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -138,35 +140,135 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 26100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 8168.810421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 8140.398372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.874580 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 16 0.06% 0.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 99 0.38% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 25985 99.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 26100 # Bytes accessed per row activation -system.physmem.totQLat 1278758950 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 63884930200 # Sum of mem lat for all requests -system.physmem.totBusLat 16666500000 # Total cycles spent in databus access -system.physmem.totBankLat 45939671250 # Total cycles spent in bank access -system.physmem.avgQLat 383.63 # Average queueing delay per request -system.physmem.avgBankLat 13782.04 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19165.67 # Average memory access latency -system.physmem.avgRdBW 2133.31 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2133.31 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 38918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5478.771982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 4240.637477 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2732.249719 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 284 0.73% 0.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 264 0.68% 1.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 268 0.69% 2.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 268 0.69% 2.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 266 0.68% 3.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 271 0.70% 4.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 268 0.69% 4.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 264 0.68% 5.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 268 0.69% 6.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 270 0.69% 6.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 267 0.69% 7.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 268 0.69% 8.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 268 0.69% 8.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 264 0.68% 9.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 270 0.69% 10.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.01% 10.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 268 0.69% 11.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 264 0.68% 11.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 268 0.69% 12.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 268 0.69% 13.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 267 0.69% 13.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 271 0.70% 14.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 268 0.69% 15.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 264 0.68% 15.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 268 0.69% 16.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 271 0.70% 17.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 266 0.68% 17.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 268 0.69% 18.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 268 0.69% 19.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 264 0.68% 19.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 271 0.70% 20.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.01% 20.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 268 0.69% 21.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 264 0.68% 22.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 268 0.69% 22.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 268 0.69% 23.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 267 0.69% 24.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 270 0.69% 24.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 268 0.69% 25.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 264 0.68% 26.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 268 0.69% 26.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 349 0.90% 27.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 264 0.68% 28.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 268 0.69% 29.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 268 0.69% 29.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 264 0.68% 30.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 268 0.69% 31.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 268 0.69% 31.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 264 0.68% 32.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 268 0.69% 33.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 268 0.69% 33.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 264 0.68% 34.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 268 0.69% 35.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 268 0.69% 35.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 264 0.68% 36.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 268 0.69% 37.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 268 0.69% 38.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 264 0.68% 38.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 268 0.69% 39.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 268 0.69% 40.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 264 0.68% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 268 0.69% 41.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 267 0.69% 42.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 264 0.68% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 268 0.69% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 267 0.69% 44.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 264 0.68% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 268 0.69% 45.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 267 0.69% 46.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 264 0.68% 46.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 268 0.69% 47.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 267 0.69% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 264 0.68% 48.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 268 0.69% 49.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 267 0.69% 50.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 264 0.68% 51.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 268 0.69% 51.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 267 0.69% 52.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 264 0.68% 53.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 268 0.69% 53.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 267 0.69% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 264 0.68% 55.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 268 0.69% 55.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 267 0.69% 56.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 264 0.68% 57.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 268 0.69% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 268 0.69% 58.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 264 0.68% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 268 0.69% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 268 0.69% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 264 0.68% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 268 0.69% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 268 0.69% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 264 0.68% 63.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 268 0.69% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 268 0.69% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 264 0.68% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 268 0.69% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 13193 33.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38918 # Bytes accessed per row activation +system.physmem.totQLat 27766345550 # Total ticks spent queuing +system.physmem.totMemAccLat 88702111800 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 16666500000 # Total ticks spent in databus transfers +system.physmem.totBankLat 44269266250 # Total ticks spent accessing banks +system.physmem.avgQLat 8329.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13280.91 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26610.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2133.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2133.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 16.67 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.64 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3307200 # Number of row buffer hits during reads +system.physmem.busUtilRead 16.67 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.89 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 3294382 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 98.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 30000.29 # Average gap between requests +system.physmem.pageHitRate 98.83 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 2133311360 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3333300 # Transaction distribution system.membus.trans_dist::ReadResp 3333299 # Transaction distribution @@ -177,7 +279,7 @@ system.membus.tot_pkt_size::total 213331136 # Cu system.membus.data_through_bus 213331136 # Total data (bytes) system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 17154822550 # Layer occupancy (ticks) system.membus.respLayer0.utilization 17.2 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets @@ -231,8 +333,8 @@ system.monitor.writeBurstLengthHist::19 0 # Hi system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 2133311359.990499 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 6399.944145 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 2133311357.398473 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 105886.111402 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -284,20 +386,20 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333299 # Read request-response latency -system.monitor.readLatencyHist::mean 39172.137513 # Read request-response latency -system.monitor.readLatencyHist::gmean 38967.643311 # Read request-response latency -system.monitor.readLatencyHist::stdev 6823.352873 # Read request-response latency -system.monitor.readLatencyHist::0-32767 12686 0.38% 0.38% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 3289137 98.68% 99.06% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 26638 0.80% 99.85% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 937 0.03% 99.88% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 1073 0.03% 99.92% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 808 0.02% 99.94% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 670 0.02% 99.96% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 670 0.02% 99.98% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 272 0.01% 99.99% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 270 0.01% 100.00% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 138 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 46636.264419 # Read request-response latency +system.monitor.readLatencyHist::gmean 41775.198419 # Read request-response latency +system.monitor.readLatencyHist::stdev 39874.537130 # Read request-response latency +system.monitor.readLatencyHist::0-32767 0 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 3183561 95.51% 95.51% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 17049 0.51% 96.02% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 17311 0.52% 96.54% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 16920 0.51% 97.05% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 17049 0.51% 97.56% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 17311 0.52% 98.08% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 16917 0.51% 98.58% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 17052 0.51% 99.10% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 12954 0.39% 99.48% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 17175 0.52% 100.00% # Read request-response latency system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency @@ -418,17 +520,17 @@ system.monitor.ittReqReq::min_value 30000 # Re system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1 # Outstanding read transactions -system.monitor.outstandingReadsHist::gmean 1 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 0 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.270000 # Outstanding read transactions +system.monitor.outstandingReadsHist::gmean 1.105133 # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.135782 # Outstanding read transactions system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 100 100.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::4 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 94 94.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 0 0.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 0 0.00% 94.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 3 3.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 0 0.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::6 0 0.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::7 3 3.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions |