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authorAndreas Sandberg <andreas.sandberg@arm.com>2017-03-17 11:57:23 +0000
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-04-03 16:37:55 +0000
commitd2254e034e76dc23320ea1b300177a79e4818b61 (patch)
tree342e9210684cc6f44b7a194382089f341585b8a0
parentd7aef8be964b5f7eee2dace0cfc347fb23fa7ab2 (diff)
downloadgem5-d2254e034e76dc23320ea1b300177a79e4818b61.tar.xz
dev, arm: Fix multi-core KVM race in the generic timer
The generic timer sometimes needs to access global state. This can lead to race conditions when simulating a multi-core KVM system where each core lives in its own thread. In that case, the setMiscReg and readMiscReg methods are called from the thread owning the CPU and not the global device thread. Change-Id: Ie3e982258648c8562cce0b30a0c122dfbfaf42cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2460 Reviewed-by: Weiping Liao <weipingliao@google.com>
-rw-r--r--src/dev/arm/generic_timer.cc12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 1b8d917e9..d33090d74 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, 2015 ARM Limited
+ * Copyright (c) 2013, 2015, 2017 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -307,6 +307,11 @@ GenericTimer::createTimers(unsigned cpus)
void
GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
{
+ // This method might have been called from another context if we
+ // are running in multi-core KVM. Migrate to the SimObject's event
+ // queue to prevent surprising race conditions.
+ EventQueue::ScopedMigration migrate(eventQueue());
+
CoreTimers &core(getTimers(cpu));
switch (reg) {
@@ -399,6 +404,11 @@ GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
MiscReg
GenericTimer::readMiscReg(int reg, unsigned cpu)
{
+ // This method might have been called from another context if we
+ // are running in multi-core KVM. Migrate to the SimObject's event
+ // queue to prevent surprising race conditions.
+ EventQueue::ScopedMigration migrate(eventQueue());
+
CoreTimers &core(getTimers(cpu));
switch (reg) {