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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-09-01 15:38:13 +0100 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-09-13 07:25:04 +0000 |
| commit | d695a3c4c4478f08673bff255250444857d48094 (patch) | |
| tree | 653191c049190af646d4ea2f91e0c7a412dd142b | |
| parent | 2045a5c199c7c7597684c5d7501d5fb55aff9608 (diff) | |
| download | gem5-d695a3c4c4478f08673bff255250444857d48094.tar.xz | |
mem-cache: Fix bug in handleAtomicReqMiss
"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug
where if an atomic request that fills in using the tempBlock it will
not evict it when it finishes handling the request as it should. This
triggers an assertion. This change fixes this bug.
Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12644
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
| -rw-r--r-- | src/mem/cache/base.hh | 2 | ||||
| -rw-r--r-- | src/mem/cache/cache.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/cache.hh | 2 | ||||
| -rw-r--r-- | src/mem/cache/noncoherent_cache.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/noncoherent_cache.hh | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 4ba256b95..4ebc52493 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -506,7 +506,7 @@ class BaseCache : public MemObject * @param writebacks A list with packets for any performed writebacks * @return Cycles for handling the request */ - virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, + virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) = 0; /** diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 9b1612904..1b5316383 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -560,7 +560,7 @@ Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, Cycles -Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, +Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) { // deal with the packets that go through the write path of diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 32752a5e6..f8eccfee6 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -110,7 +110,7 @@ class Cache : public BaseCache void recvTimingSnoopResp(PacketPtr pkt) override; - Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, + Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) override; Tick recvAtomic(PacketPtr pkt) override; diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc index 50738375e..fb8193a99 100644 --- a/src/mem/cache/noncoherent_cache.cc +++ b/src/mem/cache/noncoherent_cache.cc @@ -170,7 +170,7 @@ NoncoherentCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, Cycles -NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, +NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) { PacketPtr bus_pkt = createMissPacket(pkt, blk, true); diff --git a/src/mem/cache/noncoherent_cache.hh b/src/mem/cache/noncoherent_cache.hh index 09012ba10..2a60f4c5e 100644 --- a/src/mem/cache/noncoherent_cache.hh +++ b/src/mem/cache/noncoherent_cache.hh @@ -98,7 +98,7 @@ class NoncoherentCache : public BaseCache panic("Unexpected timing snoop response %s", pkt->print()); } - Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, + Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) override; Tick recvAtomic(PacketPtr pkt) override; |