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authorAli Saidi <saidi@eecs.umich.edu>2007-02-13 15:58:06 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-02-13 15:58:06 -0500
commite3dcbc94f77302b23365d191d43d60b1425c76b1 (patch)
treef7bf5217596671ddd9dddb028c11084158117d46
parentdc7ef3d489f3ae54383f4b7fd525f41d339c9895 (diff)
downloadgem5-e3dcbc94f77302b23365d191d43d60b1425c76b1.tar.xz
Make mulitple consoles work and be distinguishable from each other
src/dev/alpha/tsunamireg.h: get rid of things that aren't really tsunami registers src/dev/platform.hh: src/dev/uart.cc: the uart pointer isn't used anymore src/dev/simconsole.cc: make the simconsole print something more useful to distinguish between various consoles in a single system src/dev/uart8250.hh: put the needed uart defines in here rather than including them from tsunamireg src/python/m5/objects/T1000.py: add a console to the T1000 config for the hypervisor --HG-- extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
-rw-r--r--src/dev/alpha/tsunamireg.h21
-rw-r--r--src/dev/platform.hh3
-rw-r--r--src/dev/simconsole.cc7
-rw-r--r--src/dev/uart.cc1
-rw-r--r--src/dev/uart8250.hh13
-rw-r--r--src/python/m5/objects/T1000.py5
6 files changed, 22 insertions, 28 deletions
diff --git a/src/dev/alpha/tsunamireg.h b/src/dev/alpha/tsunamireg.h
index d603972be..a2742e36d 100644
--- a/src/dev/alpha/tsunamireg.h
+++ b/src/dev/alpha/tsunamireg.h
@@ -136,15 +136,6 @@
/* Added for keyboard accesses */
#define TSDEV_KBD 0x64
-/* Added for ATA PCI DMA */
-#define ATA_PCI_DMA 0x00
-#define ATA_PCI_DMA2 0x02
-#define ATA_PCI_DMA3 0x16
-#define ATA_PCI_DMA4 0x17
-#define ATA_PCI_DMA5 0x1a
-#define ATA_PCI_DMA6 0x11
-#define ATA_PCI_DMA7 0x14
-
#define TSDEV_RTC_ADDR 0x70
#define TSDEV_RTC_DATA 0x71
@@ -155,18 +146,6 @@
#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
-// UART Defines
-#define UART_IER_RDI 0x01
-#define UART_IER_THRI 0x02
-#define UART_IER_RLSI 0x04
-
-
-#define UART_LSR_TEMT 0x40
-#define UART_LSR_THRE 0x20
-#define UART_LSR_DR 0x01
-
-#define UART_MCR_LOOP 0x10
-
// System Control PortB Status Bits
#define PORTB_SPKR_HIGH 0x20
diff --git a/src/dev/platform.hh b/src/dev/platform.hh
index 1940dcad6..aceec0970 100644
--- a/src/dev/platform.hh
+++ b/src/dev/platform.hh
@@ -55,9 +55,6 @@ class Platform : public SimObject
/** Pointer to the interrupt controller */
IntrControl *intrctrl;
- /** Pointer to the UART, set by the uart */
- Uart *uart;
-
/** Pointer to the system for info about the memory system. */
System *system;
diff --git a/src/dev/simconsole.cc b/src/dev/simconsole.cc
index 77aafd9fa..903368491 100644
--- a/src/dev/simconsole.cc
+++ b/src/dev/simconsole.cc
@@ -364,7 +364,12 @@ ConsoleListener::listen(int port)
port++;
}
- ccprintf(cerr, "Listening for console connection on port %d\n", port);
+
+ int p1, p2;
+ p2 = name().rfind('.') - 1;
+ p1 = name().rfind('.', p2);
+ ccprintf(cerr, "Listening for %s connection on port %d\n",
+ name().substr(p1+1,p2-p1), port);
event = new Event(this, listener.getfd(), POLLIN);
pollQueue.schedule(event);
diff --git a/src/dev/uart.cc b/src/dev/uart.cc
index f769b720b..1c781f76d 100644
--- a/src/dev/uart.cc
+++ b/src/dev/uart.cc
@@ -47,7 +47,6 @@ Uart::Uart(Params *p)
// set back pointers
cons->uart = this;
- platform->uart = this;
}
DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh
index a0620c7e0..c28200592 100644
--- a/src/dev/uart8250.hh
+++ b/src/dev/uart8250.hh
@@ -35,7 +35,6 @@
#ifndef __DEV_UART8250_HH__
#define __DEV_UART8250_HH__
-#include "dev/alpha/tsunamireg.h"
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/uart.hh"
@@ -54,6 +53,18 @@ const uint8_t IIR_TXID = 0x02; /* Tx Data */
const uint8_t IIR_RXID = 0x04; /* Rx Data */
const uint8_t IIR_LINE = 0x06; /* Rx Line Status (highest priority)*/
+const uint8_t UART_IER_RDI = 0x01;
+const uint8_t UART_IER_THRI = 0x02;
+const uint8_t UART_IER_RLSI = 0x04;
+
+
+const uint8_t UART_LSR_TEMT = 0x40;
+const uint8_t UART_LSR_THRE = 0x20;
+const uint8_t UART_LSR_DR = 0x01;
+
+const uint8_t UART_MCR_LOOP = 0x10;
+
+
class SimConsole;
class Platform;
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index 85c4db6df..3ab6d4283 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -69,16 +69,19 @@ class T1000(Platform):
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
+ hconsole = SimConsole(listener = ConsoleListener())
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()
+ pconsole = SimConsole(listener = ConsoleListener())
puart0 = Uart8250(pio_addr=0x1f10000000)
- console = SimConsole(listener = ConsoleListener())
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
+ self.hvuart.sim_console = self.hconsole
+ self.puart0.sim_console = self.pconsole
self.fake_clk.pio = bus.port
self.fake_membnks.pio = bus.port
self.fake_iob.pio = bus.port