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authorGabe Black <gblack@eecs.umich.edu>2009-04-19 04:56:43 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-19 04:56:43 -0700
commite475cf85f0ff50b3e997a00bc0af822c86b9d826 (patch)
tree822ae5b13cb8da374145b432049cb4cd8b9bd996
parent43f58927d693fbe18a7db2e20f540da13bc15cd3 (diff)
downloadgem5-e475cf85f0ff50b3e997a00bc0af822c86b9d826.tar.xz
X86: Implement a locking version of BTR.
-rw-r--r--src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py46
1 files changed, 46 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
index bc222300d..4dca52010 100644
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
@@ -214,6 +214,27 @@ def macroop BTR_P_I {
st t1, seg, riprel, disp
};
+def macroop BTR_LOCKED_M_I {
+ limm t1, imm, dataSize=asz
+ limm t4, "(uint64_t(-(2ULL)))"
+ roli t4, t4, imm
+ ldstl t1, seg, sib, disp
+ sexti t0, t1, imm, flags=(CF,)
+ and t1, t1, t4
+ stul t1, seg, sib, disp
+};
+
+def macroop BTR_LOCKED_P_I {
+ rdip t7, dataSize=asz
+ limm t1, imm, dataSize=asz
+ limm t4, "(uint64_t(-(2ULL)))"
+ roli t4, t4, imm
+ ldstl t1, seg, riprel, disp
+ sexti t0, t1, imm, flags=(CF,)
+ and t1, t1, t4
+ stul t1, seg, riprel, disp
+};
+
def macroop BTR_R_R {
sext t0, reg, regm, flags=(CF,)
limm t1, "(uint64_t(-(2ULL)))"
@@ -246,6 +267,31 @@ def macroop BTR_P_R {
st t1, seg, [1, t3, t7], disp
};
+def macroop BTR_LOCKED_M_R {
+ srai t2, reg, 3, dataSize=asz
+ srai t3, t2, ldsz, dataSize=asz
+ lea t3, flatseg, [dsz, t3, base], dataSize=asz
+ limm t4, "(uint64_t(-(2ULL)))"
+ rol t4, t4, reg
+ ldstl t1, seg, [scale, index, t3], disp
+ sext t0, t1, reg, flags=(CF,)
+ and t1, t1, t4
+ stul t1, seg, [scale, index, t3], disp
+};
+
+def macroop BTR_LOCKED_P_R {
+ rdip t7, dataSize=asz
+ srai t2, reg, 3, dataSize=asz
+ srai t3, t2, ldsz, dataSize=asz
+ lea t3, flatseg, [dsz, t3, base], dataSize=asz
+ limm t4, "(uint64_t(-(2ULL)))"
+ rol t4, t4, reg
+ ldstl t1, seg, [1, t3, t7], disp
+ sext t0, t1, reg, flags=(CF,)
+ and t1, t1, t4
+ stul t1, seg, [1, t3, t7], disp
+};
+
def macroop BTS_R_I {
sexti t0, reg, imm, flags=(CF,)
limm t1, 1