cache: Allow main memory to be at disjoint address ranges.

21 files changed, 25 insertions, 27 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 7a0759e47..19c1bd81f 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -159,7 +159,7 @@ if bm[0]:
 else:
     mem_size = SysConfig().mem()
 if options.caches or options.l2cache:
-    test_sys.iocache = IOCache(addr_range=test_sys.physmem.range)
+    test_sys.iocache = IOCache(addr_ranges=[mem_size])
     test_sys.iocache.cpu_side = test_sys.iobus.master
     test_sys.iocache.mem_side = test_sys.membus.slave
 else:
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index adc48a461..83b3c70c2 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -60,5 +60,5 @@ class BaseCache(MemObject):
     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
     cpu_side = SlavePort("Port on side closer to CPU")
     mem_side = MasterPort("Port on side closer to MEM")
-    addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
+    addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
     system = Param.System(Parent.any, "System we belong to")
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index c7c213cc6..fb2757616 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -83,7 +83,7 @@ BaseCache::BaseCache(const Params *p)
       noTargetMSHR(NULL),
       missCount(p->max_miss_count),
       drainEvent(NULL),
-      addrRange(p->addr_range),
+      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
       system(p->system)
 {
 }
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index e522bc0c9..2a79fb354 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -269,7 +269,7 @@ class BaseCache : public MemObject
     /**
      * The address range to which the cache responds on the CPU side.
      * Normally this is all possible memory addresses. */
-    Range<Addr> addrRange;
+    AddrRangeList addrRanges;
 
   public:
     /** System we are currently operating in. */
@@ -439,7 +439,7 @@ class BaseCache : public MemObject
     Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
 
 
-    const Range<Addr> &getAddrRange() const { return addrRange; }
+    const AddrRangeList &getAddrRanges() const { return addrRanges; }
 
     MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
     {
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 024ae3297..f6efc3fb8 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1556,9 +1556,7 @@ template<class TagStore>
 AddrRangeList
 Cache<TagStore>::CpuSidePort::getAddrRanges()
 {
-    AddrRangeList ranges;
-    ranges.push_back(cache->getAddrRange());
-    return ranges;
+    return cache->getAddrRanges();
 }
 
 template<class TagStore>
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index f35812085..0b8b9381f 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -77,7 +77,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range = AddrRange(0, size=mem_size)
+    addr_ranges = [AddrRange(0, size=mem_size)]
     forward_snoops = False
 
 #cpu
@@ -86,7 +86,7 @@ cpu = DerivO3CPU(cpu_id=0)
 mdesc = SysConfig(disk = 'linux-x86.img')
 system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
-system.iocache = IOCache(addr_range=mem_size)
+system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index b78cb9495..77cd1319f 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -78,7 +78,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range = AddrRange(0, size=mem_size)
+    addr_ranges = [AddrRange(0, size=mem_size)]
     forward_snoops = False
     is_top_level = True
 
@@ -88,7 +88,7 @@ cpu = AtomicSimpleCPU(cpu_id=0)
 mdesc = SysConfig(disk = 'linux-x86.img')
 system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
-system.iocache = IOCache(addr_range=mem_size)
+system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index b5117f2fe..fbe6b4c4f 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -78,7 +78,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range = AddrRange(0, size=mem_size)
+    addr_ranges = [AddrRange(0, size=mem_size)]
     forward_snoops = False
 
 #cpu
@@ -91,7 +91,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 system.cpu = cpu
 #create the l1/l2 bus
 system.toL2Bus = Bus()
-system.iocache = IOCache(addr_range=mem_size)
+system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
 
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 2f06ab2d7..71b4f06dd 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='256MB')
+    addr_ranges = [AddrRange(0, size='256MB')]
     forward_snoops = False
 
 #cpu
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index 795bd534a..db64ccc60 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='256MB')
+    addr_ranges = [AddrRange(0, size='256MB')]
     forward_snoops = False
 
 #cpu
diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index daee4f478..eef5e90c5 100644
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='256MB')
+    addr_ranges = [AddrRange(0, size='256MB')]
     forward_snoops = False
 
 #cpu
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index f6377d21d..0544c98b6 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -63,7 +63,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='256MB')
+    addr_ranges = [AddrRange(0, size='256MB')]
     forward_snoops = False
 
 #cpu
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index c610bc432..edc2b7a95 100644
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='256MB')
+    addr_ranges = [AddrRange(0, size='256MB')]
     forward_snoops = False
 
 #cpu
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index a55358306..6e539624b 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='256MB')
+    addr_ranges = [AddrRange(0, size='256MB')]
     forward_snoops = False
 
 #cpu
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index 0c3323f62..41df45fab 100644
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='8GB')
+    addr_ranges = [AddrRange(0, size='8GB')]
     forward_snoops = False
     is_top_level = True
 
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index 603664d53..d50a45b07 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='8GB')
+    addr_ranges = [AddrRange(0, size='8GB')]
     forward_snoops = False
     is_top_level = True
 
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index ce64c497f..c5a3236a5 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='8GB')
+    addr_ranges = [AddrRange(0, size='8GB')]
     forward_snoops = False
     is_top_level = True
 
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index f242c80cc..57672b0e1 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -63,7 +63,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='8GB')
+    addr_ranges = [AddrRange(0, size='8GB')]
     forward_snoops = False
     is_top_level = True
 
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 456dc5da6..8a03760e3 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -63,7 +63,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='8GB')
+    addr_ranges = [AddrRange(0, size='8GB')]
     forward_snoops = False
     is_top_level = True
 
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 56daf0dd3..1b905a8d0 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -63,7 +63,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='8GB')
+    addr_ranges = [AddrRange(0, size='8GB')]
     forward_snoops = False
     is_top_level = True
 
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index ef055e38e..e4920ddf4 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
-    addr_range=AddrRange(0, size='8GB')
+    addr_ranges = [AddrRange(0, size='8GB')]
     forward_snoops = False
     is_top_level = True