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| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-11-06 13:07:28 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-18 09:14:08 +0000 |
| commit | ec9ce6239d0c3a4e6141961bfb9caae50b9caac9 (patch) | |
| tree | ceffaea840aa448c2a9de043a36201ea6696c5f6 | |
| parent | b18c2e575ee079b873767b57604138e00bc1c465 (diff) | |
| download | gem5-ec9ce6239d0c3a4e6141961bfb9caae50b9caac9.tar.xz | |
arch-arm: Secure EL2 checking
This patch adds Armv8.4-SecEL2 checking. Helpers implementing
EL2Enabled, IsSecureEL2Enabled and HaveSecureEL2Ext following
the architecture pseudocode are provided. These are intended
to be used for checking register access permissions.
Change-Id: I3d06d0127cf165c1eeaf3302830742d610cef719
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23766
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/arch/arm/miscregs_types.hh | 7 | ||||
| -rw-r--r-- | src/arch/arm/utility.cc | 28 | ||||
| -rw-r--r-- | src/arch/arm/utility.hh | 4 |
3 files changed, 36 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh index 20265e294..07e2262b3 100644 --- a/src/arch/arm/miscregs_types.hh +++ b/src/arch/arm/miscregs_types.hh @@ -294,14 +294,15 @@ namespace ArmISA EndBitUnion(NSACR) BitUnion32(SCR) + Bitfield<18> eel2; // AArch64 (Armv8.4-SecEL2) Bitfield<13> twe; Bitfield<12> twi; - Bitfield<11> st; // AArch64 - Bitfield<10> rw; // AArch64 + Bitfield<11> st; // AArch64 + Bitfield<10> rw; // AArch64 Bitfield<9> sif; Bitfield<8> hce; Bitfield<7> scd; - Bitfield<7> smd; // AArch64 + Bitfield<7> smd; // AArch64 Bitfield<6> nEt; Bitfield<5> aw; Bitfield<4> fw; diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index d68850c5f..5ab56453b 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -290,6 +290,34 @@ getMPIDR(ArmSystem *arm_sys, ThreadContext *tc) } bool +HaveSecureEL2Ext(ThreadContext *tc) +{ + AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1); + return id_aa64pfr0.sel2; +} + +bool +IsSecureEL2Enabled(ThreadContext *tc) +{ + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); + if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc)) { + if (ArmSystem::haveEL(tc, EL3)) + return !ELIs32(tc, EL3) && scr.eel2; + else + return inSecureState(tc); + } + return false; +} + +bool +EL2Enabled(ThreadContext *tc) +{ + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); + return ArmSystem::haveEL(tc, EL2) && + (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc)); +} + +bool ELIs64(ThreadContext *tc, ExceptionLevel el) { return !ELIs32(tc, el); diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 96f6843c3..7ec44f8e2 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -166,6 +166,10 @@ currEL(CPSR cpsr) return opModeToEL((OperatingMode) (uint8_t)cpsr.mode); } +bool HaveSecureEL2Ext(ThreadContext *tc); +bool IsSecureEL2Enabled(ThreadContext *tc); +bool EL2Enabled(ThreadContext *tc); + /** * This function checks whether selected EL provided as an argument * is using the AArch32 ISA. This information might be unavailable |