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authorGabe Black <gblack@eecs.umich.edu>2007-07-23 11:20:57 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-23 11:20:57 -0700
commitecf2621f4f2dedfea03816e61ec6dc0f24a62c0e (patch)
treec68486dec3d71170c1860768c704c568622deb66
parent85f9415a67f3f3b54a615c2e29576235d11428f3 (diff)
downloadgem5-ecf2621f4f2dedfea03816e61ec6dc0f24a62c0e.tar.xz
Implement pusha, popa, three operand imul, hook them into the decoder, and clean up the decoder a little.
--HG-- extra : convert_revision : c1b8f0f433f629e4104e2b04addcdaabf57595e3
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa40
-rw-r--r--src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py21
-rw-r--r--src/arch/x86/isa/insts/data_transfer/stack_operations.py60
3 files changed, 93 insertions, 28 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 9a70e9f4f..bf19ed78e 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -160,28 +160,28 @@
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
- 0x08: decode MODE_SUBMODE {
- 0x0: M5InternalError::error (
- {{"Tried to execute an REX prefix!"}});
- default: Inst::INC(B);
- }
- 0x09: decode MODE_SUBMODE {
- 0x0: M5InternalError::error (
- {{"Tried to execute an REX prefix!"}});
- default: Inst::DEC(B);
- }
format Inst {
- 0x0A: PUSH(B);
- 0x0B: POP(B);
+ 0x08: decode MODE_SUBMODE {
+ 0x0: M5InternalError::error (
+ {{"Tried to execute an REX prefix!"}});
+ default: INC(Bv);
+ }
+ 0x09: decode MODE_SUBMODE {
+ 0x0: M5InternalError::error (
+ {{"Tried to execute an REX prefix!"}});
+ default: DEC(Bv);
+ }
+ 0x0A: PUSH(Bv);
+ 0x0B: POP(Bv);
}
0x0C: decode OPCODE_OP_BOTTOM3 {
0x0: decode MODE_SUBMODE {
0x0: Inst::UD2();
- default: pusha();
+ default: Inst::PUSHA();
}
0x1: decode MODE_SUBMODE {
0x0: Inst::UD2();
- default: popa();
+ default: Inst::POPA();
}
0x2: decode MODE_SUBMODE {
0x0: Inst::UD2();
@@ -204,10 +204,10 @@
{{"Tried to execute the DS address size override prefix!"}});
}
0x0D: decode OPCODE_OP_BOTTOM3 {
- 0x0: push_Iz();
- 0x1: imul_Gv_Ev_Iz();
- 0x2: push_Ib();
- 0x3: imul_Gv_Ev_Ib();
+ 0x0: Inst::PUSH(Iz);
+ 0x1: Inst::IMUL(Gv,Ev,Iz);
+ 0x2: Inst::PUSH(Ib);
+ 0x3: Inst::IMUL(Gv,Ev,Ib);
0x4: ins_Yb_Dx();
0x5: ins_Yz_Dx();
0x6: outs_Dx_Xb();
@@ -346,8 +346,8 @@
0x7: scas_Yv_rAX();
}
format Inst {
- 0x16: MOV(B,Ib);
- 0x17: MOV(B,Iv);
+ 0x16: MOV(Bb,Ib);
+ 0x17: MOV(Bv,Iv);
0x18: decode OPCODE_OP_BOTTOM3 {
//0x0: group2_Eb_Ib();
0x0: decode MODRM_REG {
diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 8697bef65..339e18cf8 100644
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -77,6 +77,27 @@ def macroop IMUL_R_P
ld t1, ds, [scale, index, base], disp
mul1s reg, reg, t1
};
+
+def macroop IMUL_R_R_I
+{
+ limm t1, imm
+ mul1s reg, regm, t1
+};
+
+def macroop IMUL_R_M_I
+{
+ limm t1, imm
+ ld t2, ds, [scale, index, base], disp
+ mul1s reg, t2, t1
+};
+
+def macroop IMUL_R_P_I
+{
+ rdip t7
+ limm t1, imm
+ ld t2, ds, [0, t0, t7]
+ mul1s reg, t2, t1
+};
'''
#let {{
# class MUL(Inst):
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index c381dc4f4..889e7b88b 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -62,6 +62,25 @@ def macroop POP_R {
addi rsp, rsp, dsz
};
+def macroop POP_M {
+ # Make the default data size of pops 64 bits in 64 bit mode
+ .adjust_env oszIn64Override
+
+ ld t1, ss, [0, t0, rsp]
+ addi rsp, rsp, dsz
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop POP_P {
+ # Make the default data size of pops 64 bits in 64 bit mode
+ .adjust_env oszIn64Override
+
+ rdip t7
+ ld t1, ss, [0, t0, rsp]
+ addi rsp, rsp, dsz
+ st t1, ds, [0, t0, t7]
+};
+
def macroop PUSH_R {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
@@ -70,6 +89,15 @@ def macroop PUSH_R {
st reg, ss, [0, t0, rsp]
};
+def macroop PUSH_I {
+ # Make the default data size of pops 64 bits in 64 bit mode
+ .adjust_env oszIn64Override
+
+ limm t1, imm
+ subi rsp, rsp, dsz
+ st t1, ss, [0, t0, rsp]
+};
+
def macroop PUSH_M {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
@@ -88,16 +116,32 @@ def macroop PUSH_P {
subi rsp, rsp, dsz
st t1, ss, [0, t0, rsp]
};
+
+def macroop PUSHA {
+ st rax, ss, [0, t0, rsp], "-0 * env.dataSize"
+ st rcx, ss, [0, t0, rsp], "-1 * env.dataSize"
+ st rdx, ss, [0, t0, rsp], "-2 * env.dataSize"
+ st rbx, ss, [0, t0, rsp], "-3 * env.dataSize"
+ st rsp, ss, [0, t0, rsp], "-4 * env.dataSize"
+ st rbp, ss, [0, t0, rsp], "-5 * env.dataSize"
+ st rsi, ss, [0, t0, rsp], "-6 * env.dataSize"
+ st rdi, ss, [0, t0, rsp], "-7 * env.dataSize"
+ subi rsp, rsp, "8 * env.dataSize"
+};
+
+def macroop POPA {
+ st rdi, ss, [0, t0, rsp], "0 * env.dataSize"
+ st rsi, ss, [0, t0, rsp], "1 * env.dataSize"
+ st rbp, ss, [0, t0, rsp], "2 * env.dataSize"
+ st rsp, ss, [0, t0, rsp], "3 * env.dataSize"
+ st rbx, ss, [0, t0, rsp], "4 * env.dataSize"
+ st rdx, ss, [0, t0, rsp], "5 * env.dataSize"
+ st rcx, ss, [0, t0, rsp], "6 * env.dataSize"
+ st rax, ss, [0, t0, rsp], "7 * env.dataSize"
+ addi rsp, rsp, "8 * env.dataSize"
+};
'''
#let {{
-# class POPA(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class POPAD(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class PUSHA(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class PUSHAD(Inst):
-# "GenFault ${new UnimpInstFault}"
# class ENTER(Inst):
# "GenFault ${new UnimpInstFault}"
# class LEAVE(Inst):