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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
| commit | 221e0ac5234b60283753af5d7173199085ededa6 (patch) | |
| tree | a27f0acb5209f6a1d777e7b6ee22dca541856840 /AUTHORS | |
| parent | 8c1be04af62a333cff54aa5f349e8bb9e203f267 (diff) | |
| download | gem5-221e0ac5234b60283753af5d7173199085ededa6.tar.xz | |
ARM: Warn about and ignore accesses to DCCISW.
This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.
Diffstat (limited to 'AUTHORS')
0 files changed, 0 insertions, 0 deletions