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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-25 11:14:47 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-22 09:17:22 +0000 |
| commit | 12eac0c88e21ddc76593079127a4507558cddc40 (patch) | |
| tree | 00cd013d61e15795421a8ea9d5cafe6c6c62ba33 /MAINTAINERS | |
| parent | a0649ee1e90e6c71f74425457c381e8b6c5d0d43 (diff) | |
| download | gem5-12eac0c88e21ddc76593079127a4507558cddc40.tar.xz | |
arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
Moving AArch32 instruction accessing IMPLEMENTATION DEFINED registers
from pseudo.[cc/hh] to misc.[cc/hh] in order to symmetrically match
with AArch64 implementation.
Change-Id: I27b0d65925d7965589b765269ae54129426e4c88
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15735
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions