Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.

They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76

1 files changed, 25 insertions, 22 deletions

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index d00186d95..fb619d8b3 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -293,12 +293,11 @@ AlphaITB::regStats()
 void
 AlphaITB::fault(Addr pc, ExecContext *xc) const
 {
-    uint64_t *ipr = xc->regs.ipr;
-
     if (!xc->misspeculating()) {
-        ipr[AlphaISA::IPR_ITB_TAG] = pc;
-        ipr[AlphaISA::IPR_IFAULT_VA_FORM] =
-            ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3);
+        xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
+        xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
+                       xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
+                       (AlphaISA::VAddr(pc).vpn() << 3));
     }
 }
 
@@ -306,7 +305,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const
 Fault
 AlphaITB::translate(MemReqPtr &req) const
 {
-    InternalProcReg *ipr = req->xc->regs.ipr;
+    ExecContext *xc = req->xc;
 
     if (AlphaISA::PcPAL(req->vaddr)) {
         // strip off PAL PC marker (lsb is 1)
@@ -329,13 +328,13 @@ AlphaITB::translate(MemReqPtr &req) const
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
         // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
 #if ALPHA_TLASER
-        if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+        if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
             VAddrSpaceEV5(req->vaddr) == 2) {
 #else
         if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
 #endif
             // only valid in kernel mode
-            if (ICM_CM(ipr[AlphaISA::IPR_ICM]) !=
+            if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
                 AlphaISA::mode_kernel) {
                 fault(req->vaddr, req->xc);
                 acv++;
@@ -354,8 +353,9 @@ AlphaITB::translate(MemReqPtr &req) const
 
         } else {
             // not a physical address: need to look up pte
+            int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
             AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
-                                        DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+                                        asn);
 
             if (!pte) {
                 fault(req->vaddr, req->xc);
@@ -367,7 +367,8 @@ AlphaITB::translate(MemReqPtr &req) const
                 (AlphaISA::VAddr(req->vaddr).offset() & ~3);
 
             // check permissions for this access
-            if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) {
+            if (!(pte->xre &
+                  (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
                 // instruction access fault
                 fault(req->vaddr, req->xc);
                 acv++;
@@ -469,7 +470,6 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
 {
     ExecContext *xc = req->xc;
     AlphaISA::VAddr vaddr = req->vaddr;
-    uint64_t *ipr = xc->regs.ipr;
 
     // Set fault address and flags.  Even though we're modeling an
     // EV5, we use the EV6 technique of not latching fault registers
@@ -479,17 +479,17 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
     if (!xc->misspeculating()
         && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) {
         // set VA register with faulting address
-        ipr[AlphaISA::IPR_VA] = req->vaddr;
+        xc->setMiscReg(AlphaISA::IPR_VA, req->vaddr);
 
         // set MM_STAT register flags
-        ipr[AlphaISA::IPR_MM_STAT] =
+        xc->setMiscReg(AlphaISA::IPR_MM_STAT,
             (((Opcode(xc->getInst()) & 0x3f) << 11)
              | ((Ra(xc->getInst()) & 0x1f) << 6)
-             | (flags & 0x3f));
+             | (flags & 0x3f)));
 
         // set VA_FORM register with faulting formatted address
-        ipr[AlphaISA::IPR_VA_FORM] =
-            ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3);
+        xc->setMiscReg(AlphaISA::IPR_VA_FORM,
+            xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
     }
 }
 
@@ -497,11 +497,11 @@ Fault
 AlphaDTB::translate(MemReqPtr &req, bool write) const
 {
     RegFile *regs = &req->xc->regs;
+    ExecContext *xc = req->xc;
     Addr pc = regs->pc;
-    InternalProcReg *ipr = regs->ipr;
 
     AlphaISA::mode_type mode =
-        (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
+        (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
 
 
     /**
@@ -516,7 +516,8 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
 
     if (pc & 0x1) {
         mode = (req->flags & ALTMODE) ?
-            (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])
+            (AlphaISA::mode_type)ALT_MODE_AM(
+                xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
             : AlphaISA::mode_kernel;
     }
 
@@ -535,14 +536,14 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
 
         // Check for "superpage" mapping
 #if ALPHA_TLASER
-        if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
+        if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
             VAddrSpaceEV5(req->vaddr) == 2) {
 #else
         if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
 #endif
 
             // only valid in kernel mode
-            if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
+            if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
                 AlphaISA::mode_kernel) {
                 fault(req, ((write ? MM_STAT_WR_MASK : 0) |
                             MM_STAT_ACV_MASK));
@@ -566,9 +567,11 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
             else
                 read_accesses++;
 
+            int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
+
             // not a physical address: need to look up pte
             AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
-                                        DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+                                        asn);
 
             if (!pte) {
                 // page fault