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authorNathan Binkert <binkertn@umich.edu>2004-02-29 14:54:52 -0500
committerNathan Binkert <binkertn@umich.edu>2004-02-29 14:54:52 -0500
commit27960f6d858e92572d37604e92747d0b45591665 (patch)
treedd8ab574d000d74ebdf31269e017b992ab7d9a9a /arch/alpha/ev5.cc
parentc79deda8cd404565bbd277e67b3533b6c13fac74 (diff)
downloadgem5-27960f6d858e92572d37604e92747d0b45591665.tar.xz
fix rpcc
arch/alpha/ev5.cc: actually implement the cycle count register arch/alpha/isa_desc: the rpcc instruction really just reads the cycle count register --HG-- extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1
Diffstat (limited to 'arch/alpha/ev5.cc')
-rw-r--r--arch/alpha/ev5.cc5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 96c51a2aa..551cbdabf 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -237,6 +237,11 @@ ExecContext::readIpr(int idx, Fault &fault)
retval = ipr[idx];
break;
+ case AlphaISA::IPR_CC:
+ retval |= ipr[idx] & ULL(0xffffffff00000000);
+ retval |= curTick & ULL(0x00000000ffffffff);
+ break;
+
case AlphaISA::IPR_VA:
// SFX: unlocks interrupt status registers
retval = ipr[idx];