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author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-24 18:45:28 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-24 18:45:28 -0500 |
commit | e66f521d5be35683fc9460b2c4d6b7fb35fad940 (patch) | |
tree | e290f340b7c1d5d999ee61ca3a4db008ecdc7517 /arch/alpha/ev5.cc | |
parent | 802fd04f640b34d713f7ef75142e51d3d82559b9 (diff) | |
parent | 7a37037358ae5800d0f6a40130929669d836fe70 (diff) | |
download | gem5-e66f521d5be35683fc9460b2c4d6b7fb35fad940.tar.xz |
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
SConscript:
arch/alpha/ev5.cc:
dev/alpha_console.cc:
Hand merged
--HG--
extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
Diffstat (limited to 'arch/alpha/ev5.cc')
-rw-r--r-- | arch/alpha/ev5.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 3f1c17adc..34b328a39 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -70,12 +70,15 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow) // Machine dependent functions // void -AlphaISA::initCPU(RegFile *regs) +AlphaISA::initCPU(RegFile *regs, int cpuId) { - initIPRs(regs); + initIPRs(regs, cpuId); // CPU comes up with PAL regs enabled swap_palshadow(regs, true); + regs->intRegFile[16] = cpuId; + regs->intRegFile[0] = cpuId; + regs->pc = regs->ipr[IPR_PAL_BASE] + (new ResetFault)->vect(); regs->npc = regs->pc + sizeof(MachInst); } @@ -106,13 +109,14 @@ const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { // // void -AlphaISA::initIPRs(RegFile *regs) +AlphaISA::initIPRs(RegFile *regs, int cpuId) { uint64_t *ipr = regs->ipr; bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); ipr[IPR_PAL_BASE] = PalBase; ipr[IPR_MCSR] = 0x6; + ipr[IPR_PALtemp16] = cpuId; } |