Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.

SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d

1 files changed, 36 insertions, 45 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 125affd03..9d14be4d5 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -76,7 +76,7 @@ AlphaISA::initCPU(RegFile *regs)
     // CPU comes up with PAL regs enabled
     swap_palshadow(regs, true);
 
-    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
+    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
     regs->npc = regs->pc + sizeof(MachInst);
 }
 
@@ -84,25 +84,16 @@ AlphaISA::initCPU(RegFile *regs)
 //
 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
 //
-Addr
-AlphaISA::fault_addr[Num_Faults] = {
-    0x0000,	/* No_Fault */
-    0x0001,	/* Reset_Fault */
-    0x0401,	/* Machine_Check_Fault */
-    0x0501,	/* Arithmetic_Fault */
-    0x0101,	/* Interrupt_Fault */
-    0x0201,	/* Ndtb_Miss_Fault */
-    0x0281,	/* Pdtb_Miss_Fault */
-    0x0301,	/* Alignment_Fault */
-    0x0381,	/* DTB_Fault_Fault */
-    0x0381,	/* DTB_Acv_Fault */
-    0x0181,	/* ITB_Miss_Fault */
-    0x0181,	/* ITB_Fault_Fault */
-    0x0081,	/* ITB_Acv_Fault */
-    0x0481,	/* Unimplemented_Opcode_Fault */
-    0x0581,	/* Fen_Fault */
-    0x2001,	/* Pal_Fault */
-    0x0501,	/* Integer_Overflow_Fault: maps to Arithmetic_Fault */
+const Addr
+AlphaISA::fault_addr(Fault * fault)
+{
+        //Check for the system wide faults
+        if(fault == NoFault) return 0x0000;
+        else if(fault == MachineCheckFault) return 0x0401;
+        else if(fault == AlignmentFault) return 0x0301;
+        else if(fault == FakeMemFault) return 0x0000;
+        //Deal with the alpha specific faults
+        return ((AlphaFault*)fault)->vect;
 };
 
 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
@@ -168,7 +159,7 @@ AlphaISA::processInterrupts(CPU *cpu)
     if (ipl && ipl > ipr[IPR_IPLR]) {
         ipr[IPR_ISR] = summary;
         ipr[IPR_INTID] = ipl;
-        cpu->trap(Interrupt_Fault);
+        cpu->trap(InterruptFault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                 ipr[IPR_IPLR], ipl, summary);
     }
@@ -187,25 +178,25 @@ AlphaISA::zeroRegisters(CPU *cpu)
 }
 
 void
-ExecContext::ev5_trap(Fault fault)
+ExecContext::ev5_trap(Fault * fault)
 {
-    DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
-    cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
+    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault ? fault->name : "none", regs.pc);
+    cpu->recordEvent(csprintf("Fault %s", fault ? fault->name : "none"));
 
     assert(!misspeculating());
     kernelStats->fault(fault);
 
-    if (fault == Arithmetic_Fault)
+    if (fault == ArithmeticFault)
         panic("Arithmetic traps are unimplemented!");
 
     AlphaISA::InternalProcReg *ipr = regs.ipr;
 
     // exception restart address
-    if (fault != Interrupt_Fault || !inPalMode())
+    if (fault != InterruptFault || !inPalMode())
         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 
-    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
-        fault == Interrupt_Fault && !inPalMode() */) {
+    if (fault == PalFault || fault == ArithmeticFault /* ||
+        fault == InterruptFault && !inPalMode() */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
     }
@@ -213,22 +204,22 @@ ExecContext::ev5_trap(Fault fault)
     if (!inPalMode())
         AlphaISA::swap_palshadow(&regs, true);
 
-    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
+    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
     regs.npc = regs.pc + sizeof(MachInst);
 }
 
 
 void
-AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
+AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
 {
     InternalProcReg *ipr = regs->ipr;
-    bool use_pc = (fault == No_Fault);
+    bool use_pc = (fault == NoFault);
 
-    if (fault == Arithmetic_Fault)
+    if (fault == ArithmeticFault)
         panic("arithmetic faults NYI...");
 
     // compute exception restart address
-    if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
+    if (use_pc || fault == PalFault || fault == ArithmeticFault) {
         // traps...  skip faulting instruction
         ipr[IPR_EXC_ADDR] = regs->pc + 4;
     } else {
@@ -238,20 +229,20 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 
     // jump to expection address (PAL PC bit set here as well...)
     if (!use_pc)
-        regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
+        regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
     else
         regs->npc = ipr[IPR_PAL_BASE] + pc;
 
     // that's it! (orders of magnitude less painful than x86)
 }
 
-Fault
+Fault *
 ExecContext::hwrei()
 {
     uint64_t *ipr = regs.ipr;
 
     if (!inPalMode())
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
 
     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -265,11 +256,11 @@ ExecContext::hwrei()
     }
 
     // FIXME: XXX check for interrupts? XXX
-    return No_Fault;
+    return NoFault;
 }
 
 uint64_t
-ExecContext::readIpr(int idx, Fault &fault)
+ExecContext::readIpr(int idx, Fault * &fault)
 {
     uint64_t *ipr = regs.ipr;
     uint64_t retval = 0;	// return value, default 0
@@ -363,12 +354,12 @@ ExecContext::readIpr(int idx, Fault &fault)
       case AlphaISA::IPR_DTB_IAP:
       case AlphaISA::IPR_ITB_IA:
       case AlphaISA::IPR_ITB_IAP:
-        fault = Unimplemented_Opcode_Fault;
+        fault = UnimplementedOpcodeFault;
         break;
 
       default:
         // invalid IPR
-        fault = Unimplemented_Opcode_Fault;
+        fault = UnimplementedOpcodeFault;
         break;
     }
 
@@ -380,14 +371,14 @@ ExecContext::readIpr(int idx, Fault &fault)
 int break_ipl = -1;
 #endif
 
-Fault
+Fault *
 ExecContext::setIpr(int idx, uint64_t val)
 {
     uint64_t *ipr = regs.ipr;
     uint64_t old;
 
     if (misspeculating())
-        return No_Fault;
+        return NoFault;
 
     switch (idx) {
       case AlphaISA::IPR_PALtemp0:
@@ -533,7 +524,7 @@ ExecContext::setIpr(int idx, uint64_t val)
       case AlphaISA::IPR_ITB_PTE_TEMP:
       case AlphaISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
 
       case AlphaISA::IPR_HWINT_CLR:
       case AlphaISA::IPR_SL_XMIT:
@@ -635,11 +626,11 @@ ExecContext::setIpr(int idx, uint64_t val)
 
       default:
         // invalid IPR
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 
     // no error...
-    return No_Fault;
+    return NoFault;
 }
 
 /**