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| author | Kevin Lim <ktlim@umich.edu> | 2004-05-28 14:42:59 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2004-05-28 14:42:59 -0400 |
| commit | 6964ecd1cf14f294a300e91bc5b65042d03952d4 (patch) | |
| tree | 294cda7746b1fc636a00c2a377d41a95e67a62a3 /arch/alpha/ev5.cc | |
| parent | 67b5f6afc10a87a5942d24ad503f3e6b9358580c (diff) | |
| download | gem5-6964ecd1cf14f294a300e91bc5b65042d03952d4.tar.xz | |
Updated FastCPU model with all the recent changes.
arch/alpha/ev5.cc:
Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future.
arch/isa_parser.py:
Added in FastCPU model.
--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
Diffstat (limited to 'arch/alpha/ev5.cc')
| -rw-r--r-- | arch/alpha/ev5.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index e88f6d0a3..ecf66f4f5 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -153,8 +153,10 @@ void AlphaISA::zeroRegisters(XC *xc) { // Insure ISA semantics - xc->setIntReg(ZeroReg, 0); - xc->setFloatRegDouble(ZeroReg, 0.0); + // (no longer very clean due to the change in setIntReg() in the + // cpu model. Consider changing later.) + xc->xc->setIntReg(ZeroReg, 0); + xc->xc->setFloatRegDouble(ZeroReg, 0.0); } void |