Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.

They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76

1 files changed, 49 insertions, 50 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 14b87b16f..f292c6c46 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -72,14 +72,14 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
 void
 AlphaISA::initCPU(RegFile *regs, int cpuId)
 {
-    initIPRs(regs, cpuId);
+    initIPRs(&regs->miscRegs, cpuId);
     // CPU comes up with PAL regs enabled
     swap_palshadow(regs, true);
 
     regs->intRegFile[16] = cpuId;
     regs->intRegFile[0] = cpuId;
 
-    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
+    regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + fault_addr(ResetFault);
     regs->npc = regs->pc + sizeof(MachInst);
 }
 
@@ -109,14 +109,13 @@ const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
 //
 //
 void
-AlphaISA::initIPRs(RegFile *regs, int cpuId)
+AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId)
 {
-    uint64_t *ipr = regs->ipr;
+    miscRegs->clearIprs();
 
-    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
-    ipr[IPR_PAL_BASE] = PalBase;
-    ipr[IPR_MCSR] = 0x6;
-    ipr[IPR_PALtemp16] = cpuId;
+    miscRegs->setReg(IPR_PAL_BASE, PalBase);
+    miscRegs->setReg(IPR_MCSR, 0x6);
+    miscRegs->setReg(IPR_PALtemp16, cpuId);
 }
 
 
@@ -128,17 +127,16 @@ AlphaISA::processInterrupts(CPU *cpu)
     //Handle the interrupts
     int ipl = 0;
     int summary = 0;
-    IntReg *ipr = cpu->getIprPtr();
 
     cpu->checkInterrupts = false;
 
-    if (ipr[IPR_ASTRR])
+    if (cpu->readMiscReg(IPR_ASTRR))
         panic("asynchronous traps not implemented\n");
 
-    if (ipr[IPR_SIRR]) {
+    if (cpu->readMiscReg(IPR_SIRR)) {
         for (int i = INTLEVEL_SOFTWARE_MIN;
              i < INTLEVEL_SOFTWARE_MAX; i++) {
-            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
                 // See table 4-19 of the 21164 hardware reference
                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                 summary |= (ULL(1) << i);
@@ -159,12 +157,12 @@ AlphaISA::processInterrupts(CPU *cpu)
         }
     }
 
-    if (ipl && ipl > ipr[IPR_IPLR]) {
-        ipr[IPR_ISR] = summary;
-        ipr[IPR_INTID] = ipl;
+    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
+        cpu->setMiscReg(IPR_ISR, summary);
+        cpu->setMiscReg(IPR_INTID, ipl);
         cpu->trap(InterruptFault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                ipr[IPR_IPLR], ipl, summary);
+                cpu->readMiscReg(IPR_IPLR), ipl, summary);
     }
 
 }
@@ -192,22 +190,21 @@ ExecContext::ev5_trap(Fault fault)
     if (fault == ArithmeticFault)
         panic("Arithmetic traps are unimplemented!");
 
-    AlphaISA::InternalProcReg *ipr = regs.ipr;
-
     // exception restart address
     if (fault != InterruptFault || !inPalMode())
-        ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
+        setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
 
     if (fault == PalFault || fault == ArithmeticFault /* ||
         fault == InterruptFault && !inPalMode() */) {
         // traps...  skip faulting instruction
-        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
+        setMiscReg(AlphaISA::IPR_EXC_ADDR,
+                   readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
     }
 
     if (!inPalMode())
         AlphaISA::swap_palshadow(&regs, true);
 
-    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
+    regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) + AlphaISA::fault_addr(fault);
     regs.npc = regs.pc + sizeof(MachInst);
 }
 
@@ -215,7 +212,6 @@ ExecContext::ev5_trap(Fault fault)
 void
 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 {
-    InternalProcReg *ipr = regs->ipr;
     bool use_pc = (fault == NoFault);
 
     if (fault == ArithmeticFault)
@@ -224,17 +220,18 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
     // compute exception restart address
     if (use_pc || fault == PalFault || fault == ArithmeticFault) {
         // traps...  skip faulting instruction
-        ipr[IPR_EXC_ADDR] = regs->pc + 4;
+        regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
     } else {
         // fault, post fault at excepting instruction
-        ipr[IPR_EXC_ADDR] = regs->pc;
+        regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
     }
 
     // jump to expection address (PAL PC bit set here as well...)
     if (!use_pc)
-        regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
+        regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
+            fault_addr(fault);
     else
-        regs->npc = ipr[IPR_PAL_BASE] + pc;
+        regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
 
     // that's it! (orders of magnitude less painful than x86)
 }
@@ -242,17 +239,15 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 Fault
 ExecContext::hwrei()
 {
-    uint64_t *ipr = regs.ipr;
-
     if (!inPalMode())
         return UnimplementedOpcodeFault;
 
-    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+    setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
 
     if (!misspeculating()) {
         kernelStats->hwrei();
 
-        if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
+        if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
             AlphaISA::swap_palshadow(&regs, false);
 
         cpu->checkInterrupts = true;
@@ -262,10 +257,15 @@ ExecContext::hwrei()
     return NoFault;
 }
 
-uint64_t
-ExecContext::readIpr(int idx, Fault &fault)
+void
+AlphaISA::MiscRegFile::clearIprs()
+{
+    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
+}
+
+AlphaISA::MiscReg
+AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
 {
-    uint64_t *ipr = regs.ipr;
     uint64_t retval = 0;	// return value, default 0
 
     switch (idx) {
@@ -318,7 +318,7 @@ ExecContext::readIpr(int idx, Fault &fault)
 
       case AlphaISA::IPR_CC:
         retval |= ipr[idx] & ULL(0xffffffff00000000);
-        retval |= cpu->curCycle()  & ULL(0x00000000ffffffff);
+        retval |= xc->cpu->curCycle()  & ULL(0x00000000ffffffff);
         break;
 
       case AlphaISA::IPR_VA:
@@ -335,7 +335,7 @@ ExecContext::readIpr(int idx, Fault &fault)
 
       case AlphaISA::IPR_DTB_PTE:
         {
-            AlphaISA::PTE &pte = dtb->index(!misspeculating());
+            AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating());
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -375,12 +375,11 @@ int break_ipl = -1;
 #endif
 
 Fault
-ExecContext::setIpr(int idx, uint64_t val)
+AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
 {
-    uint64_t *ipr = regs.ipr;
     uint64_t old;
 
-    if (misspeculating())
+    if (xc->misspeculating())
         return NoFault;
 
     switch (idx) {
@@ -433,7 +432,7 @@ ExecContext::setIpr(int idx, uint64_t val)
         // write entire quad w/ no side-effect
         old = ipr[idx];
         ipr[idx] = val;
-        kernelStats->context(old, val);
+        xc->kernelStats->context(old, val);
         break;
 
       case AlphaISA::IPR_DTB_PTE:
@@ -460,14 +459,14 @@ ExecContext::setIpr(int idx, uint64_t val)
 
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
-        kernelStats->swpipl(ipr[idx]);
+        xc->kernelStats->swpipl(ipr[idx]);
         break;
 
       case AlphaISA::IPR_DTB_CM:
         if (val & 0x18)
-            kernelStats->mode(Kernel::user);
+            xc->kernelStats->mode(Kernel::user);
         else
-            kernelStats->mode(Kernel::kernel);
+            xc->kernelStats->mode(Kernel::kernel);
 
       case AlphaISA::IPR_ICM:
         // only write two mode bits - processor mode
@@ -541,21 +540,21 @@ ExecContext::setIpr(int idx, uint64_t val)
         // really a control write
         ipr[idx] = 0;
 
-        dtb->flushAll();
+        xc->dtb->flushAll();
         break;
 
       case AlphaISA::IPR_DTB_IAP:
         // really a control write
         ipr[idx] = 0;
 
-        dtb->flushProcesses();
+        xc->dtb->flushProcesses();
         break;
 
       case AlphaISA::IPR_DTB_IS:
         // really a control write
         ipr[idx] = val;
 
-        dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+        xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
         break;
 
       case AlphaISA::IPR_DTB_TAG: {
@@ -578,7 +577,7 @@ ExecContext::setIpr(int idx, uint64_t val)
           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          dtb->insert(val, pte);
+          xc->dtb->insert(val, pte);
       }
         break;
 
@@ -602,7 +601,7 @@ ExecContext::setIpr(int idx, uint64_t val)
           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
+          xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
       }
         break;
 
@@ -610,21 +609,21 @@ ExecContext::setIpr(int idx, uint64_t val)
         // really a control write
         ipr[idx] = 0;
 
-        itb->flushAll();
+        xc->itb->flushAll();
         break;
 
       case AlphaISA::IPR_ITB_IAP:
         // really a control write
         ipr[idx] = 0;
 
-        itb->flushProcesses();
+        xc->itb->flushProcesses();
         break;
 
       case AlphaISA::IPR_ITB_IS:
         // really a control write
         ipr[idx] = val;
 
-        itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
+        xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
         break;
 
       default: