Cleaned up some of the Fault system.

arch/alpha/ev5.cc:
    Commented out the intr_post function since it's not used. If this really -is- needed, it should be moved into the fault class.
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Moved the fault invocation code into the fault class fully, and got rid of the need for isA.
cpu/exec_context.cc:
cpu/exec_context.hh:
    Removed the trap function from the ExecContext. The faults will execute normally in full system mode, but always panic in syscall emulation mode.
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
    Changed the execution context executing a fault to a fault executing on the execution context.
sim/faults.cc:
    If not in full system mode, trying to invoke a fault causes a panic.
sim/faults.hh:
    Removed the isA function.

--HG--
extra : convert_revision : 894dc8f0755c8efc4b7ef5a09fb2cf7373042395

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index ac0e7e67e..c6da628be 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -166,7 +166,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
 void
 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 {
-    bool use_pc = (fault == NoFault);
+/*    bool use_pc = (fault == NoFault);
 
     if (fault->isA<ArithmeticFault>())
         panic("arithmetic faults NYI...");
@@ -186,7 +186,7 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
             (dynamic_cast<AlphaFault *>(fault.get()))->vect();
     else
         regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
-
+*/
     // that's it! (orders of magnitude less painful than x86)
 }