fix rpcc

arch/alpha/ev5.cc:
    actually implement the cycle count register
arch/alpha/isa_desc:
    the rpcc instruction really just reads the cycle count
    register

--HG--
extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1

1 files changed, 5 insertions, 0 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 96c51a2aa..551cbdabf 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -237,6 +237,11 @@ ExecContext::readIpr(int idx, Fault &fault)
         retval = ipr[idx];
         break;
 
+      case AlphaISA::IPR_CC:
+        retval |= ipr[idx] & ULL(0xffffffff00000000);
+        retval |= curTick  & ULL(0x00000000ffffffff);
+        break;
+
       case AlphaISA::IPR_VA:
         // SFX: unlocks interrupt status registers
         retval = ipr[idx];