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author | Ali Saidi <saidi@eecs.umich.edu> | 2004-06-22 17:20:34 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-06-22 17:20:34 -0400 |
commit | 556b2a9098930698b39f296c8d13831f2b91311b (patch) | |
tree | 014cb2e144436258518bfb77de9a8d2150a1d8ea /arch/alpha/ev5.cc | |
parent | e05dbb5116b9ff0984ea8214ec921d2db3aed41d (diff) | |
parent | f37eb6f5c7184acb6df46d14d9e48a22c8ac8134 (diff) | |
download | gem5-556b2a9098930698b39f296c8d13831f2b91311b.tar.xz |
Merge zizzer:/bk/linux into zeep.eecs.umich.edu:/z/saidi/work/m5-linux
--HG--
extra : convert_revision : 448f6e7851c14dd2c9f6148122da873a19c20772
Diffstat (limited to 'arch/alpha/ev5.cc')
-rw-r--r-- | arch/alpha/ev5.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index ecf66f4f5..d2ca71b3a 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -162,6 +162,7 @@ AlphaISA::zeroRegisters(XC *xc) void ExecContext::ev5_trap(Fault fault) { + DPRINTF(Fault, "Fault %s\n", FaultName(fault)); Stats::recordEvent(csprintf("Fault %s", FaultName(fault))); assert(!misspeculating()); @@ -302,11 +303,7 @@ ExecContext::readIpr(int idx, Fault &fault) break; case AlphaISA::IPR_VA: - // SFX: unlocks interrupt status registers retval = ipr[idx]; - - if (!misspeculating()) - regs.intrlock = false; break; case AlphaISA::IPR_VA_FORM: |