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| author | Andrew Schultz <alschult@umich.edu> | 2004-02-18 21:38:55 -0500 |
|---|---|---|
| committer | Andrew Schultz <alschult@umich.edu> | 2004-02-18 21:38:55 -0500 |
| commit | 12747d3084339d9db52d32e75215242b38474887 (patch) | |
| tree | a053a1f60a14174e873c0507ef5d84daf74a9d9f /arch/alpha/ev5.cc | |
| parent | 2d5ef88e1c782376746c6025843cf2a10ad741a9 (diff) | |
| download | gem5-12747d3084339d9db52d32e75215242b38474887.tar.xz | |
Change the physical memory logic, and also add misspeculation fix to
tlb index calls that are called from ExecContext::readIpr
arch/alpha/ev5.cc:
Fix misspeculation bugs for misspeculated IPR accesses
--HG--
extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7
Diffstat (limited to 'arch/alpha/ev5.cc')
| -rw-r--r-- | arch/alpha/ev5.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 8494ee9f6..aaa81a58d 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -240,7 +240,9 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_VA: // SFX: unlocks interrupt status registers retval = ipr[idx]; - regs.intrlock = false; + + if (!misspeculating()) + regs.intrlock = false; break; case AlphaISA::IPR_VA_FORM: @@ -253,7 +255,7 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_DTB_PTE: { - AlphaISA::PTE &pte = dtb->index(); + AlphaISA::PTE &pte = dtb->index(!misspeculating()); retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; |