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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-02-24 08:52:38 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-02-24 08:52:38 -0500 |
| commit | 7a37037358ae5800d0f6a40130929669d836fe70 (patch) | |
| tree | 31b2c9f9033585b7c163319c8abcb80aa7bd26f4 /arch/alpha/ev5.cc | |
| parent | f6cac25dcfbeed77642026deb81979f651104efe (diff) | |
| parent | 51647e7bec8e8607fc5713b4ace2c24ce8a7455a (diff) | |
| download | gem5-7a37037358ae5800d0f6a40130929669d836fe70.tar.xz | |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/multiarch
arch/isa_parser.py:
SCCS merged
--HG--
extra : convert_revision : 080cca7616b37db3bf18976b63b3dbcb47d8b918
Diffstat (limited to 'arch/alpha/ev5.cc')
| -rw-r--r-- | arch/alpha/ev5.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 4777907e0..14b87b16f 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -70,12 +70,15 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow) // Machine dependent functions // void -AlphaISA::initCPU(RegFile *regs) +AlphaISA::initCPU(RegFile *regs, int cpuId) { - initIPRs(regs); + initIPRs(regs, cpuId); // CPU comes up with PAL regs enabled swap_palshadow(regs, true); + regs->intRegFile[16] = cpuId; + regs->intRegFile[0] = cpuId; + regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault); regs->npc = regs->pc + sizeof(MachInst); } @@ -106,13 +109,14 @@ const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { // // void -AlphaISA::initIPRs(RegFile *regs) +AlphaISA::initIPRs(RegFile *regs, int cpuId) { uint64_t *ipr = regs->ipr; bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); ipr[IPR_PAL_BASE] = PalBase; ipr[IPR_MCSR] = 0x6; + ipr[IPR_PALtemp16] = cpuId; } |