Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.

The shadow registers are folded into the normal integer registers to ease renaming indexing.

Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode.

arch/alpha/ev5.cc:
    Changes to automatically map the shadow registers if the instruction is in PAL mode.
arch/alpha/isa/branch.isa:
arch/alpha/isa/decoder.isa:
arch/alpha/isa/fp.isa:
arch/alpha/isa/int.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
arch/alpha/isa/unimp.isa:
    Changes for automatically using the shadow registers.  Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
arch/alpha/isa/main.isa:
    Changes for automatically using the shadow registers.  Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.

    The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode.  If it is, then it refers to the reg_redir table to determine the true index of the register it is using.

    Also include the opcdec instruction definition.
arch/alpha/isa_traits.hh:
    Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not.

    Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers).

    Change the dependence tags to reflect the integer registers include the 8 shadow registers.

    Define function to make an ExtMachInst.  Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU.
arch/isa_parser.py:
    Have static insts decode on the ExtMachInst.
base/remote_gdb.cc:
    Support the automatic remapping of shadow registers.  Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices.
cpu/o3/regfile.hh:
    Comment out the pal registers; they are now a part of the integer registers.
cpu/simple/cpu.cc:
    Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin.
cpu/static_inst.hh:
    Change from MachInst to ExtMachInst to support shadow register renaming.

--HG--
extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5

1 files changed, 9 insertions, 9 deletions

diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 61d6ea8fa..3c8b4f755 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -42,7 +42,7 @@ output header {{
         const StaticInstPtr memAccPtr;
 
         /// Constructor
-        Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
+        Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : AlphaStaticInst(mnem, _machInst, __opClass),
@@ -70,7 +70,7 @@ output header {{
         int32_t disp;
 
         /// Constructor.
-        MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
+        MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                      StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                      StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
@@ -89,7 +89,7 @@ output header {{
     {
       protected:
         /// Constructor
-        MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
+        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                      StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                      StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
@@ -141,7 +141,7 @@ def template LoadStoreDeclare {{
         {
           public:
             /// Constructor
-            EAComp(MachInst machInst);
+            EAComp(ExtMachInst machInst);
 
             %(BasicExecDeclare)s
         };
@@ -153,7 +153,7 @@ def template LoadStoreDeclare {{
         {
           public:
             /// Constructor
-            MemAcc(MachInst machInst);
+            MemAcc(ExtMachInst machInst);
 
             %(BasicExecDeclare)s
         };
@@ -161,7 +161,7 @@ def template LoadStoreDeclare {{
       public:
 
         /// Constructor.
-        %(class_name)s(MachInst machInst);
+        %(class_name)s(ExtMachInst machInst);
 
         %(BasicExecDeclare)s
 
@@ -186,19 +186,19 @@ def template LoadStoreConstructor {{
     /** TODO: change op_class to AddrGenOp or something (requires
      * creating new member of OpClass enum in op_class.hh, updating
      * config files, etc.). */
-    inline %(class_name)s::EAComp::EAComp(MachInst machInst)
+    inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
         : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
     {
         %(ea_constructor)s;
     }
 
-    inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
+    inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
         : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
     {
         %(memacc_constructor)s;
     }
 
-    inline %(class_name)s::%(class_name)s(MachInst machInst)
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                           new EAComp(machInst), new MemAcc(machInst))
     {