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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-02-12 00:31:19 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-02-12 00:31:19 -0500 |
| commit | 79613686f0f6a8725e88e935a7c9ff4ede4cfc2b (patch) | |
| tree | baa659b44e5f561a1686b887b4f3825ef8e1d326 /arch/alpha/isa | |
| parent | 8f2e096275386cbd6744c4bd65190dba1c5b89b4 (diff) | |
| download | gem5-79613686f0f6a8725e88e935a7c9ff4ede4cfc2b.tar.xz | |
Polishing of isa_parser.py internal operand handling, resulting in
minor change to syntax of 'def operands' in ISA descriptions.
arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
Change 'def operands' statement to work with new
isa_parser changes.
arch/isa_parser.py:
Merge OperandTraits and OperandDescriptor objects into a
unified hierarchy of Operand objects.
Required a change in the syntax of the 'def operands'
statement in the ISA description.
--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
Diffstat (limited to 'arch/alpha/isa')
| -rw-r--r-- | arch/alpha/isa/main.isa | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa index fa2f71a29..c082df8c8 100644 --- a/arch/alpha/isa/main.isa +++ b/arch/alpha/isa/main.isa @@ -148,20 +148,19 @@ def operands {{ # Int regs default to unsigned, but code should not count on this. # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. - 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1), - 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2), - 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3), - 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1), - 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2), - 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3), - 'Mem': MemOperandTraits('uq', None, - ('IsMemRef', 'IsLoad', 'IsStore'), 4), - 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4), - 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1), - 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1), + 'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1), + 'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2), + 'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3), + 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), + 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), + 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), + 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), + 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), + 'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), + 'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1), # The next two are hacks for non-full-system call-pal emulation - 'R0': IntRegOperandTraits('uq', '0', None, 1), - 'R16': IntRegOperandTraits('uq', '16', None, 1) + 'R0': ('IntReg', 'uq', '0', None, 1), + 'R16': ('IntReg', 'uq', '16', None, 1) }}; //////////////////////////////////////////////////////////////////// |