Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5

into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 427b5c957f91e66271444acebc01e1a861790363

4 files changed, 77 insertions, 67 deletions

diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index c21465928..29124f191 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -34,47 +34,47 @@ decode OPCODE default Unknown::unknown() {
     }
 
     format LoadOrNop {
-        0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
-        0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
-        0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
-        0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
-        0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
-        0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
+        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
+        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
+        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
+        0x23: ldt({{ Fa = Mem.df; }});
+        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
+        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
         0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
                                       {{ fault = xc->copySrcTranslate(EA); }},
-                                      IsMemRef, IsLoad, IsCopy);
+                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
     }
 
     format LoadOrPrefetch {
-        0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
-        0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
+        0x28: ldl({{ Ra.sl = Mem.sl; }});
+        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
         // IsFloating flag on lds gets the prefetch to disassemble
         // using f31 instead of r31... funcitonally it's unnecessary
-        0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
-                  PF_EXCLUSIVE, IsFloating);
+        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
+                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
     }
 
     format Store {
-        0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
-        0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
-        0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
-        0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
-        0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
-        0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
-        0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
+        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
+        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
+        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
+        0x2d: stq({{ Mem.uq = Ra.uq; }});
+        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
+        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
+        0x27: stt({{ Mem.df = Fa; }});
         0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
                                        {{ fault = xc->copy(EA); }},
-                                       IsMemRef, IsStore, IsCopy);
+                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
     }
 
     format StoreCond {
-        0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
+        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
                     {{
                         uint64_t tmp = write_result;
                         // see stq_c
                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
-                    }}, LOCKED);
-        0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
+                    }}, mem_flags = LOCKED);
+        0x2f: stq_c({{ Mem.uq = Ra; }},
                     {{
                         uint64_t tmp = write_result;
                         // If the write operation returns 0 or 1, then
@@ -85,7 +85,7 @@ decode OPCODE default Unknown::unknown() {
                         // mailbox access, and we don't update the
                         // result register at all.
                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
-                    }}, LOCKED);
+                    }}, mem_flags = LOCKED);
     }
 
     format IntegerOperate {
@@ -607,8 +607,9 @@ decode OPCODE default Unknown::unknown() {
         format MiscPrefetch {
             0xf800: wh64({{ EA = Rb & ~ULL(63); }},
                          {{ xc->writeHint(EA, 64, memAccessFlags); }},
-                         IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
-                         NO_FAULT);
+                         mem_flags = NO_FAULT,
+                         inst_flags = [IsMemRef, IsDataPrefetch,
+                                       IsStore, MemWriteOp]);
         }
 
         format BasicOperate {
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index fa2f71a29..c082df8c8 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -148,20 +148,19 @@ def operands {{
     # Int regs default to unsigned, but code should not count on this.
     # For clarity, descriptions that depend on unsigned behavior should
     # explicitly specify '.uq'.
-    'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
-    'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
-    'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
-    'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
-    'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
-    'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
-    'Mem': MemOperandTraits('uq', None,
-                            ('IsMemRef', 'IsLoad', 'IsStore'), 4),
-    'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
-    'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
-    'FPCR':  ControlRegOperandTraits('uq', 'Fpcr', None, 1),
+    'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1),
+    'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2),
+    'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3),
+    'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
+    'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
+    'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
+    'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
+    'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
+    'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
+    'FPCR':  (' ControlReg', 'uq', 'Fpcr', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
-    'R0':  IntRegOperandTraits('uq', '0', None, 1),
-    'R16': IntRegOperandTraits('uq', '16', None, 1)
+    'R0':  ('IntReg', 'uq', '0', None, 1),
+    'R16': ('IntReg', 'uq', '16', None, 1)
 }};
 
 ////////////////////////////////////////////////////////////////////
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 0d9d59cee..45afd378c 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -407,16 +407,12 @@ def template LoadPrefetchCheckDecode {{
 
 
 let {{
-def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
-                  base_class = 'MemoryDisp32', flags = [],
+def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                  postacc_code = '', base_class = 'MemoryDisp32',
                   decode_template = BasicDecode, exec_template_base = ''):
-    # Segregate flags into instruction flags (handled by InstObjParams)
-    # and memory access flags (handled here).
-
-    # Would be nice to autogenerate this list, but oh well.
-    valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
-    mem_flags =  [f for f in flags if f in valid_mem_flags]
-    inst_flags = [f for f in flags if f not in valid_mem_flags]
+    # Make sure flags are in lists (convert to lists if not).
+    mem_flags = makeList(mem_flags)
+    inst_flags = makeList(inst_flags)
 
     # add hook to get effective addresses into execution trace output.
     ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
@@ -469,31 +465,39 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
 }};
 
 
-def format LoadOrNop(ea_code, memacc_code, *flags) {{
+def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
+                     mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                       decode_template = LoadNopCheckDecode,
                       exec_template_base = 'Load')
 }};
 
 
 // Note that the flags passed in apply only to the prefetch version
-def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
+def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
+                          mem_flags = [], pf_flags = [], inst_flags = []) {{
     # declare the load instruction object and generate the decode block
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code,
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                       decode_template = LoadPrefetchCheckDecode,
                       exec_template_base = 'Load')
 
     # Declare the prefetch instruction object.
 
-    # convert flags from tuple to list to make them mutable
-    pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp', 'NO_FAULT']
+    # Make sure flag args are lists so we can mess with them.
+    mem_flags = makeList(mem_flags)
+    pf_flags = makeList(pf_flags)
+    inst_flags = makeList(inst_flags)
+
+    pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+    pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
+                                  'IsDataPrefetch', 'MemReadOp']
 
     (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
         LoadStoreBase(name, Name + 'Prefetch', ea_code,
                       'xc->prefetch(EA, memAccessFlags);',
-                      flags = pf_flags, exec_template_base = 'Misc')
+                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
 
     header_output += pf_header_output
     decoder_output += pf_decoder_output
@@ -501,24 +505,28 @@ def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
 }};
 
 
-def format Store(ea_code, memacc_code, *flags) {{
+def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
+                 mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                       exec_template_base = 'Store')
 }};
 
 
-def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
+def format StoreCond(memacc_code, postacc_code,
+                     ea_code = {{ EA = Rb + disp; }},
+                     mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
-                      flags = flags, exec_template_base = 'Store')
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      postacc_code, exec_template_base = 'Store')
 }};
 
 
 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
-def format MiscPrefetch(ea_code, memacc_code, *flags) {{
+def format MiscPrefetch(ea_code, memacc_code,
+                        mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                       base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
 }};
 
diff --git a/arch/alpha/isa/pal.isa b/arch/alpha/isa/pal.isa
index 552dde2d7..b68a7c19f 100644
--- a/arch/alpha/isa/pal.isa
+++ b/arch/alpha/isa/pal.isa
@@ -198,23 +198,25 @@ output decoder {{
 def format HwLoad(ea_code, memacc_code, class_ext, *flags) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
-                      flags = flags, base_class = 'HwLoadStore',
-                      exec_template_base = 'Load')
+                      mem_flags = [], inst_flags = flags,
+                      base_class = 'HwLoadStore', exec_template_base = 'Load')
 }};
 
 
 def format HwStore(ea_code, memacc_code, class_ext, *flags) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
-                      flags = flags, base_class = 'HwLoadStore',
-                      exec_template_base = 'Store')
+                      mem_flags = [], inst_flags = flags,
+                      base_class = 'HwLoadStore', exec_template_base = 'Store')
 }};
 
 
-def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
+def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext,
+                       *flags) {{
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
-                      postacc_code, flags = flags, base_class = 'HwLoadStore')
+                      postacc_code, mem_flags = [], inst_flags = flags,
+                      base_class = 'HwLoadStore')
 }};