Merge gblack@m5.eecs.umich.edu:/bk/multiarch

into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d

6 files changed, 70 insertions, 69 deletions

diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index aff8571e9..37b15416b 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() {
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
                 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc.sl = tmp;
             }});
             0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
@@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() {
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
                 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc = tmp;
             }});
             0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() {
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
                 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc.sl = tmp;
             }});
             0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
@@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() {
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
                 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc = tmp;
             }});
             0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() {
                 // checking the upper 33 bits for all 0s or all 1s.
                 uint64_t sign_bits = tmp<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc.sl = tmp<31:0>;
             }}, IntMultOp);
             0x60: mulqv({{
@@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() {
                 // the lower 64
                 if (!((hi == 0 && lo<63:> == 0) ||
                       (hi == mask(64) && lo<63:> == 1)))
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc = lo;
             }}, IntMultOp);
         }
@@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() {
 #if SS_COMPATIBLE_FP
                     0x0b: sqrts({{
                         if (Fb < 0.0)
-                            fault = Arithmetic_Fault;
+                            fault = ArithmeticFault;
                         Fc = sqrt(Fb);
                     }}, FloatSqrtOp);
 #else
                     0x0b: sqrts({{
                         if (Fb.sf < 0.0)
-                            fault = Arithmetic_Fault;
+                            fault = ArithmeticFault;
                         Fc.sf = sqrt(Fb.sf);
                     }}, FloatSqrtOp);
 #endif
                     0x2b: sqrtt({{
                         if (Fb < 0.0)
-                            fault = Arithmetic_Fault;
+                            fault = ArithmeticFault;
                         Fc = sqrt(Fb);
                     }}, FloatSqrtOp);
                 }
@@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() {
                 // checking the upper 33 bits for all 0s or all 1s.
                 uint64_t sign_bits = Fb.uq<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
             }});
 
@@ -673,7 +673,7 @@ decode OPCODE default Unknown::unknown() {
              && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
-            fault = Unimplemented_Opcode_Fault;
+            fault = UnimplementedOpcodeFault;
         }
         else {
             // check to see if simulator wants to do something special
@@ -729,7 +729,7 @@ decode OPCODE default Unknown::unknown() {
         0x19: hw_mfpr({{
             // this instruction is only valid in PAL mode
             if (!xc->inPalMode()) {
-                fault = Unimplemented_Opcode_Fault;
+                fault = UnimplementedOpcodeFault;
             }
             else {
                 Ra = xc->readIpr(ipr_index, fault);
@@ -738,7 +738,7 @@ decode OPCODE default Unknown::unknown() {
         0x1d: hw_mtpr({{
             // this instruction is only valid in PAL mode
             if (!xc->inPalMode()) {
-                fault = Unimplemented_Opcode_Fault;
+                fault = UnimplementedOpcodeFault;
             }
             else {
                 xc->setIpr(ipr_index, Ra);
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index 0abc814be..c718c5524 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -29,21 +29,21 @@
 output exec {{
     /// Check "FP enabled" machine status bit.  Called when executing any FP
     /// instruction in full-system mode.
-    /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
-    /// if not.  Non-full-system mode: always returns No_Fault.
+    /// @retval Full-system mode: NoFault if FP is enabled, FenFault
+    /// if not.  Non-full-system mode: always returns NoFault.
 #if FULL_SYSTEM
-    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
-        Fault fault = No_Fault;	// dummy... this ipr access should not fault
+        Fault * fault = NoFault;	// dummy... this ipr access should not fault
         if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
-            fault = Fen_Fault;
+            fault = FloatEnableFault;
         }
         return fault;
     }
 #else
-    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
-        return No_Fault;
+        return NoFault;
     }
 #endif
 }};
@@ -199,7 +199,7 @@ output decoder {{
 // FP instruction class execute method template.  Handles non-standard
 // rounding modes.
 def template FloatingPointExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -208,7 +208,7 @@ def template FloatingPointExecute {{
             warnedOnTrapping = true;
         }
 
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -230,7 +230,7 @@ def template FloatingPointExecute {{
         %(code)s;
 #endif
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -242,7 +242,7 @@ def template FloatingPointExecute {{
 // rounding mode control is needed.  Like BasicExecute, but includes
 // check & warning for non-standard trapping mode.
 def template FPFixedRoundingExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -251,14 +251,14 @@ def template FPFixedRoundingExecute {{
             warnedOnTrapping = true;
         }
 
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index ef4d83ce2..42fb29404 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -33,6 +33,7 @@ output header {{
 
 #include "config/ss_compatible_fp.hh"
 #include "cpu/static_inst.hh"
+#include "arch/alpha/faults.hh"
 #include "mem/mem_req.hh"  // some constructors use MemReq flags
 }};
 
@@ -253,7 +254,7 @@ output decoder {{
 
 // Declarations for execute() methods.
 def template BasicExecDeclare {{
-    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault * execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 }};
 
 // Basic instruction class declaration template.
@@ -282,17 +283,17 @@ def template BasicConstructor {{
 
 // Basic instruction class execute method template.
 def template BasicExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -377,10 +378,10 @@ output decoder {{
 }};
 
 output exec {{
-    Fault
+    Fault *
     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
     {
-        return No_Fault;
+        return NoFault;
     }
 }};
 
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 1889daefc..19785e3a8 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -208,19 +208,19 @@ def template LoadStoreConstructor {{
 
 
 def template EACompExecute {{
-    Fault
+    Fault *
     %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
             xc->setEA(EA);
         }
@@ -230,24 +230,24 @@ def template EACompExecute {{
 }};
 
 def template LoadMemAccExecute {{
-    Fault
+    Fault *
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         EA = xc->getEA();
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
             %(code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -257,23 +257,23 @@ def template LoadMemAccExecute {{
 
 
 def template LoadExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(ea_code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
             %(memacc_code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -331,12 +331,12 @@ def template LoadCompleteAcc {{
 
 
 def template StoreMemAccExecute {{
-    Fault
+    Fault *
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
@@ -344,21 +344,21 @@ def template StoreMemAccExecute {{
         %(op_rd)s;
         EA = xc->getEA();
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                               memAccessFlags, &write_result);
             if (traceData) { traceData->setData(Mem); }
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(postacc_code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -368,11 +368,11 @@ def template StoreMemAccExecute {{
 
 
 def template StoreExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
@@ -380,21 +380,21 @@ def template StoreExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(memacc_code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                               memAccessFlags, &write_result);
             if (traceData) { traceData->setData(Mem); }
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(postacc_code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -458,42 +458,42 @@ def template StoreCompleteAcc {{
 
 
 def template MiscMemAccExecute {{
-    Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                           Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         EA = xc->getEA();
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(code)s;
         }
 
-        return No_Fault;
+        return NoFault;
     }
 }};
 
 def template MiscExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(ea_code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(memacc_code)s;
         }
 
-        return No_Fault;
+        return NoFault;
     }
 }};
 
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index 767888157..ce8197708 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -105,16 +105,16 @@ output decoder {{
 }};
 
 output exec {{
-    Fault
+    Fault *
     FailUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
         panic("attempt to execute unimplemented instruction '%s' "
               "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 
-    Fault
+    Fault *
     WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
@@ -123,7 +123,7 @@ output exec {{
             warned = true;
         }
 
-        return No_Fault;
+        return NoFault;
     }
 }};
 
diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa
index 6eba5b4f9..e7f8bc8db 100644
--- a/arch/alpha/isa/unknown.isa
+++ b/arch/alpha/isa/unknown.isa
@@ -36,13 +36,13 @@ output decoder {{
 }};
 
 output exec {{
-    Fault
+    Fault *
     Unknown::execute(%(CPU_exec_context)s *xc,
                      Trace::InstRecord *traceData) const
     {
         panic("attempt to execute unknown instruction "
               "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 }};