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authorSteve Reinhardt <stever@eecs.umich.edu>2005-08-30 13:18:54 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2005-08-30 13:18:54 -0400
commitc4793184bd32e97e8932a9a0355d8a7b8a214752 (patch)
treed616bdd39c608898bd5fea6928166175e96d8d79 /arch/alpha/isa_desc
parente007aa59e3da2609de92cc6d2cfcd7acf9d4276f (diff)
downloadgem5-c4793184bd32e97e8932a9a0355d8a7b8a214752.tar.xz
Build options are set via a build_options file in the
build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. Build option flags are now always defined to 0 or 1, so checks must use '#if' rather than '#ifdef'. SConscript: MySQL detection moved to SConstruct. Add config/*.hh files (via ConfigFile builder). arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/isa_traits.hh: base/fast_alloc.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/fetch_impl.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/regfile.hh: cpu/o3/rename_impl.hh: cpu/o3/rob_impl.hh: cpu/ozone/cpu.hh: cpu/pc_event.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. arch/alpha/isa_desc: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. Revamp fenv.h support... most of the ugliness is hidden in base/fenv.hh now. base/mysql.hh: Fix typo in #ifndef guard. build/SConstruct: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. python/SConscript: Generate m5_build_env directly from scons options instead of indirectly via CPPDEFINES. python/m5/convert.py: Allow '0' and '1' for booleans. Rewrite toBool to use dict. base/fenv.hh: Revamp <fenv.h> support to make it a compile option (so we can test w/o it even if it's present) and to make isa_desc cleaner. --HG-- extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
Diffstat (limited to 'arch/alpha/isa_desc')
-rw-r--r--arch/alpha/isa_desc45
1 files changed, 17 insertions, 28 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 12b2a4822..60ffbfd54 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -45,30 +45,29 @@ output header {{
#include <iostream>
#include <iomanip>
+#include "config/ss_compatible_fp.hh"
#include "cpu/static_inst.hh"
#include "mem/mem_req.hh" // some constructors use MemReq flags
}};
output decoder {{
#include "base/cprintf.hh"
+#include "base/fenv.hh"
#include "base/loader/symtab.hh"
+#include "config/ss_compatible_fp.hh"
#include "cpu/exec_context.hh" // for Jump::branchTarget()
#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
}};
output exec {{
#include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
#include "arch/alpha/pseudo_inst.hh"
#endif
+#include "base/fenv.hh"
+#include "config/ss_compatible_fp.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
@@ -542,7 +541,7 @@ output exec {{
/// instruction in full-system mode.
/// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
/// if not. Non-full-system mode: always returns No_Fault.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = No_Fault; // dummy... this ipr access should not fault
@@ -593,9 +592,8 @@ output header {{
};
protected:
-#if defined(linux)
+ /// Map Alpha rounding mode to C99 constants from <fenv.h>.
static const int alphaToC99RoundingMode[];
-#endif
/// Map enum RoundingMode values to disassembly suffixes.
static const char *roundingModeSuffix[];
@@ -620,9 +618,7 @@ output header {{
}
}
-#if defined(linux)
int getC99RoundingMode(uint64_t fpcr_val) const;
-#endif
// This differs from the AlphaStaticInst version only in
// printing suffixes for non-default rounding & trapping modes.
@@ -650,7 +646,6 @@ def template FloatingPointDecode {{
}};
output decoder {{
-#if defined(linux)
int
AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
{
@@ -661,7 +656,6 @@ output decoder {{
return alphaToC99RoundingMode[roundingMode];
}
}
-#endif
std::string
AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -705,14 +699,12 @@ output decoder {{
return ss.str();
}
-#if defined(linux)
const int AlphaFP::alphaToC99RoundingMode[] = {
FE_TOWARDZERO, // Chopped
FE_DOWNWARD, // Minus_Infinity
FE_TONEAREST, // Normal
FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
-#endif
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
// mark invalid trapping modes, but don't fail on them, because
@@ -738,14 +730,11 @@ def format FloatingPointOperate(code, *opt_args) {{
exec_output = BasicExecute.subst(fast_iop)
gen_code_prefix = r'''
-#if defined(linux)
fesetround(getC99RoundingMode(xc->readFpcr()));
-#endif
'''
+
gen_code_suffix = r'''
-#if defined(linux)
fesetround(FE_TONEAREST);
-#endif
'''
gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
@@ -2080,7 +2069,7 @@ decode OPCODE default Unknown::unknown() {
1: decode INTIMM {
// return EV5 for FULL_SYSTEM and EV6 otherwise
1: implver({{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
Rc = 1;
#else
Rc = 2;
@@ -2090,7 +2079,7 @@ decode OPCODE default Unknown::unknown() {
}
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
// The mysterious 11.25...
0x25: WarnUnimpl::eleven25();
#endif
@@ -2310,7 +2299,7 @@ decode OPCODE default Unknown::unknown() {
0xb: decode FA {
31: decode FP_TYPEFUNC {
format FloatingPointOperate {
-#ifdef SS_COMPATIBLE_FP
+#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
fault = Arithmetic_Fault;
@@ -2350,7 +2339,7 @@ decode OPCODE default Unknown::unknown() {
// and source type.
0: decode FP_TYPEFUNC {
format FloatingPointOperate {
-#ifdef SS_COMPATIBLE_FP
+#if SS_COMPATIBLE_FP
0x00: adds({{ Fc = Fa + Fb; }});
0x01: subs({{ Fc = Fa - Fb; }});
0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
@@ -2484,7 +2473,7 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate {
0xc000: rpcc({{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
/* Rb is a fake dependency so here is a fun way to get
* the parser to understand that.
*/
@@ -2517,7 +2506,7 @@ decode OPCODE default Unknown::unknown() {
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
format BasicOperate {
0xe000: rc({{
Ra = xc->readIntrFlag();
@@ -2536,7 +2525,7 @@ decode OPCODE default Unknown::unknown() {
#endif
}
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
0x00: CallPal::call_pal({{
if (!palValid ||
(palPriv
@@ -2574,7 +2563,7 @@ decode OPCODE default Unknown::unknown() {
}
#endif
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
format HwLoadStore {
0x1b: decode HW_LDST_QUAD {
0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);