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| author | Erik Hallnor <ehallnor@umich.edu> | 2004-02-29 22:41:11 -0500 |
|---|---|---|
| committer | Erik Hallnor <ehallnor@umich.edu> | 2004-02-29 22:41:11 -0500 |
| commit | cbc42f1d71323fa94ad2b5262258c1d6b1c0b0bf (patch) | |
| tree | cc6998130c115c9219206fc23f6c523d77c75697 /arch/alpha/isa_desc | |
| parent | 7f688ba6a97808290aa5fcaaa4ff8c383d191830 (diff) | |
| download | gem5-cbc42f1d71323fa94ad2b5262258c1d6b1c0b0bf.tar.xz | |
Remove copys from isa_desc, and implement a store and forward bus bridge
arch/alpha/isa_desc:
Just to make sure, remove the new copy instructions until everything works.
--HG--
extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a
Diffstat (limited to 'arch/alpha/isa_desc')
| -rw-r--r-- | arch/alpha/isa_desc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 0cfe5b452..a7665210f 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1854,9 +1854,9 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); - 0x20: copy_load({{EA = Ra;}}, - {{memAccessObj->copySrcTranslate(EA);}}, - IsMemRef, IsLoad, IsCopy); + //0x20: copy_load({{EA = Ra;}}, + // {{memAccessObj->copySrcTranslate(EA);}}, + // IsMemRef, IsLoad, IsCopy); } format LoadOrPrefetch { @@ -1876,9 +1876,9 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); - 0x24: copy_store({{EA = Rb;}}, - {{memAccessObj->copy(EA);}}, - IsMemRef, IsStore, IsCopy); + //0x24: copy_store({{EA = Rb;}}, + // {{memAccessObj->copy(EA);}}, + // IsMemRef, IsStore, IsCopy); } format StoreCond { |