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| author | Erik Hallnor <ehallnor@umich.edu> | 2004-02-27 02:40:43 -0500 |
|---|---|---|
| committer | Erik Hallnor <ehallnor@umich.edu> | 2004-02-27 02:40:43 -0500 |
| commit | cfb6f8fd01e19dbd0b3ce5cfa28d6f78f617e954 (patch) | |
| tree | 10fabe88602c18bd99010b6df12bec0a7373e59b /arch/alpha/isa_desc | |
| parent | c3784e37ceba78eee92f46ed92aa2462e238a206 (diff) | |
| download | gem5-cfb6f8fd01e19dbd0b3ce5cfa28d6f78f617e954.tar.xz | |
Added copy instructions to the ISA. Well it didn't break anything yet...
arch/alpha/isa_desc:
Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
Add copy functions to SimpleCPU as well
--HG--
extra : convert_revision : 1fa041da582b418c47d4eefc22dabba978a50e2d
Diffstat (limited to 'arch/alpha/isa_desc')
| -rw-r--r-- | arch/alpha/isa_desc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 6a95b4e04..46fb306a4 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1854,6 +1854,9 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); + 0x20: copy_load({{EA = Ra;}}, + {{memAccessObj->copySrcTranslate(EA);}}, + IsMemRef, IsLoad, IsCopy); } format LoadOrPrefetch { @@ -1873,6 +1876,9 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); + 0x24: copy_store({{EA = Rb;}}, + {{memAccessObj->copy(EA);}}, + IsMemRef, IsStore, IsCopy); } format StoreCond { |