added m5 debug and m5 switch cpu instruction (doesn't work yet) and

a p4 memory/cpu config

arch/alpha/alpha_memory.cc:
    Added code to fault on an unaligned access
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
    Added m5debug break and m5switchcpu (the latter doesn't work)

--HG--
extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916

1 files changed, 12 insertions, 1 deletions

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index fa24e5215..d6b99a8ae 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2400,7 +2400,11 @@ decode OPCODE default Unknown::unknown() {
 	format BasicOperate {
 	    0xc000: rpcc({{
 #ifdef FULL_SYSTEM
-		Ra = xc->readIpr(AlphaISA::IPR_CC, fault);
+        /* Rb is a fake dependency so here is a fun way to get
+         * the parser to understand that.
+         */
+		Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
+        
 #else
 		Ra = curTick;
 #endif
@@ -2543,6 +2547,13 @@ decode OPCODE default Unknown::unknown() {
             0x50: m5readfile({{
 		AlphaPseudo::readfile(xc->xcBase());
 	    }}, IsNonSpeculative);
+            0x51: m5break({{
+        AlphaPseudo::debugbreak(xc->xcBase());
+        }}, IsNonSpeculative);
+            0x52: m5switchcpu({{
+        AlphaPseudo::switchcpu(xc->xcBase());
+        }}, IsNonSpeculative);
+
 	}
     }