Add support for "serializing" instructions that flush

execution pipeline (Alpha trapb & excb).

Add support for write memory barriers (mostly impacts
store buffer).

Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.

arch/alpha/isa_desc:
    Implement trapb, excb, mb, and wmb as insts with
    no execution effect (empty execute() function) but
    with flags that indicate their side effects.

    Also make sure every instruction that needs to go to
    the execute stage has a real opClass value, since we
    are now using No_OpClass to signal insts that can get
    dropped at dispatch.

    StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
    Add flags to indicate serializing insts (trapb, excb) and
    memory and write barriers.

    Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
    Make name() return value const.

--HG--
extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c

1 files changed, 26 insertions, 9 deletions

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 51bce65c2..d4636f609 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1225,7 +1225,7 @@ declare {{
 	{
 	}
 
-	Addr branchTarget(Addr branchPC)
+	Addr branchTarget(Addr branchPC) const
 	{
 	    return branchPC + 4 + disp;
 	}
@@ -1287,7 +1287,7 @@ declare {{
 	{
 	}
 
-	Addr branchTarget(ExecContext *xc)
+	Addr branchTarget(ExecContext *xc) const
 	{
 	    Addr NPC = xc->readPC() + 4;
 	    uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
@@ -2330,10 +2330,6 @@ decode OPCODE default Unknown::unknown() {
     // miscellaneous mem-format ops
     0x18: decode MEMFUNC {
 	format WarnUnimpl {
-	    0x0000: trapb();
-	    0x0400: excb();
-	    0x4000: mb();
-	    0x4400: wmb();
 	    0x8000: fetch();
 	    0xa000: fetch_m();
 	    0xe800: ecb();
@@ -2347,6 +2343,27 @@ decode OPCODE default Unknown::unknown() {
 
 	format BasicOperate {
 	    0xc000: rpcc({{ Ra = curTick; }});
+
+	    // All of the barrier instructions below do nothing in
+	    // their execute() methods (hence the empty code blocks).
+	    // All of their functionality is hard-coded in the
+	    // pipeline based on the flags IsSerializing,
+	    // IsMemBarrier, and IsWriteBarrier.  In the current
+	    // detailed CPU model, the execute() function only gets
+	    // called at fetch, so there's no way to generate pipeline
+	    // behavior at any other stage.  Once we go to an
+	    // exec-in-exec CPU model we should be able to get rid of
+	    // these flags and implement this behavior via the
+	    // execute() methods.
+
+	    // trapb is just a barrier on integer traps, where excb is
+	    // a barrier on integer and FP traps.  "EXCB is thus a
+	    // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
+	    // them the same though.
+	    0x0000: trapb({{ }}, IsSerializing, No_OpClass);
+	    0x0400: excb({{ }}, IsSerializing, No_OpClass);
+	    0x4000: mb({{ }}, IsMemBarrier);
+	    0x4400: wmb({{ }}, IsWriteBarrier);
 	}
 
 #ifdef FULL_SYSTEM
@@ -2356,13 +2373,13 @@ decode OPCODE default Unknown::unknown() {
 		if (!xc->misspeculating()) {
 		    xc->regs.intrflag = 0;
 		}
-	    }}, No_OpClass);
+	    }});
 	    0xf000: rs({{
 		Ra = xc->regs.intrflag;
 		if (!xc->misspeculating()) {
 		    xc->regs.intrflag = 1;
 		}
-	    }}, No_OpClass);
+	    }});
 	}
 #else
 	format FailUnimpl {
@@ -2476,7 +2493,7 @@ decode OPCODE default Unknown::unknown() {
 		if (!xc->misspeculating())
 		    AlphaPseudo::m5exit(xc);
 	    }}, No_OpClass);
-            0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
+            0x30: initparam({{ Ra = cpu->system->init_param; }});
             0x40: resetstats({{
 		if (!xc->misspeculating())
 		    AlphaPseudo::resetstats(xc);