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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2005-03-01 22:32:14 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2005-03-01 22:32:14 -0500 |
| commit | 50a4ed87d0dc548e55d607381d0aecc35b02caf6 (patch) | |
| tree | 3df3b888e3a4746d5930e199c4026ad17c286855 /arch/alpha/isa_desc | |
| parent | d9de7c57837fa24177b8604daad638100c4e013a (diff) | |
| download | gem5-50a4ed87d0dc548e55d607381d0aecc35b02caf6.tar.xz | |
Two fixes to try and get TLB miss cost more in line with real platform:
1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).
arch/alpha/isa_desc:
Make hw_rei a serializing instruction (guarantees previous insts
complete before hw_rei will issue).
--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359
Diffstat (limited to 'arch/alpha/isa_desc')
| -rw-r--r-- | arch/alpha/isa_desc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 6a6bca4fe..0e07400d3 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2566,7 +2566,7 @@ decode OPCODE default Unknown::unknown() { } format BasicOperate { - 0x1e: hw_rei({{ xc->hwrei(); }}); + 0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing); // M5 special opcodes use the reserved 0x01 opcode space 0x01: decode M5FUNC { |