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authorSteve Reinhardt <stever@eecs.umich.edu>2003-10-26 22:37:14 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2003-10-26 22:37:14 -0800
commitced22d81a6f63e3b0d9089fe7cd3590ed51dbc1c (patch)
tree23ad90eadd98ff8cf4d5f9d5fecea8e96510f331 /arch/alpha/isa_desc
parent5e0b617283e468a273a65744b01f6f907b564f48 (diff)
downloadgem5-ced22d81a6f63e3b0d9089fe7cd3590ed51dbc1c.tar.xz
Fix some problems with stats reset & floss counters.
arch/alpha/isa_desc: Keep m5 pseudo-instructions (like resetstats) from taking effect on misspeculated paths. --HG-- extra : convert_revision : 7f0b0490164bca377ff2b14abc35a6c26bac9e6d
Diffstat (limited to 'arch/alpha/isa_desc')
-rw-r--r--arch/alpha/isa_desc32
1 files changed, 22 insertions, 10 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 3a0c1bffe..89ec05c0e 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2388,27 +2388,39 @@ decode OPCODE default Unknown::unknown() {
0x1e: hw_rei({{ xc->hwrei(); }});
// M5 special opcodes use the reserved 0x01 opcode space
- 0x01: decode M5FUNC{
+ 0x01: decode M5FUNC {
0x00: arm({{
- Annotate::ARM(xc);
- xc->kernelStats.arm();
+ if (!xc->misspeculating()) {
+ Annotate::ARM(xc);
+ xc->kernelStats.arm();
+ }
}});
0x01: quiesce({{
- Annotate::QUIESCE(xc);
- xc->setStatus(ExecContext::Suspended);
- xc->kernelStats.quiesce();
+ if (!xc->misspeculating()) {
+ Annotate::QUIESCE(xc);
+ xc->setStatus(ExecContext::Suspended);
+ xc->kernelStats.quiesce();
+ }
}});
0x10: ivlb({{
- Annotate::BeginInterval(xc);
- xc->kernelStats.ivlb();
+ if (!xc->misspeculating()) {
+ Annotate::BeginInterval(xc);
+ xc->kernelStats.ivlb();
+ }
+ }}, No_OpClass);
+ 0x11: ivle({{
+ if (!xc->misspeculating())
+ Annotate::EndInterval(xc);
}}, No_OpClass);
- 0x11: ivle({{ Annotate::EndInterval(xc); }}, No_OpClass);
0x20: m5exit({{
if (!xc->misspeculating())
m5_exit();
}}, No_OpClass);
0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
- 0x40: resetstats({{ Statistics::reset(); }});
+ 0x40: resetstats({{
+ if (!xc->misspeculating())
+ Statistics::reset();
+ }});
}
}