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authorSteve Reinhardt <stever@eecs.umich.edu>2004-10-24 23:06:35 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2004-10-24 23:06:35 -0400
commit400daa7e41057ec358691afeffe35ffa430d11b0 (patch)
tree06eaf8242206a12eb7a14281c7d112984c02ac89 /arch/alpha/isa_traits.hh
parent7c58c38e668ff4057820f8c6ee8cd8169b934051 (diff)
parent6ac0d27b7dc130397b6ba9b11e593706c2f669fe (diff)
downloadgem5-400daa7e41057ec358691afeffe35ffa430d11b0.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : aac76a4b82b3455620618bba6238507248cc68cc
Diffstat (limited to 'arch/alpha/isa_traits.hh')
-rw-r--r--arch/alpha/isa_traits.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 6559368e4..c73e79024 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -29,9 +29,9 @@
#ifndef __ISA_TRAITS_HH__
#define __ISA_TRAITS_HH__
-#include "sim/host.hh"
-#include "targetarch/faults.hh"
+#include "arch/alpha/faults.hh"
#include "base/misc.hh"
+#include "sim/host.hh"
class FastCPU;
class FullCPU;
@@ -125,7 +125,7 @@ class AlphaISA
typedef uint64_t InternalProcReg;
-#include "targetarch/isa_fullsys_traits.hh"
+#include "arch/alpha/isa_fullsys_traits.hh"
#else
enum {
@@ -278,7 +278,7 @@ const int NumInterruptLevels = TheISA::NumInterruptLevels;
// more stuff that should be imported here, but I'm too tired to do it
// right now...
-#include "targetarch/ev5.hh"
+#include "arch/alpha/ev5.hh"
#endif
#endif // __ALPHA_ISA_H__