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authorAli Saidi <saidi@eecs.umich.edu>2006-03-09 15:56:42 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-03-09 15:56:42 -0500
commit56cc760f6f53138c133c5d4e1f9d3e3199965d99 (patch)
tree991271751791743eb9db33508fd3d183e61772be /arch/alpha/isa_traits.hh
parent91545ac2bf5ac47ecbfc403ef6e2b2ce340ae551 (diff)
parentce3a6343b6c54e95d63403d46c9ddea384e49476 (diff)
downloadgem5-56cc760f6f53138c133c5d4e1f9d3e3199965d99.tar.xz
Merge zizzer:/bk/multiarch
into zeep.eecs.umich.edu:/z/saidi/work/m5.ma2 arch/alpha/isa_traits.hh: arch/alpha/linux/process.cc: arch/sparc/isa_traits.hh: arch/sparc/linux/process.cc: sim/process.cc: merge --HG-- rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : fea0155c8e23abbd0d5d5251abbd0f4d223fe935
Diffstat (limited to 'arch/alpha/isa_traits.hh')
-rw-r--r--arch/alpha/isa_traits.hh95
1 files changed, 57 insertions, 38 deletions
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 3cd6868b8..6f6b11e62 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -53,6 +53,44 @@ int DTB_ASN_ASN(uint64_t reg);
int ITB_ASN_ASN(uint64_t reg);
}
+#if !FULL_SYSTEM
+class SyscallReturn {
+ public:
+ template <class T>
+ SyscallReturn(T v, bool s)
+ {
+ retval = (uint64_t)v;
+ success = s;
+ }
+
+ template <class T>
+ SyscallReturn(T v)
+ {
+ success = (v >= 0);
+ retval = (uint64_t)v;
+ }
+
+ ~SyscallReturn() {}
+
+ SyscallReturn& operator=(const SyscallReturn& s) {
+ retval = s.retval;
+ success = s.success;
+ return *this;
+ }
+
+ bool successful() { return success; }
+ uint64_t value() { return retval; }
+
+
+ private:
+ uint64_t retval;
+ bool success;
+};
+
+#endif
+
+
+
namespace AlphaISA
{
@@ -85,6 +123,10 @@ namespace AlphaISA
const int ArgumentReg3 = 19;
const int ArgumentReg4 = 20;
const int ArgumentReg5 = 21;
+ const int SyscallNumReg = ReturnValueReg;
+ const int SyscallPseudoReturnReg = ArgumentReg4;
+
+
const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);
@@ -299,44 +341,21 @@ extern const int reg_redir[NumIntRegs];
template <class XC>
void zeroRegisters(XC *xc);
- const Addr MaxAddr = (Addr)-1;
-};
-
-#if !FULL_SYSTEM
-class SyscallReturn {
- public:
- template <class T>
- SyscallReturn(T v, bool s)
- {
- retval = (uint64_t)v;
- success = s;
- }
-
- template <class T>
- SyscallReturn(T v)
- {
- success = (v >= 0);
- retval = (uint64_t)v;
- }
-
- ~SyscallReturn() {}
-
- SyscallReturn& operator=(const SyscallReturn& s) {
- retval = s.retval;
- success = s.success;
- return *this;
- }
-
- bool successful() { return success; }
- uint64_t value() { return retval; }
-
-
- private:
- uint64_t retval;
- bool success;
-};
-
-#endif
+ static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
+ {
+ // check for error condition. Alpha syscall convention is to
+ // indicate success/failure in reg a3 (r19) and put the
+ // return value itself in the standard return value reg (v0).
+ if (return_value.successful()) {
+ // no error
+ regs->intRegFile[SyscallSuccessReg] = 0;
+ regs->intRegFile[ReturnValueReg] = return_value.value();
+ } else {
+ // got an error, return details
+ regs->intRegFile[SyscallSuccessReg] = (IntReg) -1;
+ regs->intRegFile[ReturnValueReg] = -return_value.value();
+ }
+ }
static inline AlphaISA::ExtMachInst
AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {