Fix timing modeling of faults: functionally the very next instruction after

a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model.  New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).

Also fix Ali's bad-address assertion that doesn't apply to full system.

Added some more debugging support in the process.  Hopefully we'll move to the new
cpu model soon and we won't need it anymore.

arch/alpha/alpha_memory.cc:
    Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
    Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
    Replace "Dispatch" flag with "Pipeline" (since I added similar
    DPRINTFs in other pipe stages).
cpu/exetrace.cc:
    Change default for printing mis-speculated instructions to true (since
    that's often what we want, and right now you can't change it from the
    command line...).

--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc

1 files changed, 3 insertions, 0 deletions

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index ff3da1502..8db8c6994 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -175,6 +175,9 @@ static const Addr PageOffset = PageBytes - 1;
 
     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
 
+    // return a no-op instruction... used for instruction fetch faults
+    static const MachInst NoopMachInst;
+
     enum annotes {
         ANNOTE_NONE = 0,
         // An impossible number for instruction annotations