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author | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-29 21:45:39 -0800 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-29 21:45:39 -0800 |
commit | 5a1eb9049d16d37448282362529d462d73558181 (patch) | |
tree | fb1d5a05dad6869173a352abb16ddca7b3a1667f /arch/alpha/isa_traits.hh | |
parent | 976429121c7fddbf8de18b2a347a53546fe14264 (diff) | |
download | gem5-5a1eb9049d16d37448282362529d462d73558181.tar.xz |
Support for Serializable non-SimObject things like events.
Can now serialize & unserialize DmaRequestEvents and DmaTransferEvents.
Also support serialize/unserialize of pointers to SimObjects and
other Serializable objects.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
unserialize() now takes a Checkpoint* instead of an IniFile*.
cpu/simple_cpu/simple_cpu.cc:
unserialize() now takes a Checkpoint* instead of an IniFile*.
Put ExecContext in its own section so its _status fields doesn't conflict.
sim/eventq.cc:
sim/eventq.hh:
unserialize() now takes a Checkpoint* instead of an IniFile*.
Events get serialized by the event queue only if they're marked
as AutoSerialize... others are assumed to be serialized by something
else (e.g. an owning SimObject) or to not matter.
sim/param.cc:
Shift 'const' in case T is a ptr type.
sim/serialize.cc:
sim/serialize.hh:
Define Checkpoint object to encapsulate everything you need to know
about a checkpoint. Use it to allow lookups of named Serializable
objects (and SimObjects) during unserialization.
unserialize() now takes a Checkpoint* instead of an IniFile*.
--HG--
extra : convert_revision : 8e6baab32405f8f548bb67a097b2f713296537a5
Diffstat (limited to 'arch/alpha/isa_traits.hh')
-rw-r--r-- | arch/alpha/isa_traits.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index fbdcffbcf..406ffb6f3 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -34,7 +34,7 @@ #include "base/misc.hh" class FullCPU; -class IniFile; +class Checkpoint; #define TARGET_ALPHA @@ -160,7 +160,7 @@ class AlphaISA uint8_t opcode, ra; // current instruction details (for intr's) void serialize(std::ostream &os); - void unserialize(const IniFile *db, const std::string §ion); + void unserialize(Checkpoint *cp, const std::string §ion); }; static StaticInstPtr<AlphaISA> decodeInst(MachInst); |