Move the m5 pseudo instructions into their own file

arch/alpha/isa_desc:
    Move the pseudo instructions out of the isa_desc, into their own
    file and call out to them when they're to be accessed
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
    move SimExit to sim_exit.cc

--HG--
extra : convert_revision : 1c393adb1c18bd0fef065057d7f4e9cf60ac4197

1 files changed, 101 insertions, 0 deletions

diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc
new file mode 100644
index 000000000..1f24a07f5
--- /dev/null
+++ b/arch/alpha/pseudo_inst.cc
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/alpha/pseudo_inst.hh"
+#include "cpu/exec_context.hh"
+#include "sim/serialize.hh"
+#include "sim/sim_exit.hh"
+#include "sim/sim_stats.hh"
+
+using namespace Statistics;
+
+namespace AlphaPseudo
+{
+    void
+    m5exit_old(ExecContext *xc)
+    {
+        SimExit(curTick, "m5_exit_old instruction encountered");
+    }
+
+    void
+    m5exit(ExecContext *xc)
+    {
+        Tick delay = xc->regs.intRegFile[16];
+        Tick when = curTick + NS2Ticks(delay);
+        SimExit(when, "m5_exit instruction encountered");
+    }
+
+    void
+    resetstats(ExecContext *xc)
+    {
+        Tick delay = xc->regs.intRegFile[16];
+        Tick period = xc->regs.intRegFile[17];
+
+        Tick when = curTick + NS2Ticks(delay);
+        Tick repeat = NS2Ticks(period);
+
+        SetupEvent(Reset, when, repeat);
+    }
+
+    void
+    dumpstats(ExecContext *xc)
+    {
+        Tick delay = xc->regs.intRegFile[16];
+        Tick period = xc->regs.intRegFile[17];
+
+        Tick when = curTick + NS2Ticks(delay);
+        Tick repeat = NS2Ticks(period);
+
+        SetupEvent(Dump, when, repeat);
+    }
+
+    void
+    dumpresetstats(ExecContext *xc)
+    {
+        Tick delay = xc->regs.intRegFile[16];
+        Tick period = xc->regs.intRegFile[17];
+
+        Tick when = curTick + NS2Ticks(delay);
+        Tick repeat = NS2Ticks(period);
+
+        SetupEvent(Dump|Reset, when, repeat);
+    }
+
+    void
+    m5checkpoint(ExecContext *xc)
+    {
+        Tick delay = xc->regs.intRegFile[16];
+        Tick period = xc->regs.intRegFile[17];
+
+        Tick when = curTick + NS2Ticks(delay);
+        Tick repeat = NS2Ticks(period);
+
+        SetupCheckpoint(when, repeat);
+    }
+
+}