added m5 debug and m5 switch cpu instruction (doesn't work yet) and

a p4 memory/cpu config

arch/alpha/alpha_memory.cc:
    Added code to fault on an unaligned access
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
    Added m5debug break and m5switchcpu (the latter doesn't work)

--HG--
extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916

1 files changed, 16 insertions, 0 deletions

diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc
index 370266909..fd6742801 100644
--- a/arch/alpha/pseudo_inst.cc
+++ b/arch/alpha/pseudo_inst.cc
@@ -35,6 +35,7 @@
 #include "arch/alpha/pseudo_inst.hh"
 #include "arch/alpha/vtophys.hh"
 #include "cpu/base_cpu.hh"
+#include "cpu/sampling_cpu/sampling_cpu.hh"
 #include "cpu/exec_context.hh"
 #include "sim/param.hh"
 #include "sim/serialize.hh"
@@ -42,8 +43,12 @@
 #include "sim/stat_control.hh"
 #include "sim/stats.hh"
 #include "sim/system.hh"
+#include "sim/debug.hh"
 
 using namespace std;
+
+extern SamplingCPU *SampCPU;
+
 using namespace Stats;
 
 namespace AlphaPseudo
@@ -219,4 +224,15 @@ namespace AlphaPseudo
         doStatisticsInsts = __statistics;
         doCheckpointInsts = __checkpoint;
     }
+
+    void debugbreak(ExecContext *xc)
+    {
+        debug_break();
+    }
+
+    void switchcpu(ExecContext *xc)
+    {
+        if (SampCPU)
+            SampCPU->switchCPUs();
+    }
 }