First cut at moving alpha specefic stuff out of /sim/system* into

arch/alpha/system*.

SConscript:
dev/alpha_console.cc:
dev/alpha_console.hh:
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
kern/kernel_stats.cc:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/pseudo_inst.cc:
sim/system.cc:
sim/system.hh:
    First cut at moving alpha specefic stuff out of /sim/system*

--HG--
extra : convert_revision : eba58f537fc04e605af4fc216e184b074a44c8a0

1 files changed, 298 insertions, 0 deletions

diff --git a/arch/alpha/system.cc b/arch/alpha/system.cc
new file mode 100644
index 000000000..b841a6d53
--- /dev/null
+++ b/arch/alpha/system.cc
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/alpha/system.hh"
+#include "base/remote_gdb.hh"
+#include "base/loader/object_file.hh"
+#include "base/loader/symtab.hh"
+#include "base/trace.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
+#include "sim/byteswap.hh"
+#include "sim/builder.hh"
+#include "targetarch/vtophys.hh"
+
+using namespace LittleEndianGuest;
+
+AlphaSystem::AlphaSystem(Params *p)
+    : System(p)
+{
+    consoleSymtab = new SymbolTable;
+    palSymtab = new SymbolTable;
+
+
+    /**
+     * Load the pal, and console code into memory
+     */
+    // Load Console Code
+    console = createObjectFile(params()->console_path);
+    if (console == NULL)
+        fatal("Could not load console file %s", params()->console_path);
+
+    // Load pal file
+    pal = createObjectFile(params()->palcode);
+    if (pal == NULL)
+        fatal("Could not load PALcode file %s", params()->palcode);
+
+
+    // Load program sections into memory
+    pal->loadSections(physmem, true);
+    console->loadSections(physmem, true);
+
+    // load symbols
+    if (!console->loadGlobalSymbols(consoleSymtab))
+        panic("could not load console symbols\n");
+
+    if (!pal->loadGlobalSymbols(palSymtab))
+        panic("could not load pal symbols\n");
+
+    if (!pal->loadLocalSymbols(palSymtab))
+        panic("could not load pal symbols\n");
+
+    if (!console->loadGlobalSymbols(debugSymbolTable))
+        panic("could not load console symbols\n");
+
+    if (!pal->loadGlobalSymbols(debugSymbolTable))
+        panic("could not load pal symbols\n");
+
+    if (!pal->loadLocalSymbols(debugSymbolTable))
+        panic("could not load pal symbols\n");
+
+     Addr addr = 0;
+#ifndef NDEBUG
+    consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic");
+#endif
+
+    /**
+     * Copy the osflags (kernel arguments) into the consoles
+     * memory. (Presently Linux does not use the console service
+     * routine to get these command line arguments, but Tru64 and
+     * others do.)
+     */
+    if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
+        Addr paddr = vtophys(physmem, addr);
+        char *osflags = (char *)physmem->dma_addr(paddr, sizeof(uint32_t));
+
+        if (osflags)
+              strcpy(osflags, params()->boot_osflags.c_str());
+    }
+
+    /**
+     * Set the hardware reset parameter block system type and revision
+     * information to Tsunami.
+     */
+    if (consoleSymtab->findAddress("m5_rpb", addr)) {
+        Addr paddr = vtophys(physmem, addr);
+        char *hwrpb = (char *)physmem->dma_addr(paddr, sizeof(uint64_t));
+
+        if (!hwrpb)
+            panic("could not translate hwrpb addr\n");
+
+        *(uint64_t*)(hwrpb+0x50) = htog(params()->system_type);
+        *(uint64_t*)(hwrpb+0x58) = htog(params()->system_rev);
+    } else
+        panic("could not find hwrpb\n");
+
+}
+
+AlphaSystem::~AlphaSystem()
+{
+    delete consoleSymtab;
+    delete console;
+    delete pal;
+#ifdef DEBUG
+    delete consolePanicEvent;
+#endif
+}
+
+/**
+ * This function fixes up addresses that are used to match PCs for
+ * hooking simulator events on to target function executions.
+ *
+ * Alpha binaries may have multiple global offset table (GOT)
+ * sections.  A function that uses the GOT starts with a
+ * two-instruction prolog which sets the global pointer (gp == r29) to
+ * the appropriate GOT section.  The proper gp value is calculated
+ * based on the function address, which must be passed by the caller
+ * in the procedure value register (pv aka t12 == r27).  This sequence
+ * looks like the following:
+ *
+ *			opcode Ra Rb offset
+ *	ldah gp,X(pv)     09   29 27   X
+ *	lda  gp,Y(gp)     08   29 29   Y
+ *
+ * for some constant offsets X and Y.  The catch is that the linker
+ * (or maybe even the compiler, I'm not sure) may recognize that the
+ * caller and callee are using the same GOT section, making this
+ * prolog redundant, and modify the call target to skip these
+ * instructions.  If we check for execution of the first instruction
+ * of a function (the one the symbol points to) to detect when to skip
+ * it, we'll miss all these modified calls.  It might work to
+ * unconditionally check for the third instruction, but not all
+ * functions have this prolog, and there's some chance that those
+ * first two instructions could have undesired consequences.  So we do
+ * the Right Thing and pattern-match the first two instructions of the
+ * function to decide where to patch.
+ *
+ * Eventually this code should be moved into an ISA-specific file.
+ */
+Addr
+AlphaSystem::fixFuncEventAddr(Addr addr)
+{
+    // mask for just the opcode, Ra, and Rb fields (not the offset)
+    const uint32_t inst_mask = 0xffff0000;
+    // ldah gp,X(pv): opcode 9, Ra = 29, Rb = 27
+    const uint32_t gp_ldah_pattern = (9 << 26) | (29 << 21) | (27 << 16);
+    // lda  gp,Y(gp): opcode 8, Ra = 29, rb = 29
+    const uint32_t gp_lda_pattern  = (8 << 26) | (29 << 21) | (29 << 16);
+    // instruction size
+    const int sz = sizeof(uint32_t);
+
+    Addr paddr = vtophys(physmem, addr);
+    uint32_t i1 = *(uint32_t *)physmem->dma_addr(paddr, sz);
+    uint32_t i2 = *(uint32_t *)physmem->dma_addr(paddr+sz, sz);
+
+    if ((i1 & inst_mask) == gp_ldah_pattern &&
+        (i2 & inst_mask) == gp_lda_pattern) {
+        Addr new_addr = addr + 2*sz;
+        DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr);
+        return new_addr;
+    } else {
+        return addr;
+    }
+}
+
+
+void
+AlphaSystem::setAlphaAccess(Addr access)
+{
+    Addr addr = 0;
+    if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
+        Addr paddr = vtophys(physmem, addr);
+        uint64_t *m5AlphaAccess =
+            (uint64_t *)physmem->dma_addr(paddr, sizeof(uint64_t));
+
+        if (!m5AlphaAccess)
+            panic("could not translate m5AlphaAccess addr\n");
+
+        *m5AlphaAccess = htog(EV5::Phys2K0Seg(access));
+    } else
+        panic("could not find m5AlphaAccess\n");
+}
+
+bool
+AlphaSystem::breakpoint()
+{
+    return remoteGDB[0]->trap(ALPHA_KENTRY_INT);
+}
+
+void
+AlphaSystem::serialize(std::ostream &os)
+{
+    System::serialize(os);
+    consoleSymtab->serialize("console_symtab", os);
+    palSymtab->serialize("pal_symtab", os);
+}
+
+
+void
+AlphaSystem::unserialize(Checkpoint *cp, const std::string &section)
+{
+    System::unserialize(cp,section);
+    consoleSymtab->unserialize("console_symtab", cp, section);
+    palSymtab->unserialize("pal_symtab", cp, section);
+}
+
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
+
+    Param<Tick> boot_cpu_frequency;
+    SimObjectParam<MemoryController *> memctrl;
+    SimObjectParam<PhysicalMemory *> physmem;
+
+    Param<std::string> kernel;
+    Param<std::string> console;
+    Param<std::string> pal;
+
+    Param<std::string> boot_osflags;
+    Param<std::string> readfile;
+    Param<unsigned int> init_param;
+
+    Param<uint64_t> system_type;
+    Param<uint64_t> system_rev;
+
+    Param<bool> bin;
+    VectorParam<std::string> binned_fns;
+    Param<bool> bin_int;
+
+END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
+
+    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
+    INIT_PARAM(memctrl, "memory controller"),
+    INIT_PARAM(physmem, "phsyical memory"),
+    INIT_PARAM(kernel, "file that contains the kernel code"),
+    INIT_PARAM(console, "file that contains the console code"),
+    INIT_PARAM(pal, "file that contains palcode"),
+    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
+                    "a"),
+    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
+    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
+    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
+    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
+    INIT_PARAM_DFLT(bin, "is this system to be binned", false),
+    INIT_PARAM(binned_fns, "functions to be broken down and binned"),
+    INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
+
+END_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
+
+CREATE_SIM_OBJECT(AlphaSystem)
+{
+    AlphaSystem::Params *p = new AlphaSystem::Params;
+    p->name = getInstanceName();
+    p->boot_cpu_frequency = boot_cpu_frequency;
+    p->memctrl = memctrl;
+    p->physmem = physmem;
+    p->kernel_path = kernel;
+    p->console_path = console;
+    p->palcode = pal;
+    p->boot_osflags = boot_osflags;
+    p->init_param = init_param;
+    p->readfile = readfile;
+    p->system_type = system_type;
+    p->system_rev = system_rev;
+    p->bin = bin;
+    p->binned_fns = binned_fns;
+    p->bin_int = bin_int;
+    return new AlphaSystem(p);
+}
+
+REGISTER_SIM_OBJECT("AlphaSystem", AlphaSystem)
+
+