diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-31 20:32:18 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-31 20:32:18 -0500 |
| commit | adeb458b878d0768fd4de82bc1997512dc65e6d3 (patch) | |
| tree | d7b27950803618125f7c2fcfa3353e4e40e0166c /arch/alpha/tlb.cc | |
| parent | 5c79eb04104e6e3dd2fd957c071fef3ceb47b722 (diff) | |
| parent | 5936c79ba0f3fd29ef2bbf41fcaddc78fcd9c75c (diff) | |
| download | gem5-adeb458b878d0768fd4de82bc1997512dc65e6d3.tar.xz | |
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision : 08ae5e999d9b313e3e40cb6d58863905b70ca781
Diffstat (limited to 'arch/alpha/tlb.cc')
| -rw-r--r-- | arch/alpha/tlb.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc index 562235ef8..3f991b10c 100644 --- a/arch/alpha/tlb.cc +++ b/arch/alpha/tlb.cc @@ -94,7 +94,7 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const void -AlphaTLB::checkCacheability(MemReqPtr &req) +AlphaTLB::checkCacheability(CpuRequestPtr &req) { // in Alpha, cacheability is controlled by upper-level bits of the // physical address @@ -292,7 +292,7 @@ AlphaITB::regStats() Fault -AlphaITB::translate(MemReqPtr &req) const +AlphaITB::translate(CpuRequestPtr &req) const { ExecContext *xc = req->xc; @@ -451,7 +451,7 @@ AlphaDTB::regStats() } Fault -AlphaDTB::translate(MemReqPtr &req, bool write) const +AlphaDTB::translate(CpuRequestPtr &req, bool write) const { ExecContext *xc = req->xc; Addr pc = xc->readPC(); |