fixes for new memory system

SConscript:
    comment out most devices
    add vport.cc
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
    push in alpha name space
    fix for new memory system
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Added an unimplemented fault that can be returned if a certain
    function isn't implemented
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
arch/alpha/stacktrace.cc:
arch/alpha/system.cc:
arch/alpha/tlb.hh:
arch/alpha/tru64/system.cc:
    fixed for new memory system
arch/alpha/tlb.cc:
    fixed for new memory system
    removed code that seems to have no purpose
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
    fixed for new memory system
    put in namespace AlphaISA
base/remote_gdb.cc:
    fix for new memory system
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
    create two ports one of physical accesses and one for superpage accesses
    Add functions getVirtPort() getPhysPort() delVirtPort(). To get statically
    allocated physical or virtual ports or if an execcontext is passed in
    get a dynamically allocated virtual port
dev/alpha_console.cc:
dev/alpha_console.hh:
    Redo for new memory system
dev/io_device.cc:
dev/io_device.hh:
    new I/O devices for new memory system
kern/linux/events.cc:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/tru64/dump_mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
    Arguments now in namespaces
kern/tru64/tru64_events.cc:
mem/bus.cc:
    fix for new memory syste
mem/physical.hh:
    new addressranges function
    getPort should be public
mem/port.hh:
    Add write/read methods to functional port
    update getDeviceAddrRanges to have a list of both snoops and response lists
sim/pseudo_inst.cc:
sim/system.cc:
sim/system.hh:
    Update for new mem system
sim/vptr.hh:
    comment out code and replace with panics
    This will need to be fixed at some point, but it's not easy.

--HG--
extra : convert_revision : 41f41f422cfbab3751284d55cccb6ea64a7956e2

1 files changed, 7 insertions, 22 deletions

diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc
index 3f991b10c..a1a7c9366 100644
--- a/arch/alpha/tlb.cc
+++ b/arch/alpha/tlb.cc
@@ -93,7 +93,7 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const
 }
 
 
-void
+Fault
 AlphaTLB::checkCacheability(CpuRequestPtr &req)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
@@ -115,17 +115,7 @@ AlphaTLB::checkCacheability(CpuRequestPtr &req)
 #endif
         // IPR memory space not implemented
         if (PAddrIprSpace(req->paddr)) {
-            if (!req->xc->misspeculating()) {
-                switch (req->paddr) {
-                  case ULL(0xFFFFF00188):
-                    req->data = 0;
-                    break;
-
-                  default:
-                    panic("IPR memory space not implemented! PA=%x\n",
-                          req->paddr);
-                }
-            }
+            return new UnimpFault("IPR memory space not implemented!");
         } else {
             // mark request as uncacheable
             req->flags |= UNCACHEABLE;
@@ -136,6 +126,7 @@ AlphaTLB::checkCacheability(CpuRequestPtr &req)
 #endif
         }
     }
+    return NoFault;
 }
 
 
@@ -292,10 +283,8 @@ AlphaITB::regStats()
 
 
 Fault
-AlphaITB::translate(CpuRequestPtr &req) const
+AlphaITB::translate(CpuRequestPtr &req, ExecContext *xc) const
 {
-    ExecContext *xc = req->xc;
-
     if (AlphaISA::PcPAL(req->vaddr)) {
         // strip off PAL PC marker (lsb is 1)
         req->paddr = (req->vaddr & ~3) & PAddrImplMask;
@@ -368,9 +357,8 @@ AlphaITB::translate(CpuRequestPtr &req) const
     if (req->paddr & ~PAddrImplMask)
         return genMachineCheckFault();
 
-    checkCacheability(req);
+    return checkCacheability(req);
 
-    return NoFault;
 }
 
 ///////////////////////////////////////////////////////////////////////
@@ -451,9 +439,8 @@ AlphaDTB::regStats()
 }
 
 Fault
-AlphaDTB::translate(CpuRequestPtr &req, bool write) const
+AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
 {
-    ExecContext *xc = req->xc;
     Addr pc = xc->readPC();
 
     AlphaISA::mode_type mode =
@@ -583,9 +570,7 @@ AlphaDTB::translate(CpuRequestPtr &req, bool write) const
     if (req->paddr & ~PAddrImplMask)
         return genMachineCheckFault();
 
-    checkCacheability(req);
-
-    return NoFault;
+    return checkCacheability(req);
 }
 
 AlphaISA::PTE &