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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-04-06 15:00:11 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-04-06 15:00:11 -0400 |
| commit | 6a962f8343d0e7f138baa4034633c986eecc9edf (patch) | |
| tree | f16fdcc7455b0e7cd14af660ebdeb029db3c669a /arch/alpha/tlb.hh | |
| parent | 3124c5b7bb0cdcb3b16b52533c6a3e50a5970152 (diff) | |
| parent | 6240f8c4bcf12e3367905adfba066bb14f79262a (diff) | |
| download | gem5-6a962f8343d0e7f138baa4034633c986eecc9edf.tar.xz | |
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision : bd6352647798275a12d52d55a129cdddd8e25423
Diffstat (limited to 'arch/alpha/tlb.hh')
| -rw-r--r-- | arch/alpha/tlb.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/alpha/tlb.hh b/arch/alpha/tlb.hh index fe156b7e3..39faffbee 100644 --- a/arch/alpha/tlb.hh +++ b/arch/alpha/tlb.hh @@ -73,7 +73,7 @@ class AlphaTLB : public SimObject return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); } - static void checkCacheability(CpuRequestPtr &req); + static Fault checkCacheability(CpuRequestPtr &req); // Checkpointing virtual void serialize(std::ostream &os); @@ -92,7 +92,7 @@ class AlphaITB : public AlphaTLB AlphaITB(const std::string &name, int size); virtual void regStats(); - Fault translate(CpuRequestPtr &req) const; + Fault translate(CpuRequestPtr &req, ExecContext *xc) const; }; class AlphaDTB : public AlphaTLB @@ -115,7 +115,7 @@ class AlphaDTB : public AlphaTLB AlphaDTB(const std::string &name, int size); virtual void regStats(); - Fault translate(CpuRequestPtr &req, bool write) const; + Fault translate(CpuRequestPtr &req, ExecContext *xc, bool write) const; }; #endif // __ALPHA_MEMORY_HH__ |