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| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-29 18:42:53 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-29 18:42:53 -0500 |
| commit | 2ad1db3fde4f95eaf0b1be77910de0feb2185712 (patch) | |
| tree | 0105265c89557bde3d8f1e10687ae5568ed5b262 /arch/alpha/tlb.hh | |
| parent | 3dcb589ea46290ecfe2c2e54ebf2ba8921a932ed (diff) | |
| download | gem5-2ad1db3fde4f95eaf0b1be77910de0feb2185712.tar.xz | |
page_table.cc is a syscall only kinda thing
fix tlbs for newmem
SConscript:
page_table.cc is a syscall only kinda thing
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
fix tlbs for newmem
--HG--
extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408
Diffstat (limited to 'arch/alpha/tlb.hh')
| -rw-r--r-- | arch/alpha/tlb.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/alpha/tlb.hh b/arch/alpha/tlb.hh index 676345f01..fe156b7e3 100644 --- a/arch/alpha/tlb.hh +++ b/arch/alpha/tlb.hh @@ -35,7 +35,7 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/faults.hh" #include "base/statistics.hh" -#include "mem/mem_req.hh" +#include "mem/request.hh" #include "sim/sim_object.hh" class ExecContext; @@ -73,7 +73,7 @@ class AlphaTLB : public SimObject return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); } - static void checkCacheability(MemReqPtr &req); + static void checkCacheability(CpuRequestPtr &req); // Checkpointing virtual void serialize(std::ostream &os); @@ -92,7 +92,7 @@ class AlphaITB : public AlphaTLB AlphaITB(const std::string &name, int size); virtual void regStats(); - Fault translate(MemReqPtr &req) const; + Fault translate(CpuRequestPtr &req) const; }; class AlphaDTB : public AlphaTLB @@ -115,7 +115,7 @@ class AlphaDTB : public AlphaTLB AlphaDTB(const std::string &name, int size); virtual void regStats(); - Fault translate(MemReqPtr &req, bool write) const; + Fault translate(CpuRequestPtr &req, bool write) const; }; #endif // __ALPHA_MEMORY_HH__ |