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authorNathan Binkert <binkertn@umich.edu>2003-11-02 02:07:31 -0500
committerNathan Binkert <binkertn@umich.edu>2003-11-02 02:07:31 -0500
commitc7d6745b073982782eb05ca523b53e1c7fe784da (patch)
treea8b4047fe21b28aaa2234aa1d22a3eb0e31d34f9 /arch/alpha
parent7c6fa585ca5f0d79024a7f83faacaebf29f95999 (diff)
downloadgem5-c7d6745b073982782eb05ca523b53e1c7fe784da.tar.xz
deprecate the m5exit instruction and rename it to m5exit_old
Implement a new m5exit instruction with an optional delay arch/alpha/isa_desc: move m5exit to m5exit old. The old version of the instruction is now deprecated Implement the new exit instruction with the optional delay sim/sim_events.cc: sim/sim_events.hh: Make SimExit take a cycle sim/universe.cc: provide ticksPerMS, ticksPerUS, and ticksPerNS so we don't have to do math during the cycle --HG-- extra : convert_revision : e2ed47a2e5cfcd57c82086c6fcb4a28bf801c214
Diffstat (limited to 'arch/alpha')
-rw-r--r--arch/alpha/isa_desc16
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 75f765029..09fb4a50a 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2425,9 +2425,21 @@ decode OPCODE default Unknown::unknown() {
if (!xc->misspeculating())
Annotate::EndInterval(xc);
}}, No_OpClass);
- 0x20: m5exit({{
+ 0x20: m5exit_old({{
if (!xc->misspeculating())
- SimExit("m5_exit instruction encountered");
+ SimExit(curTick, "m5_exit_old instruction encountered");
+ }}, No_OpClass);
+ 0x21: m5exit({{
+ if (!xc->misspeculating()) {
+ Tick when = curTick;
+ Tick delay = xc->regs.intRegFile[16];
+ if (delay != 0) {
+ delay *= ticksPerUS;
+ delay /= 1000;
+ when += delay;
+ }
+ SimExit(when, "m5_exit instruction encountered");
+ }
}}, No_OpClass);
0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
0x40: resetstats({{