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authorGabe Black <gblack@eecs.umich.edu>2006-02-28 06:02:18 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-28 06:02:18 -0500
commit299efffaf5eb5fb55b2109a643e1e0e985f89ce6 (patch)
treea907d19867b35f26e11d9c9f5fe3b38e33853c2c /arch/alpha
parent6165419d356fb0cdbcb70d22dcd2f32e689eb7db (diff)
downloadgem5-299efffaf5eb5fb55b2109a643e1e0e985f89ce6.tar.xz
Cleaned up and slightly reorganized the Fault class heirarchy.
arch/alpha/ev5.cc: Changed c style casts of Faults to dynamic_casts arch/alpha/faults.cc: AlphaFault is now an abstract class. arch/alpha/faults.hh: AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes. cpu/o3/alpha_cpu_impl.hh: Changed a c style cast to a dynamic_cast for a Fault sim/faults.hh: All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults. --HG-- extra : convert_revision : 2cb906708e3eaec4a12587484c09e50ed6ef88fc
Diffstat (limited to 'arch/alpha')
-rw-r--r--arch/alpha/ev5.cc6
-rw-r--r--arch/alpha/faults.cc4
-rw-r--r--arch/alpha/faults.hh18
3 files changed, 12 insertions, 16 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 23546bbe2..ca26fc257 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -192,7 +192,8 @@ ExecContext::ev5_temp_trap(Fault fault)
if (!inPalMode())
AlphaISA::swap_palshadow(&regs, true);
- regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + ((AlphaFault *)(fault.get()))->vect();
+ regs.pc = ipr[AlphaISA::IPR_PAL_BASE] +
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect();
regs.npc = regs.pc + sizeof(MachInst);
}
@@ -217,7 +218,8 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
- regs->npc = ipr[IPR_PAL_BASE] + ((AlphaFault *)(fault.get()))->vect();
+ regs->npc = ipr[IPR_PAL_BASE] +
+ (dynamic_cast<AlphaFault *>(fault.get()))->vect();
else
regs->npc = ipr[IPR_PAL_BASE] + pc;
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index 2eedfedbd..78613761d 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -32,10 +32,6 @@
namespace AlphaISA
{
-FaultName AlphaFault::_name = "alphafault";
-FaultVect AlphaFault::_vect = 0x0000;
-FaultStat AlphaFault::_stat;
-
FaultVect AlphaMachineCheckFault::_vect = 0x0401;
FaultStat AlphaMachineCheckFault::_stat;
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 7c52738c1..156faa8fb 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -38,22 +38,18 @@ namespace AlphaISA
typedef const Addr FaultVect;
-class AlphaFault : public FaultBase
+class AlphaFault : public virtual FaultBase
{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _stat;
public:
#if FULL_SYSTEM
void ev5_trap(ExecContext * xc);
#endif
- FaultName name() {return _name;}
- virtual FaultVect vect() {return _vect;}
- virtual FaultStat & stat() {return _stat;}
+ virtual FaultVect vect() = 0;
};
-class AlphaMachineCheckFault : public MachineCheckFault
+class AlphaMachineCheckFault :
+ public MachineCheckFault,
+ public AlphaFault
{
private:
static FaultVect _vect;
@@ -66,7 +62,9 @@ class AlphaMachineCheckFault : public MachineCheckFault
FaultStat & stat() {return _stat;}
};
-class AlphaAlignmentFault : public AlignmentFault
+class AlphaAlignmentFault :
+ public AlignmentFault,
+ public AlphaFault
{
private:
static FaultVect _vect;