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authorKevin Lim <ktlim@umich.edu>2005-02-04 18:25:49 -0500
committerKevin Lim <ktlim@umich.edu>2005-02-04 18:25:49 -0500
commit1e7a744c09d0bde70e0f83179fdf4d6059585e4b (patch)
tree9bbc7713c4bb79abb3f76b07547d8822f0557caa /arch/alpha
parentc389c2e327cc3ee1c988855b05505660c6670172 (diff)
parentb78d7c2f16dac11ed468de45a088a362605c6493 (diff)
downloadgem5-1e7a744c09d0bde70e0f83179fdf4d6059585e4b.tar.xz
Hand merge
--HG-- extra : convert_revision : 86c7399b79c17558041a73056745227f70fe8b3b
Diffstat (limited to 'arch/alpha')
-rw-r--r--arch/alpha/alpha_linux_process.cc16
-rw-r--r--arch/alpha/isa_desc171
-rw-r--r--arch/alpha/pseudo_inst.cc2
-rw-r--r--arch/alpha/vptr.hh11
4 files changed, 118 insertions, 82 deletions
diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc
index 67bb0ab3b..ba4b1d07e 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/alpha_linux_process.cc
@@ -26,24 +26,24 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <dirent.h>
#include <errno.h>
-#include <unistd.h>
#include <fcntl.h> // for host open() flags
-#include <sys/types.h>
-#include <sys/stat.h>
#include <string.h> // for memset()
-#include <dirent.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
-#include "sim/host.hh"
#include "cpu/base_cpu.hh"
-#include "mem/functional_mem/functional_memory.hh"
-#include "sim/process.hh"
#include "cpu/exec_context.hh"
+#include "mem/functional_mem/functional_memory.hh"
#include "sim/fake_syscall.hh"
+#include "sim/host.hh"
+#include "sim/process.hh"
#include "sim/sim_events.hh"
-#include "sim/syscall_emul.hh"
#include "arch/alpha/alpha_common_syscall_emul.hh"
+#include "sim/syscall_emul.hh"
#include "sim/universe.hh" // for curTick & ticksPerSecond
#include "arch/alpha/alpha_linux_process.hh"
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index fbd4cfe60..e7d0d68ce 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -790,48 +790,14 @@ output header {{
protected:
/// Constructor
MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
- StaticInstPtr<AlphaISA> _eaCompPtr,
- StaticInstPtr<AlphaISA> _memAccPtr)
+ StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
+ StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
};
-
-
- /**
- * Base class for "fake" effective-address computation
- * instructions returnded by eaCompInst().
- */
- class EACompBase : public AlphaStaticInst
- {
- public:
- /// Constructor
- EACompBase(MachInst machInst)
- : AlphaStaticInst("(eacomp)", machInst, IntAluOp)
- {
- }
-
- %(BasicExecDeclare)s
- };
-
- /**
- * Base class for "fake" memory-access instructions returnded by
- * memAccInst().
- */
- class MemAccBase : public AlphaStaticInst
- {
- public:
- /// Constructor
- MemAccBase(MachInst machInst, OpClass __opClass)
- : AlphaStaticInst("(memacc)", machInst, __opClass)
- {
- }
-
- %(BasicExecDeclare)s
- };
-
}};
@@ -850,21 +816,6 @@ output decoder {{
}
}};
-output exec {{
- Fault
- EACompBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
- {
- panic("attempt to execute eacomp");
- }
-
- Fault
- MemAccBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
- {
- panic("attempt to execute memacc");
- }
-}};
-
-
def format LoadAddress(code) {{
iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
header_output = BasicDeclare.subst(iop)
@@ -885,21 +836,25 @@ def template LoadStoreDeclare {{
/**
* "Fake" effective address computation class for "%(mnemonic)s".
*/
- class EAComp : public EACompBase
+ class EAComp : public %(base_class)s
{
public:
/// Constructor
EAComp(MachInst machInst);
+
+ %(BasicExecDeclare)s
};
/**
* "Fake" memory access instruction class for "%(mnemonic)s".
*/
- class MemAcc : public MemAccBase
+ class MemAcc : public %(base_class)s
{
public:
/// Constructor
MemAcc(MachInst machInst);
+
+ %(BasicExecDeclare)s
};
public:
@@ -912,14 +867,17 @@ def template LoadStoreDeclare {{
}};
def template LoadStoreConstructor {{
+ /** TODO: change op_class to AddrGenOp or something (requires
+ * creating new member of OpClass enum in op_class.hh, updating
+ * config files, etc.). */
inline %(class_name)s::EAComp::EAComp(MachInst machInst)
- : EACompBase(machInst)
+ : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
%(ea_constructor)s;
}
inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
- : MemAccBase(machInst, %(op_class)s)
+ : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
%(memacc_constructor)s;
}
@@ -932,6 +890,64 @@ def template LoadStoreConstructor {{
}
}};
+
+def template EACompExecute {{
+ Fault
+ %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData)
+ {
+ Addr EA;
+ Fault fault = No_Fault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+
+ if (fault == No_Fault) {
+ %(op_wb)s;
+ xc->setEA(EA);
+ }
+
+ return fault;
+ }
+}};
+
+def template MemAccExecute {{
+ Fault
+ %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData)
+ {
+ Addr EA;
+ Fault fault = No_Fault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_nonmem_rd)s;
+ EA = xc->getEA();
+
+ if (fault == No_Fault) {
+ %(op_mem_rd)s;
+ %(code)s;
+ }
+
+ if (fault == No_Fault) {
+ %(op_mem_wb)s;
+ }
+
+ if (fault == No_Fault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == No_Fault) {
+ %(op_nonmem_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+
def template LoadStoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
@@ -1022,18 +1038,33 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
# Would be nice to autogenerate this list, but oh well.
valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
- inst_flags = []
- mem_flags = []
- for f in flags:
- if f in valid_mem_flags:
- mem_flags.append(f)
- else:
- inst_flags.append(f)
+ mem_flags = [f for f in flags if f in valid_mem_flags]
+ inst_flags = [f for f in flags if f not in valid_mem_flags]
+
+ # add hook to get effective addresses into execution trace output.
+ ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
+ # generate code block objects
ea_cblk = CodeBlock(ea_code)
memacc_cblk = CodeBlock(memacc_code)
postacc_cblk = CodeBlock(postacc_code)
+ # Some CPU models execute the memory operation as an atomic unit,
+ # while others want to separate them into an effective address
+ # computation and a memory access operation. As a result, we need
+ # to generate three StaticInst objects. Note that the latter two
+ # are nested inside the larger "atomic" one.
+
+ # generate InstObjParams for EAComp object
+ ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
+
+ # generate InstObjParams for MemAcc object
+ memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
+ # in the split execution model, the MemAcc portion is responsible
+ # for the post-access code.
+ memacc_iop.postacc_code = postacc_cblk.code
+
+ # generate InstObjParams for unified execution
cblk = CodeBlock(ea_code + memacc_code + postacc_code)
iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
@@ -1043,13 +1074,17 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
iop.memacc_code = memacc_cblk.code
iop.postacc_code = postacc_cblk.code
- mem_flags = string.join(mem_flags, '|')
- if mem_flags != '':
- iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
+ if mem_flags:
+ s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
+ iop.constructor += s
+ memacc_iop.constructor += s
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
- decode_template.subst(iop), exec_template.subst(iop))
+ decode_template.subst(iop),
+ EACompExecute.subst(ea_iop)
+ + MemAccExecute.subst(memacc_iop)
+ + exec_template.subst(iop))
}};
@@ -1460,8 +1495,8 @@ output header {{
/// Constructor
HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
- StaticInstPtr<AlphaISA> _eaCompPtr,
- StaticInstPtr<AlphaISA> _memAccPtr);
+ StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
+ StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
};
diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc
index 95c85b45a..22d65638b 100644
--- a/arch/alpha/pseudo_inst.cc
+++ b/arch/alpha/pseudo_inst.cc
@@ -206,7 +206,7 @@ namespace AlphaPseudo
void checkParams();
};
- Context context("PseudoInsts");
+ Context context("pseudo_inst");
Param<bool> __quiesce(&context, "quiesce",
"enable quiesce instructions",
diff --git a/arch/alpha/vptr.hh b/arch/alpha/vptr.hh
index cd4bc547b..e955c67cf 100644
--- a/arch/alpha/vptr.hh
+++ b/arch/alpha/vptr.hh
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __VPTR_HH__
-#define __VPTR_HH__
+#ifndef __ARCH_ALPHA_VPTR_HH__
+#define __ARCH_ALPHA_VPTR_HH__
#include "arch/alpha/vtophys.hh"
@@ -69,14 +69,15 @@ class VPtr
const VPtr<T> &operator+=(int offset)
{
ptr += offset;
- assert((ptr & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES);
+ assert((ptr & (AlphaISA::PageBytes - 1)) + sizeof(T)
+ < AlphaISA::PageBytes);
return *this;
}
const VPtr<T> &operator=(Addr p)
{
- assert((p & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES);
+ assert((p & (AlphaISA::PageBytes)) + sizeof(T) < AlphaISA::PageBytes);
ptr = p;
return *this;
@@ -110,4 +111,4 @@ class VPtr
}
};
-#endif // __VPTR_HH__
+#endif // __ARCH_ALPHA_VPTR_HH__