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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-24 23:37:28 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-24 23:37:28 -0700 |
| commit | 9508bf0a8706162d7f081dd4a0343ca572959210 (patch) | |
| tree | 48cb730eaf2cdfb7d6c2526008b9beeaf8d2a67c /arch/alpha | |
| parent | 47399b6c5e3f2b76ac934c4005726c913df0c218 (diff) | |
| parent | 2622601b836c413546fdbb12abcd6a3cec34c74b (diff) | |
| download | gem5-9508bf0a8706162d7f081dd4a0343ca572959210.tar.xz | |
Merge stever@zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG--
extra : convert_revision : 921d26b6fe29870fa532394b388bc0fe6cac183e
Diffstat (limited to 'arch/alpha')
| -rw-r--r-- | arch/alpha/ev5.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index cc33f6890..7330d7ce0 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -47,6 +47,11 @@ void AlphaISA::initCPU(RegFile *regs) { initIPRs(regs); + // CPU comes up with PAL regs enabled + swap_palshadow(regs, true); + + regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault]; + regs->npc = regs->pc + sizeof(MachInst); } void @@ -97,6 +102,7 @@ AlphaISA::initIPRs(RegFile *regs) bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); ipr[IPR_PAL_BASE] = PAL_BASE; + ipr[IPR_MCSR] = 0x6; } |