Merge zizzer.eecs.umich.edu:/bk/m5

into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest

--HG--
extra : convert_revision : 64eca6a11aeae236e802f9ca8eb97ca05d394ec7

1 files changed, 11 insertions, 13 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 8b95e8b3d..aa52916b9 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -101,17 +101,17 @@ AlphaISA::initIPRs(RegFile *regs)
 }
 
 
-template <class XC>
+template <class CPU>
 void
-AlphaISA::processInterrupts(XC *xc)
+AlphaISA::processInterrupts(CPU *cpu)
 {
     //Check if there are any outstanding interrupts
     //Handle the interrupts
     int ipl = 0;
     int summary = 0;
-    IntReg *ipr = xc->getIprPtr();
+    IntReg *ipr = cpu->getIprPtr();
 
-    check_interrupts = 0;
+    cpu->checkInterrupts = false;
 
     if (ipr[IPR_ASTRR])
         panic("asynchronous traps not implemented\n");
@@ -127,7 +127,7 @@ AlphaISA::processInterrupts(XC *xc)
         }
     }
 
-    uint64_t interrupts = xc->intr_status();
+    uint64_t interrupts = cpu->intr_status();
 
     if (interrupts) {
         for (int i = INTLEVEL_EXTERNAL_MIN;
@@ -143,22 +143,22 @@ AlphaISA::processInterrupts(XC *xc)
     if (ipl && ipl > ipr[IPR_IPLR]) {
         ipr[IPR_ISR] = summary;
         ipr[IPR_INTID] = ipl;
-        xc->trap(Interrupt_Fault);
+        cpu->trap(Interrupt_Fault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                 ipr[IPR_IPLR], ipl, summary);
     }
 
 }
 
-template <class XC>
+template <class CPU>
 void
-AlphaISA::zeroRegisters(XC *xc)
+AlphaISA::zeroRegisters(CPU *cpu)
 {
     // Insure ISA semantics
     // (no longer very clean due to the change in setIntReg() in the
     // cpu model.  Consider changing later.)
-    xc->xc->setIntReg(ZeroReg, 0);
-    xc->xc->setFloatRegDouble(ZeroReg, 0.0);
+    cpu->xc->setIntReg(ZeroReg, 0);
+    cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
 }
 
 void
@@ -220,8 +220,6 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
     // that's it! (orders of magnitude less painful than x86)
 }
 
-bool AlphaISA::check_interrupts = false;
-
 Fault
 ExecContext::hwrei()
 {
@@ -238,7 +236,7 @@ ExecContext::hwrei()
         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
             AlphaISA::swap_palshadow(&regs, false);
 
-        AlphaISA::check_interrupts = true;
+        cpu->checkInterrupts = true;
     }
 
     // FIXME: XXX check for interrupts? XXX