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authorNathan Binkert <binkertn@umich.edu>2005-06-28 12:42:15 -0400
committerNathan Binkert <binkertn@umich.edu>2005-06-28 12:42:15 -0400
commit036a8ceb8da8aff10b819b4aab32584d41282a64 (patch)
treee3d1c6bd8572ec503ff53e6b1b27bcd0f292f247 /arch/alpha
parentd172447a7ae945139d0c3465b8504cd6b77ae819 (diff)
downloadgem5-036a8ceb8da8aff10b819b4aab32584d41282a64.tar.xz
Don't hard code the location of m5AlphaAccess. Instead, move the
code into a function that can be called by the AlphaConsole class. AlphaConsole will pass in its address. arch/alpha/ev5.hh: Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable bits so that they will be converted correctly. dev/alpha_access.h: Do not hard code the location of the AlphaConsole dev/alpha_console.cc: fixup #includes tell the system where the alpha console is sim/system.hh: Provide a function that will tell the system where the AlphaAccess structure (device) lives --HG-- extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
Diffstat (limited to 'arch/alpha')
-rw-r--r--arch/alpha/ev5.hh10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 8508162ed..a5a76b5bd 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -58,6 +58,16 @@ const Addr PAddrUncachedBit39 = ULL(0x8000000000);
const Addr PAddrUncachedBit40 = ULL(0x10000000000);
const Addr PAddrUncachedBit43 = ULL(0x80000000000);
const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
+inline Addr Phys2K0Seg(Addr addr)
+{
+#ifndef ALPHA_TLASER
+ if (addr & PAddrUncachedBit43) {
+ addr &= PAddrUncachedMask;
+ addr |= PAddrUncachedBit40;
+ }
+#endif
+ return addr | AlphaISA::K0SegBase;
+}
inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
inline Addr DTB_PTE_PPN(uint64_t reg)