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authorNathan Binkert <binkertn@umich.edu>2003-10-28 10:05:58 -0500
committerNathan Binkert <binkertn@umich.edu>2003-10-28 10:05:58 -0500
commitcec7f73abf841a65bdce38d6eb67a643e4879335 (patch)
tree1c2fbce339a33ef5efc8e64a3f623482b04bb46e /arch/alpha
parent5cf0b0541b7536221643606e368bd0d0e530125a (diff)
downloadgem5-cec7f73abf841a65bdce38d6eb67a643e4879335.tar.xz
emulate callpal halt for non FULL_SYSTEM
in the process make m5_exit more generic arch/alpha/ev5.cc: arch/alpha/ev5.hh: There's no reason that this needs to be in an arch specific file arch/alpha/isa_desc: m5_exit -> SimExit Emulate callpal halt and cause the simulator to exit while we're at it, sort #includes sim/sim_events.cc: sim/sim_events.hh: move the m5_exit function here, renaming it to SimExit. Also Allow the caller to pass in the termination message. --HG-- extra : convert_revision : 54b43b17a412ab387b8672c27ef0b04fce10ee15
Diffstat (limited to 'arch/alpha')
-rw-r--r--arch/alpha/ev5.cc6
-rw-r--r--arch/alpha/ev5.hh2
-rw-r--r--arch/alpha/isa_desc18
3 files changed, 11 insertions, 15 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 7330d7ce0..ff1ecc4bf 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -54,12 +54,6 @@ AlphaISA::initCPU(RegFile *regs)
regs->npc = regs->pc + sizeof(MachInst);
}
-void
-m5_exit()
-{
- static SimExitEvent event("m5_exit instruction encountered");
-}
-
////////////////////////////////////////////////////////////////////////
//
// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 921aeb12d..aa3d7e226 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -9,8 +9,6 @@
#include "targetarch/isa_traits.hh"
-void m5_exit();
-
////////////////////////////////////////////////////////////////////////
//
//
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 89ec05c0e..ac6934fac 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -18,17 +18,17 @@ let {{
#include <fenv.h>
#endif
-#include "cpu/static_inst.hh"
#include "base/cprintf.hh"
#include "base/misc.hh"
-#include "cpu/full_cpu/op_class.hh"
-
#include "cpu/exec_context.hh"
-#include "cpu/simple_cpu/simple_cpu.hh"
-#include "cpu/full_cpu/spec_state.hh"
-#include "cpu/full_cpu/full_cpu.hh"
#include "cpu/exetrace.hh"
+#include "cpu/full_cpu/full_cpu.hh"
+#include "cpu/full_cpu/op_class.hh"
+#include "cpu/full_cpu/spec_state.hh"
+#include "cpu/simple_cpu/simple_cpu.hh"
+#include "cpu/static_inst.hh"
#include "sim/annotation.hh"
+#include "sim/sim_events.hh"
#ifdef FULL_SYSTEM
#include "targetarch/ev5.hh"
@@ -2356,6 +2356,10 @@ decode OPCODE default Unknown::unknown() {
#else
0x00: decode PALFUNC {
format EmulatedCallPal {
+ 0x00: halt ({{
+ if (!xc->misspeculating())
+ SimExit("halt instruction encountered");
+ }});
0x83: callsys({{ xc->syscall(); }});
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }});
@@ -2414,7 +2418,7 @@ decode OPCODE default Unknown::unknown() {
}}, No_OpClass);
0x20: m5exit({{
if (!xc->misspeculating())
- m5_exit();
+ SimExit("m5_exit instruction encountered");
}}, No_OpClass);
0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
0x40: resetstats({{